JPH07210106A - Equivalent pulse period invalidation discrimination circuit - Google Patents

Abstract

PURPOSE:To provide an equivalent pulse period invalidation discrimination circuit capable of correctly discriminating a frequency of a horizontal synchronizing signal by a horizontal frequency discrimination circuit. CONSTITUTION:When the frequency of the horizontal synchronizing signal is discriminated from a composite synchronizing signal in which an equivalent pulse is inserted into a vertical blanking period at the half period of the horizontal synchronizing signal by the horizontal frequency discrimination circuit A, horizontal frequency discrimination operation by the horizontal frequency discrimination circuit A is invalidated based on an output of a horizontal frequency discrimination invalidation period generation circuit 24 in the interval when the equivalent pulse detected by an equivalent pulse period detection decoder 23 exists, and the operation is prohibited by the output of a latch pulse enable circuit 25.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an equivalent pulse period invalidity discrimination circuit used in computer displays, monitor receivers and the like.

[0002]

2. Description of the Related Art Conventionally, a circuit shown in FIG. 3 has been used as a horizontal frequency discriminating circuit in a multi-scan type computer display or monitor receiver. FIG. 4 shows the signal timing.

The horizontal frequency discriminating circuit will be described below with reference to FIGS. 3 and 4. This circuit includes 11 edge detection / clock synchronization circuits, 12 horizontal frequency counters, 13 first stage data latches, 14 _{1 to} 14 _M M comparators, and 15 ₁ to 15 _{M M} comparators. It consists of components such as the next stage data latch.

First, the edge detection / clock synchronization circuit 11
Input a reference clock pulse signal (hereinafter abbreviated as CLK) to the clock terminal c11 and a horizontal synchronization signal (hereinafter abbreviated as HS) to the input terminal i11, thereby synchronizing the input HS from the edge of CLK. The following three types of horizontal sync edge signals are created. These are HS C
A signal synchronized with the rise of LK (hereinafter abbreviated as HS1) and a signal obtained by delaying HS1 by one CLK cycle (hereinafter referred to as H1).
S2) and a signal obtained by delaying HS1 by two CLK cycles (hereinafter abbreviated as HS3).

The horizontal frequency counter 12 inputs HS2 to the reset terminal R and CLK to the clock terminal c12. The horizontal frequency counter 12 is reset at the trailing edge of HS2, starts counting from 0, and counts until the next trailing edge of HS2. That is (N +
1) (N is a natural number) is counted. At this count point, the horizontal frequency counter 12 is reset and starts counting from 0 again.

The first stage data latch 13 has a clock terminal c.
HS1 is input to 13 and the count value of the horizontal frequency counter 12 is held at the time of falling of HS1. That is,
The horizontal frequency counter 12 is reset by the falling edge of HS2 to the value N two before (where N.times.CLK period.apprxeq.
Holds one cycle of the horizontal synchronizing signal).

In the M comparators 14 _{1 to} 14 _M of the _{first to Mth} comparators, the output terminal o13 of the first stage data latch 13 is connected to each input terminal i14, and the input first stage is input. The output value N of the data latch 13 is compared with each of the M comparison values, and the following horizontal frequency determination operation is performed. When the output of the horizontal frequency counter 12 is N (that is, the horizontal frequency F
H = 1 / (N × CLK cycle)), the output (represented by FH1 to FHm) of each comparator whose comparison value is less than N is High.
And the output of each comparator whose comparison value is N or more (FH1 to FH
Hm) is Low.

The M next-stage data latches 15 ₁ to 15 _M of the first next-stage data latch to the M-th next-stage data latch are
HS3 is input to each clock terminal c15, and each output terminal o1 of the _M comparators 14 _{1 to} 14 _M is input to each input terminal i15.
4 are connected, and each output value of the _M comparators 14 _{1 to} 14 _M is held as each output value (FHD1 to FHDm) of its own corresponding to these at the fall of HS3.

[0009]

In such a conventional horizontal frequency discriminating circuit, as shown in FIG. 5A, a vertical synchronizing signal is superimposed on a horizontal synchronizing signal (HS) such as a television signal. In the case of the sync signal, the equivalent pulse is inserted in the vertical blanking period at a half cycle of the horizontal sync signal (1/2 · H when the cycle of the horizontal sync signal is 1H). Therefore, in the equivalent pulse period in which the equivalent pulse is inserted, as shown in FIG. 5 (b), it is determined that the horizontal synchronizing frequency (2fh) is twice the actual horizontal synchronizing frequency (fh) during the normal determination operation. When the discriminating operation is abnormal, the horizontal synchronizing frequency cannot be discriminated correctly, and there is a problem that a circuit connected to such a horizontal frequency discriminating circuit malfunctions.

The present invention is an equivalent pulse period invalidity discriminating circuit capable of correctly discriminating the frequency of a horizontal synchronizing signal by a conventional horizontal frequency discriminating circuit even for a composite synchronizing signal containing an equivalent pulse such as a television signal. The purpose is to provide.

[0011]

In order to achieve the above object, an equivalent pulse period invalidity discrimination circuit of the present invention is a composite circuit in which a vertical synchronizing signal is superimposed on a horizontal synchronizing signal and an equivalent pulse is inserted in a vertical blanking period. In a receiver having a function of discriminating the frequency of the horizontal synchronizing signal from the synchronizing signal by the horizontal frequency discriminating circuit, an edge detecting / horizontal synchronizing signal synchronizing circuit for detecting an edge of the vertical synchronizing signal and synchronizing with the horizontal synchronizing signal, Based on the output of the edge detection / horizontal synchronization signal synchronization circuit and the horizontal synchronization signal, a vertical frequency counter that counts the cycle of the horizontal synchronization signal for each cycle of the vertical synchronization signal, and based on the count value of the vertical frequency counter hand,
An equivalent pulse period detection decoder that detects an equivalent pulse period corresponding to this count value, and a horizontal period that generates an invalid period of the horizontal synchronizing frequency determination operation of the horizontal frequency determination circuit based on the output of the equivalent pulse period detection decoder. A frequency discrimination invalid period generating circuit; and a latch pulse enable circuit for inhibiting the discrimination operation of the horizontal synchronizing frequency based on the output of the horizontal frequency discriminating invalid period generating circuit. It is configured to assist the determination operation.

[0012]

According to this structure, when the horizontal frequency discriminating circuit discriminates the frequency of the horizontal synchronizing signal from the composite synchronizing signal in which the equivalent pulse is inserted at a half cycle of the horizontal synchronizing signal in the vertical blanking period. During the period when the equivalent pulse exists, the horizontal frequency discriminating circuit invalidates the horizontal frequency discriminating operation and prohibits this operation.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of the present invention will be described below with reference to FIGS.
Will be described with reference to. FIG. 1 shows a horizontal frequency discrimination circuit A.
6 is a block diagram of an equivalent pulse period invalidity determination circuit of the present embodiment with respect to FIG. FIG. 2 is a timing chart of signals of respective parts of the equivalent pulse period invalidity judgment circuit of this embodiment.

In FIG. 1, reference numeral 21 is an edge detection / horizontal synchronization signal synchronization circuit for detecting an edge of a vertical synchronization signal (hereinafter abbreviated as VS) and synchronizing with the horizontal synchronization signal, and 22 is V.
A vertical frequency counter that counts S in units of horizontal synchronization signals, 23 is an equivalent pulse period detection decoder that detects an equivalent pulse period based on the count value, and 24 is a horizontal frequency determination that is invalid based on the value of the equivalent pulse period detection decoder 23. A horizontal frequency discrimination invalid period generation circuit for producing a period for which the switch is turned on, and 25 is a latch pulse enable circuit for operating and stopping the horizontal frequency discriminating circuit A. Since the configuration and operation of the horizontal frequency discriminating circuit A are the same as the conventional ones, the description thereof is omitted here.

The operation of the equivalent pulse period invalidity discrimination circuit having the above components will be described below. First, the edge detection / horizontal synchronization signal synchronization circuit 21
The VS input to the vertical circuit is input, and a vertical edge signal (hereinafter abbreviated as VS1) of the horizontal synchronization edge signals from the horizontal frequency determination circuit A that is synchronized with the rise of HS2 is created.

The vertical frequency counter 22 is reset at the fall of VS1, counts from 0 to L (L is a natural number) every one cycle based on HS2, and outputs this count value (hereinafter abbreviated as FVC). .

The equivalent pulse period detection decoder 23 outputs the following decode values (hereinafter abbreviated as D1 and D2) corresponding to the FVC based on the FVC from the vertical frequency counter 22. D1 is set to High only during the period (n + k), which is the value before the start of the equivalent pulse period of FVC, and is output as the frequency discrimination stop detection signal. Also, D2
Is kept High only during a period of n, which is a value after the end of the equivalent pulse period, and is output as a frequency discrimination start detection signal.

The horizontal frequency discrimination invalid period generating circuit 24 is
It is composed of a flip-flop and is set at the rising edge of D2 and reset at the rising edge of D1. That is, a signal (hereinafter, abbreviated as FHN) is output such that most of the period without the equivalent pulse is High and the period including the other equivalent pulse periods is Low.

The latch pulse enable circuit 25 has an FH
A signal (hereinafter abbreviated as HSNO) obtained by ANDing N with HS1 of the horizontal synchronizing edge signal from the horizontal frequency discrimination circuit A is output. By inputting this HSNO to the clock terminal c13 of the first stage data latch 13 of the horizontal frequency discrimination circuit A, the latch of FHC which is the output of the horizontal frequency counter 12 of the horizontal frequency discrimination circuit A is prohibited and the horizontal frequency discrimination operation is stopped. A period of time is generated.

By the above operation, the conventional horizontal frequency discriminating circuit can correctly discriminate the frequency of the horizontal synchronizing signal even for a composite synchronizing signal containing an equivalent pulse such as a television signal.

[0021]

As described above, according to the present invention, in the horizontal frequency discriminating circuit, the horizontal sync signal is converted from the composite sync signal in which the equivalent pulse is inserted at the half cycle of the horizontal sync signal in the vertical blanking period. When discriminating the frequency, the horizontal frequency discriminating operation can be disabled and prohibited during the period when the equivalent pulse exists.

Therefore, the conventional horizontal frequency discriminating circuit can correctly discriminate the frequency of the horizontal synchronizing signal even for a composite synchronizing signal containing an equivalent pulse such as a television signal.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an equivalent pulse period invalidity determination circuit according to an embodiment of the present invention.

FIG. 2 is a timing chart of an equivalent pulse period invalidity determination circuit of the same embodiment.

FIG. 3 is a block diagram of a conventional horizontal frequency discrimination circuit.

FIG. 4 is a timing chart of the horizontal frequency discrimination circuit of the conventional example.

FIG. 5 is an operation explanatory diagram of a decoding frequency signal of the horizontal frequency discrimination circuit of the conventional example.

[Explanation of symbols]

 21 edge detection / horizontal synchronization signal synchronization circuit 22 vertical frequency counter 23 equivalent pulse period detection decoder 24 horizontal frequency discrimination invalid period generation circuit 25 latch pulse enable circuit

Claims (1)

[Claims] 1. A receiver having a function of discriminating the frequency of a horizontal synchronizing signal by a horizontal frequency discriminating circuit from a composite synchronizing signal in which a vertical synchronizing signal is superimposed on a horizontal synchronizing signal and an equivalent pulse is inserted in a vertical blanking period. An edge detection / horizontal synchronization signal synchronization circuit that detects an edge of the vertical synchronization signal and synchronizes with the horizontal synchronization signal; and a vertical synchronization signal based on the output of the edge detection / horizontal synchronization signal synchronization circuit and the horizontal synchronization signal. A vertical frequency counter for counting the cycle of the horizontal synchronizing signal for each cycle of, and an equivalent pulse period detection decoder for detecting an equivalent pulse period corresponding to the count value of the vertical frequency counter,
A horizontal frequency discrimination invalid period generation circuit for generating an invalid period of the horizontal synchronizing frequency discrimination operation of the horizontal frequency discrimination circuit based on the output of the equivalent pulse period detection decoder;
A latch pulse enable circuit for prohibiting the discrimination operation of the horizontal synchronization frequency based on the output of the horizontal frequency discrimination invalid period generation circuit, and an equivalent pulse for assisting the discrimination operation of the horizontal synchronization frequency of the horizontal frequency discrimination circuit. Period invalidity determination circuit.