KR960004129B1 - Programmable vertical sync. separation circuit - Google Patents

Abstract

The circuit is for detecting a synchronous signal from the compound signal by using a program. The circuit comprises a register(1) for latching 1H line pixel data, a frequency divider(2) for dividing 1H line duration by using pixel clock signal and output signal of the register(1), an up/down counter(3) for counting output signal of the divider(2), a first counter value detector(6) for discriminating that the counter value is a first counter value, a second counter value detector for discriminating that the counter value is a second value, and a vertical synchronous signal generator for generating a vertical synchronous signal by operating output signal of the frequency divider and the detectors.

Description

Programmable Vertical Sync Signal Extraction Circuit

1 is a programmable vertical synchronizing signal extraction circuit according to the present invention;

2 is a timing diagram of the present invention.

* Explanation of symbols for main parts of the drawings

1: register 2: divider

3: up / down counter 4: flip-flop

6: 225 detection gate 9,10,11,12 178 detection gate

PCK: Pixel Clock C-sync: Composite Synchronous Signal

V-sync: Vertical Sync Signal

The present invention relates to a programmable vertical synchronous signal extraction circuit for extracting a vertical synchronous signal from a composite synchronous signal with a program without changing the fixed hardware.

In video cassette recorders or color televisions, the conventional technique for separating the vertical synchronization signal from the composite synchronization signal has been separated using fixed hardware. If the number of pixels for the 1H line of the monitor is wrong, the corresponding hardware is reset again. It had to be constructed.

Accordingly, the present invention has been invented in view of the above circumstances, and it is possible to program the vertical synchronization signal from the composite synchronization signal without any hardware change by using the pixel clock according to the number of pixels of one scan line of the monitor. The purpose is to provide a vertical synchronization signal extraction circuit.

The present invention for achieving this object is a programmable vertical synchronous signal extraction circuit for detecting a vertical synchronous signal in a composite synchronous signal, comprising: a register for latching a data value corresponding to the number of pixels of a 1H line; A divider for dividing a 1H line section using a pixel clock and a register output; An up / down counter for performing up / down counting using the divided output and the composite synchronous signal; First count value detection means for logically combining the outputs of the counters to detect whether the value of the counter is a first value; Second count value detecting means for logically combining the output of the counter to detect whether the value of the counter is a second value; second count value detecting means for detecting whether the value of the counter is a second value by logically combining the output of the counter Over: Operate with the first count value or the second count value as the data input and the output of the divider as the clock signal, but keep the vertical synchronization signal high when the second count value is input, and the second counter value When inputted, the vertical synchronization signal generation means is configured to convert the vertical synchronization signal to the low state.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

1 is a schematic diagram of a programmable vertical synchronizing signal extraction circuit according to the present invention. The present invention is to program a vertical synchronizing signal between vertical synchronizing signals included in a composite synchronizing signal in a color television of any type. (1) latches the data obtained by dividing the 1H line immediately by the pixel clock PCK, and the upper 5 bits of this register 1 are loaded to the initial value of the 128 divider 2. The 128 divider 2 outputs the divided signal through the output terminal OUT using the pixel clock PCK which is a clock of the divider 2. By the way, the basic unit of the image displayed on the monitor is composed of pixels, and the pixel clock is such that the pixels are appropriately placed with respect to the length of one scan line of the monitor. Therefore, the data latched in the register 1 becomes the clock number of the required pixel clock per 1H. Therefore, the output frequency of the carry signal of the 128 divider 2 is 128 times that of 1H. The divider 2 reloads the initial value every time the carry output is enabled to proceed down counting synchronized with the pixel clock PCK.

The output of the 128 divider 2 is used as a clock signal of the up / down counter 3 and the flip-flop 4 which is the final output terminal. The up / down counter 3 performs an up or down count according to the state of the composite synchronous signal C-sync. As shown in the timing diagram of FIG. 2, the up / down counter 3 becomes a low in the synchronous period. Since the down input of 3) is made high by the inverter 5, the up / down counter 3 performs down counting, and in the video line section, the composite synchronous signal becomes high, so the up input becomes high and up counts. Will be performed.

As shown in the timing diagram of the present invention, when the up / down counter 3 starts up counting at the start of the video section of the 1H line, the relationship of the 1H line with respect to the 128-division clock is 10 clocks in the sync section and 118 in the video section. When divided by the clock, the counter 3 has a value of 117 in the section ending with the start of the video section.

Again, as the synchronization section of the next 1H line starts, the counter 3 performs down counting to have a value of 107 at the end of the synchronization signal section. Consequently, in the normal 1H line section, the increase rate of the up count is much higher than the increase rate of the down count. Since the counter 3 counts high, the maximum value of 225 is reached. Here, the output (Q7, Q6, Q5, Q4, Q3, Q2, Q1, Q0) of the up / down counter 3 is applied to the input terminal of the AND gate 6, so that the count value of the counter 3 is 225. In other words, when all outputs of the counter 3 become "1", the output of the AND gate 6 also becomes "1", and the output of the AND gate 6 is flip-flop 4 through the oragate 7. Is applied to the D-input terminal, and the flip-flop 4 causes the vertical synchronization signal to be low.

In addition, when the value of the counter 3 reaches 225, the signal Scup of the counter 3 becomes 1, which is connected to the hold input terminal Hold of the counter 3 via the oragate 8. Is applied to cause the counter 3 to maintain its current value.

When the synchronization section of the next 1H line starts again, the counter 3 performs down counting, but in this case, the outputs of the counter 3 (Q6, Q3, Q2, Q0) are provided at one input terminal of the AND gates 9-12. Are applied to the other input terminal, and a high vertical sync signal output from the positive output terminal Q of the flip-flop 4 is applied to the other input terminal. However, when the value of the counter 3 does not become 178 or less when the vertical synchronization signal V-sync output from the sub-output terminal Q of the flip-flop 4 is low, the AND gates 9 and 10 , 11, 12) output is always high and the vertical synchronization signal is kept low. If the value of the counter 3 is 178, the state of each bit of the counter 3 is Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 = 10110010, and the outputs Q6, Q3, Q2, and Q0 all turn low. This is because any one of the four bits Q6, Q3, Q2, and Q0 is necessarily "1" except for this value.

As can be seen from FIG. 2, the ratio of the down count of the counter 3 in this section in the waveform of FIG. 2 (b) to the vertical section of the composite synchronization signal (FIG. It is much larger than the ratio, so that the value of the counter 3 continues to fall in this section, and before the end of 1H, the count reaches 178, where all of the end gates 6, 9, 10, 11, and 12 Since the output becomes "0", when the vertical synchronization signal (Fig. 2 (c)) becomes high, one input of the AND gates 9, 10, 11, and 12 (i.e., the positive output of flip-flop 4) becomes low. Even if the output value of the count 3 becomes less than or equal to 177, the vertical synchronization signal remains high.

However, when the vertical synchronization signal falls low again, the normal 1H line starts after the vertical section of the composite synchronization signal C-sync ends, and when the value of the counter 3 increases to 225, the AND gate ( It is the time when all the inputs of 6) become "1" and the output of the AND gate 6 becomes "1".

As described above, when the total number of pixels of the 1H line of the monitor is known, the present invention writes the register data and extracts the vertical synchronous signal from the composite synchronous signal without any hardware change using an appropriate pixel clock. I have it.

Claims (1)

A programmable vertical synchronous signal extraction circuit for detecting a vertical synchronous signal from a composite synchronous signal, comprising: a register for latching a data value corresponding to the number of pixels of a 1H line; A divider for dividing the 1H line section using the pixel clock and the register output; An up / down counter for performing up / down counting by using the output of the divider and the composite synchronization signal; First count value detecting means for logically combining the outputs of the up / down counters to detect whether the value of the counter is a first value; Second count value detecting means for logically combining the outputs of the up / down counters to detect whether the value of the counter is a second value; The first count value or the second count value is used as a data input and the output of the divider is used as a clock signal. When the first count value is input, the second sync count is maintained while the vertical synchronization signal is kept high. And a vertical synchronizing signal generating means for converting the vertical synchronizing signal into a low state when a value is inputted.