KR970003795B1 - Digital source image-signal change device using the number of pixel and line - Google Patents

Abstract

A digital component video signal converter converts a digital video signal of CCIR 656 type to a CCIR 601 type being a digital component video signal, by using a combination between a pixel and a line address number. The digital component video signal converter includes: a hamming decoder for receiving a video signal of CCIR 656 type, and outputting a decoded output and a multiplexing control signal; a hamming decoder controller for providing an enable signal of the hamming decoder; a multiplexer for selecting one between the hamming decoder and the CCIR 656 type video signal; 1st and 2nd flip-flops for delaying the output signal of the multiplexer by two clocks, and outputting a color signal; a 3rd flip-flop for delaying the output signal of the multiplexer by two clocks, and outputting a brightness signal; a pixel counter for receiving a horizontal and vertical signal and timing signal, and outputting a pixel address; a pixel decoder for outputting a horizontal synchronizing signal, a horizontal reference signal, even word and odd word of a pixel, decoder enable signal, and a reset signal of the pixel counter; an initial pulse generator for receiving an inverted F-bit from a timing reference signal decoder, and outputting a line counter enable signal; a line counter for outputting a line address according the enable signal of the initial pulse generator; and a line decoder for receiving a horizontal reference signal from the pixel decoder and the line address from the line counter, and outputting a vertical synchronizing signal.

Description

Digital element video signal converter using a combination of pixel and line address

1 is a connection diagram of the peripheral device of the present invention,

2 is an arrangement diagram of words in a line;

3 is a configuration diagram of a timing reference signal;

4 is an arrangement diagram of an image signal in a frame;

5 is a block diagram according to the present invention,

6 is a waveform diagram of HSYNC and HREF,

7 is a waveform diagram of VSYNC,

8 is a configuration diagram of a VSYNC generation circuit (line decoder) of the present invention.

* Description of the symbols for the main parts of the drawings *

3: Hamming decoder 4: Hamming decoder control circuit

5: multiplexer 10: timing reference signal decoder

11, 13, 14: first to third multiplexer 27: pixel counter

23: initial pulse generating circuit 28: line counter

31: pixel decoder 32: line decoder

The present invention relates to a conversion apparatus for converting a digital image signal of the CCIR 656 format into a CCIR 601 format that is a digital component video signal using a combination of a pixel and a line address.

Currently, domestic TV broadcasting uses the analog television system, NTSC (National Television System Committee), but it plans to use a digital system that can easily store and edit information. In addition, the CCIR 656 format is used for information compatibility when communicating between digital imaging equipment internationally. When connected to a digital NTSC encoder within an NTSC TV decoder, it can receive and display 656-format digital video signals from an existing TV decoder using NTSC. Also, it can be used for video display for the monitor function of TV encoder. It is available.

The digital video signal of the 4: 2: 2 method is 8 bits (or 10 bits) in which C (Cb, Cr), which is a chroma component and 1716 words per line, which is a luminance component, is Cb, Y, It is transmitted in the order of Cr and Y, and End of Active Video (EAV) for notifying the end of the active video signal and SAV (Start of Active Video) for the start are transmitted in 4 words as shown in FIG. 3. The timing reference signals EAV and SAV are configured as shown in FIG. 2 in the line, and the word of the blanking interval transmits 20h when Y and 80h when C.

Therefore, the present invention inputs a CCIR 656 image signal to find the value of the timing reference signal from the signal, and operates the pixel and line counter using this value to use a combination of the pixel and line address, which is the output signal of the counter. It is an object of the present invention to provide an apparatus for converting a 656 signal into a synchronization signal and data of CCIR 601.

In order to achieve the above object, the present invention provides a Hamming decoder that receives a CCIR 656 format video signal and outputs a decoded output and a multiplexing control signal. A hamming decoder control circuit for providing a first signal; A second flip-flop, a third flip-flop for delaying the output of the multiplexer by one clock to output a luminance signal, a timing for outputting horizontal and vertical signals, an F-bit, and a pixel counter in-table signal by receiving the output of the multiplexer A pixel counter that receives a signal and outputs a pixel address, and a pixel address output by the pixel counter A pixel decoder for receiving a horizontal register signal, a horizontal reference signal, odd and even words of a pixel, a decoder enable signal, a reset signal of the pixel counter, and an inverted F bit from the timing reference signal decoder An initial pulse generation circuit for outputting a counter enable signal, a line counter for outputting a line address in accordance with an enable signal from the initial pulse generation circuit, a horizontal reference signal from the pixel decoder, and a line from the line counter And a line decoder for receiving an address and outputting a vertical synchronization signal.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;

1 is a configuration diagram of the connection with the peripheral device of the present invention.

A 656 video signal is input to the apparatus of the present invention to output a 601 signal (Y, C) and a synchronous signal of two channels, and are input to the digital NTSC encoder. A digital NTSC encoder converts the input signal into an NTSC analog video signal for display on an NTSC analog TV monitor.

Figure 2 shows the arrangement of words in a line. The 656 signal consists of 1716 words and is in the sequence Cb0, Y0, Cr0, Y1 .... In addition, the SAV and EAV signals, which are timing reference signals, are located at the positions shown in FIG. 2 to indicate the start and end of the active region of the video signal.

3 shows an arrangement of timing reference signals. The timing reference signals EAV and SAV are each composed of 4 words, and are composed of a header of FFh, 00h, and 00h and a fourth word of actual information to indicate that the timing reference signal is a timing reference signal. The fourth word consists of a signal indicating the positions of the active and blanking regions, the positions of the filter 1 (ODD) and the filter 2 (EVEN) in the line or frame, and four bits of error protection bits for correct transmission thereof.

4 is a spatial representation of a timing reference signal to represent an arrangement of video signals within a frame. One frame consists of two fields, and when changed to another field, it goes through a vertical blanking interval of 9 (or 19) lines. At the start of each line, there is a horizontal blanking section of 273 (1443-1715) pixel sections, in which case 10h is transmitted at Y and 80h at C.

5 is a circuit of an apparatus for converting a CCIR 656 signal into a CCIR 601 signal for input to a digital NTSC encoder using two channels (Y, C) of the CCIR 601 system.

C656 (1), which is a 656-format data signal, is input to the Hamming decoder 3, Hamming decoder control circuit 4, and MUX 5 of FIG. In (4), when the fourth word of the timing reference signal, that is, the word after the header, HENB (inverting Hamming decoder enable) 8, which is 0, is generated and input to (3). In (3), when (8) is 0, the decoding operation is performed to search for an error, and when an error is found, HOUT (Hamming decoder output) (6), which is a signal corrected and corrected, and MUXC (MUX control), which is 1 (7) Generate and enter in (5). (5) is (1) when the selection signal (7) is 0, and (1) when the selection signal is 1, and through the terminal H656 (9), the timing reference signal decoder 10, flip-flop 1 (11), and flip-flop 3 ( 13). The 656 signal modified by the Hamming decoder (9) is separated into two clock delayed Cs (15) and one flip-flop (13) by one clock delayed Y (16). The two-channel 601 signals (15) and (16) are output in the order of Cb0, Cr0, Cb1, Cr1 ... and Y0, Y1, Y2, Y3, ..., respectively.

In (10), H, V, and F bits of the timing reference signals are detected and output through the H (17), V (18), and F (19) terminals, respectively. In addition, a PENB (inversion of the pixel counter enable) 20, which is 0, is generated and inputted to the pixel counter 27 at the moment when the EAV signal is generated in one line of the video signal. Also, at this moment, a clock reference (CREF) 21, which is 0 and is twice the clock signal of CLK (Clock) 2, is output for use in a digital NTSC encoder.

In (27), when (20) is 0, the counter is operated in accordance with the address number of the video signal by inputting 1443, which is the variable number at this time, to PINT (Pixel initial) (25). A PA (Pixel address) 29, which is an output signal of (27), is input to the pixel decoder 31 to decode the value to generate necessary signals.

6 shows waveforms of a horizontal sync (HSYNC) 33 and a horizontal reference (HREF) 34 among the output signals of (31). (34) indicates whether or not the active area in the line (33), such as VSYNC (Vertical sync) (38) can vary the interval and the generated position of each synchronization signal according to the characteristics of the digital NTSC. The DENB (inversion of data enable) 36 is a clock signal capable of outputting the 601 output signals Y (16) and C (15) of the present invention at a speed of 13,5 MHz. PCRSB (Pixel counter reset inversion) 37 becomes 0 when the value of 29 is 1715, allowing 27 to operate as a 1716 (0-1715) counter.

7 shows a waveform of VSYNC (Vertical sync) 38. Since the pixel address number generated by VSYNC is different from each other in the field 1 and the field 2, PODD and PEVEN 35, which are 0, are generated and input to the line decoder 32, respectively.

LEB which becomes 0 for one period of (40) from the rising time of (22) by inputting the FB (23) which is the inversion signal of F and the HREFB (40) which is the inversion signal of (34) to the initial pulse generation circuit (23). (Inversion of Line counter enable) 24 is generated and input to the line counter 28. When (24) is 0, the line counter 28 is initialized to the value of LINT (Line counter initial) 26. In (26), input the line number of video signal +1 when (24) is 0. In (22), it is 1 when the line number is 3, as shown in FIG. Initialize the counter to match the address of the video signal. A line address (LA) 30, which is an output signal of (28), is input to the line decoder 32, and as a result, the input 35 decodes (35) input from (31) to generate a necessary signal. LCRSB (Inversion of Line Counter Reset) 39 becomes zero when the value of 30 is 524, allowing 28 to operate as a 525 (0-524) counter.

8 shows a circuit for generating VSYNC 38. When PODD input in (31) is 0 and (28) is 2, (8-1) is reset to 0, and when PODD is 0 and (28) is 5, it is set to 1 to generate a vertical synchronization signal of field 1. Also, when PEVEN is 0 and (28) is 265, (8-2) is reset to 0, and PEVEN is 0 and (28) sets (8-2) to 1 to generate the vertical sync signal of the filter 2. When the vertical synchronization signals of the fields 1 and 2 are inputted to the AND gate and outputted, VSYNC, which is the vertical synchronization signal of FIG.

Accordingly, the present invention, which is constructed and operated as described above, is designed by referring to CCIR Recommendation 656 so that the CCIR Recommendation 656 format video signal can be used as an input of a digital NTSC encoder. It can be received from a TV decoder and displayed on an analog monitor.

Claims (1)

A decoder (3) receiving a CCIR 656 format video signal and outputting a decoded output and a multiplexing control signal, and receiving an CCIR 656 format video signal to provide an enable signal of the Hamming decoder (3) The Hamming decoder control circuit 4, a multiplexer 5 which receives the Hamming decoder 3 and a CCIR 656 type video signal, selects one of them, and outputs one of them, and outputs the output of the Milter multiplexer 5. First and second flip-flops 11 and 14 for delaying the output of the color signal, a third flip-flop 13 for outputting the luminance signal by delaying the output of the multiplexer 5 by one clock, and the multiplexer ( A timing reference signal decoder 10 that receives the output of 5) and outputs horizontal and vertical signals, an F bit and a pixel counter enable signal, and an enable signal from the timing reference signal decoder 10 to receive a pixel address; Pixel count to output And a pixel address output from the pixel counter 27 to output a horizontal synchronization signal, a horizontal reference signal, odd and even words of the pixel, a decoder enable signal, and a reset signal of the pixel counter. From the pixel decoder 34, the initial pulse generator circuit 23 for receiving the inverted F bit from the timing reference signal decoder 10 and outputting a line counter enable signal, and from the initial pulse generator circuit 23. A line counter 28 for outputting a line address in accordance with an enable signal, a horizontal reference signal from the pixel decoder 31, and a line address from the line counter 28 to output a vertical synchronization signal; And a decoder (32).