KR970003796B1 - Digital source image-signal change device using the number of pixel and line - Google Patents

Abstract

The digital component video signal converter comprises: a first multiplexor(4) for selecting one of two CCIR 601 channel signals(Y,C); a first initial pulse generating circuit(9) for generating a pixel counter enable signal; a pixel counter(15) for outputting a pixel address; a pixel decoder(17) for decoding the pixel address to output even and odd words in a vertical blacking interval, a reset signal of the pixel counter(15), and a decoding output signal; a second initial pulse generating circuit(12); a line decoder(24); a main decoder(27); and a second multiplexor(31) for outputting a CCIR 656 signal in accordance with a multiplexing control signal.

Description

Digital element video signal converter using a combination of pixel and line address

1 is a block diagram of the peripheral device of the present invention,

2 is an arrangement diagram of words in a line;

3 is a configuration diagram of a timing reference signal;

4 is an arrangement diagram of an image signal in a frame;

5 is a block diagram according to the present invention,

6 is a timing diagram of an image signal and a control signal in a line;

7 is a timing diagram of an image signal and a control signal in a frame;

8 is an output signal display diagram of a pixel decoder used in the present invention;

9 is an output signal display diagram of the line decoder used in the present invention;

10 is a configuration diagram of a timing reference signal and blanking data according to the number of pixels and lines;

* Description of the symbols for the main parts of the drawings *

4,30: multiplexer 9,12: initial pulse generating circuit

22: line counter 24: line decoder

15: pixel counter 17: pixel decoder

27: main decoder

The present invention relates to an apparatus for converting a CCIR 601 format signal, which is a digital component video signal, into a CCIR 656 format using a combination of a pixel and a line address number.

Currently, it uses NTSC (National Television System Committee) method, which is an analog method of TV broadcasting in Korea, but it is going to use digital method that is easy to store and edit information. In addition, CCIR 656 format is used for information compatibility when communicating between digital video equipments internationally. In order to use existing NTSC signals in digital video equipments in domestic television studios, CCIR 601 / CCIR 656 conversion circuits must be used.

The digital video signal of the 4: 2: 2 method is 8 bits (or 10 bits) in which C (Cb, Cr), which is a chroma component and 1716 words per line, which is a luminance component, is Cb, Y, It is transmitted in the order of Cr and Y, and End of Active Video (EAV) indicating the end of the active video signal and SAV (Start of Active Video) indicating the start are transmitted in 4 words as shown in FIG. 3. The timing reference signals EAV and SAV are configured as shown in FIG. 2 in the line, and the word of the blanking interval transmits 10h when Y and 80h when C.

The circuit of the present patent is realized by considering that the 656 signal has the same value according to the number of pixels and lines as shown in FIG.

Accordingly, an object of the present invention is to provide an apparatus for converting a video signal of CCIR 601 into a video signal of CCIR 656 by using a combination of pixels and line address numbers.

In order to achieve the above object, the present invention provides a first multiplexer which receives a CCIR 601 two-channel signal (Y, C) and selects one of the channels, and receives a horizontal signal (HREF) and a pixel counter enable signal. A first blanking pulse generating circuit, a pixel counter which receives an enable signal from the first seeding pulse generating circuit, outputs a pixel address, and decodes the pixel address from the pixel counter during vertical blanking period; A pixel decoder for outputting an even word and an odd word, a reset signal of the pixel counter, and a decoding output signal, a second initial pulse generator circuit for receiving an inverted signal of an odd word and a horizontal signal and outputting a line counter enable signal; A line counter which receives an enable signal from the second initial pulse generating circuit and outputs a line address; A line decoder for decoding a line address and outputting a reset signal and a decoding output signal of a line counter, a main decoder for decoding outputs of the line decoder and the pixel decoder and outputting a multiplexing control signal and blanking data, and the first multiplexer And a second multiplier for receiving a blanking data from the main decoder and outputting a CCIR 656 format signal according to a multiplexing control signal provided from the main decoder.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;

1 is a configuration diagram of the connection with the peripheral device of the present invention.

The NTSC digital decoder inputs an NTSC analog video signal, outputs a CCIR 601 signal (Y, C) and a synchronization signal, and inputs it to a CCIR601 / CCIR656 conversion circuit which is a device of the present invention. In the apparatus of the present invention, the 601 signal is converted into a 656-format video signal so as to interface with a digital video device capable of receiving the 656 signal.

Figure 2 shows the arrangement of words in a line.

The 656 signal consists of 1716 words, in the order Cb0, Y0, Cr0, Y1 .... Also, the SAV and EAV signals, which are timing reference signals, are located at the positions shown in FIG. 2 to indicate the start and end of the active region of the image signal.

3 shows an arrangement of timing reference signals.

Each of the timing reference signals EAV and SAV is composed of four words, and is composed of a header of FFh, 00h, and 00h and a fourth word representing actual information to indicate that the timing reference signal is a timing reference signal. The fourth word consists of a signal indicating the position of the active area and the blanking area, the positions of the Field 1 (ODD) and the Field 2 (EVEN) in the line or frame, and the 4-bit error protection bit for the correct transmission thereof.

4 is a spatial representation of a timing reference signal to represent an arrangement of video signals within a frame.

One frame consists of two fields, and when changed to another field, it goes through a vertical blanking interval of 9 (or 19) lines. At the start of each line, there is a horizontal blanking section of the 273 (1443-1715) pixel section. In this case, 20h is transmitted in Y and 80h is transmitted in C.

5 is a block diagram of a conversion apparatus according to the present invention for converting the CCIR 601 format to the CCIR 656 format using the output of a digital decoder operating in two channels (Y, C), and FIG. A timing diagram of a control signal.

Input the Y (1) and C (2) output signals of the 2-channel digital decoder to the multiplexer 1 (4; hereinafter referred to as MUX1) and use the CREF (Clock reference) 3 as the selection signal of the MUX1 (4). If CREF (3) is 0, Y (1) is output, and if C1 (1) is 1, C (2) is output to generate C601 (5), which is a one-channel CCIR 601 signal. Input the HREF (Horizontal reference) (7) and CLK (Clock) (6) to the initial pulse generation circuit 1 (9), and 0 is reset for one period of the CLK (6) from the rising time of the HREF (7) as shown in FIG. A PENB (inversion of the pixel counter enable) 10 is generated and input to the pixel counter 15. 7 shows timings of an image signal and a control signal in a frame.

In addition, an ODD (Odd field) 11 and an HREFB (8), which is an inverted signal of the HREF (7), are inputted to the initial pulse generating circuit 2 (12) for one cycle of the HREFB (8) from the rising time of the ODD (11). A LENB (inverting line counter enable) 13 that becomes 0 is generated and input to the line counter 22. In FIG. 7, in order to accurately indicate the position of the line in the frame, instead of the digital signal (5), the analog video signal is represented as a continuous video baseband signal (CVBS).

When the PENB 10 is 0, the pixel counter 15 is initialized to the value of PINT (Pixel counter initial) 14. In the PINT 14, the pixel number of (5) when the input signal of the multiplexer 2 (30 (hereinafter referred to as MUX2)) is " difference between (5) and BLD (Blanking data) 29 " and " 10 " You must enter a sum of +1 ". In order to reduce the delay difference between the output terminals and use the flip-flop at two places (17) and (27) for correct operation, two clocks are delayed, so the difference between (5) and (29) is 2. If (10) is 0 when the signal of HREF (7) is generated and the number of lines is 0, 3 should be input to "2+ (0 + 1)", that is, (14).

In addition, when (13) is 0, the line counter 22 is initialized to the value of LINT (Line counter initial) 21. In (21), input the line number +1 of (5) when (13) is 0. That is, when the signal of the ODD 11 is generated at the position as shown in FIG. 7 and the number of lines of (5) is 10, if (13) is 0, 11 should be input to "10 + 1", that is, 21.

The three decoders 17, 24, and 27 can also use PAL (Programmable Array Logic) to reduce the delay difference between each output terminal and to allow easy design.

8 shows the output of the pixel decoder. In the pixel decoder 17, addresses within a line are classified as shown in FIG. 8 by a combination of the PA (Pixel address) 16 inputted from (15), and the signals, (19) and (20), respectively, are line decoders ( 24) and the main decoder 27. Also, to enable (15) to operate as a 1716 (0-1715) counter, PCRSB (reverse of Pixel counter reset) 18, which is 0 when the value of (16) is 1715, is used as the reset signal of (15).

9 shows the output of the line decoder. The line decoder 24 classifies the addresses in one frame by the combination of the LA (Line address) 23 input from the 22, and inputs the signal 26 to the 27. The timing reference signal is generated according to the number of lines as shown in FIG. 3 and can be classified as shown in FIG. 9 because the even pixels EVEN-BL and odd pixels ODD-BL have different data even in the vertical blanking period. Also, in order to allow (22) to operate as a 525 (0-524) counter in the same way as in (17), set LCRSB (Inversion of Line counter reset) (25) equal to 0 when the value of (23) is 524 ( It is used as a reset signal in 22).

10 shows words of timing reference signals and blanking data classified according to pixel and line address numbers. Words of the data and the timing reference signal in the blanking area are determined by the number of pixels and lines, and the values of the respective positions can be known by the third and fourth degrees. By using a combination of (2), which corresponds to the pixel address, and (26), which corresponds to the line address, you can design a circuit that can generate BLD (Blanking data) 29, which is the same word as in FIG. Generate MUXCB (inverting the mux control) (28) and input it to MUX2 (30). In (30), if the selection signal (28) is 0, it is (29), and if it is 1, C656 (31) which is a CCIR 656 type signal of (5) can be obtained.

Accordingly, the present invention, which is configured and operated as described above, is a hardware implementation such that a signal input from an NTSC digital decoder that outputs a CCIR Recommendation 601 video signal (in 656 format) can be output with reference to CCIR Recommendation 656. Enables communication with digital imaging equipment capable of receiving video signals and reception.

Claims (1)

CCIR 601 First multiplexer 4 which receives two channels (Y, C) and selects one of them and outputs the first multiplexer 4, and a first initial pulse generating circuit which receives a horizontal signal HREF and generates a pixel counter enable signal. (9), a pixel counter 15 for receiving the enable signal from the first initial pulse generating circuit 9 and outputting a pixel address; and decoding the pixel address from the pixel counter 15 to form a vertical column. A second pixel outputting a line counter enable signal by receiving an even word and an odd word, a pixel decoder 17 for outputting a reset signal and a decoding output signal of the pixel counter, and an inverted signal of an odd word and a horizontal signal during a blanking period; A line counter 22 for receiving an enable signal from the initial pulse generating circuit 12, the second initial pulse generating circuit 12 and outputting a line address, and a line address from the line counter 22. Deco A line decoder 24 which outputs the reset signal and the decoded output signal of the line counter 22, and outputs the multiplexing control signal and the blanking data by decoding the outputs of the line decoder 24 and the pixel decoder 17. The main decoder 27, the output of the first multiplexer 4, and the blanking data from the main decoder 27, and according to the multiplexing control signal provided by the main decoder 27, in a CCIR 656 format. And a second multiplexer (31) for outputting a signal.