KR950023001A

KR950023001A - Digital element video signal converter using a combination of pixel and line address

Info

Publication number: KR950023001A
Application number: KR1019930030025A
Authority: KR
Inventors: 이진환; 김용한; 권동현
Original assignee: 양승택; 재단법인 한국전자통신연구소
Priority date: 1993-12-27
Filing date: 1993-12-27
Publication date: 1995-07-28
Also published as: KR970003796B1

Abstract

본 발명은 CCIR(International Radio Consultative Committee) 권고안 601을 출력하는 디지탈 디코더로부터 입력된 신호를 CCIR 권고안 656을 참고하여 CCIR 656형식으로 출력 할 수 있도록 하드 웨어로 구현한 것이다.The present invention is implemented in hardware so that the signal input from the digital decoder that outputs the International Radio Consultative Committee (CCIR) Recommendation 601 can be output in CCIR 656 format with reference to CCIR Recommendation 656.

본 발명은 NTSC 디지탈 디코더로 부터 받은 601 신호를 656 형식으로 변환하여 656형식의 데이타와 통신이 가능한 디지탈 영상장비에 연결하여 사용할 수 있다.The present invention can be used by converting a 601 signal received from an NTSC digital decoder into a 656 format and connecting to a digital imaging apparatus capable of communicating with the 656 format data.

Description

Digital element video signal converter using a combination of pixel and line address

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명의 주변장치와의 구성도,1 is a block diagram of the peripheral device of the present invention,

제2도는 라인 내에서 워드의 배열 구성도,2 is an arrangement diagram of words in a line;

제3도는 타이밍 기준 신호의 구성도,3 is a configuration diagram of a timing reference signal;

제4도는 프레임 내에서 영상 신호의 배열 구성도,4 is an arrangement diagram of an image signal in a frame;

제5도는 본 발명에 따른 구성도,5 is a block diagram according to the present invention,

Claims

First multiplexer 4 for receiving CCIR 601 two-channel signals (Y, C) and selecting one of the channels, and outputting a first counter pulse for receiving a horizontal counter (FREF) and generating a pixel counter enable signal. A pixel counter 15 that receives an enable signal from the first initial pulse generator circuit 9 and outputs a pixel address, and decodes the pixel address from the pixel counter 15 A pixel decoder 17 for outputting an even word and an odd word, a reset signal of the pixel counter, and a decoding output signal during a vertical blanking period, and an inverted signal of an odd word and a horizontal signal, and outputting a line counter enable signal; 2 an initial pulse generating circuit 12, a line counter 22 for receiving an enable signal from the second initial pulse generating circuit 12 and outputting a line address, and a line address from the line counter 22; To A line decoder 24 that decodes and outputs the reset signal and the decoded output signal of the line counter 22, and outputs the multiplexing control signal and the blanking data by decoding the outputs of the line decoder 24 and the pixel decoder 17. The main decoder 27, the output of the first multiplexer 4, and the blanking data from the main decoder 27, and according to the multiplexing control signal provided by the main decoder 27, in a CCIR 656 format. And a second multiplexer (31) for outputting a signal.

※ Note: The disclosure is based on the initial application.