KR970060912A

KR970060912A - Video signal conversion device

Info

Publication number: KR970060912A
Application number: KR1019960001730A
Authority: KR
Inventors: 이광재
Original assignee: 구자홍; 엘지전자 주식회사
Priority date: 1996-01-26
Filing date: 1996-01-26
Publication date: 1997-08-12
Also published as: KR100186529B1

Abstract

본 발명은 각종 영상기기에서 출력되는 NTSC 방식의 영상신호를 PAL(Phase Alternation by Line) 방식의 신호로 변환하는 장치에 관한 것으로 특히, 듀얼포트 램을 사용하여 리얼타임으로 변환시키는 영상신호 변환장치에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for converting an NTSC video signal output from various video apparatuses into a PAL (Phase Alternation by Line) signal, and more particularly, .

본 발명의 영상신호 변환장치는 NTSC 방식의 복합영상 신호를 아날로그 R,G,B신호로 디코딩 하는 아날로그디코더와, 상기 NTSC 방식의 복합영상 신호로 부터 수평 및 수직동기 신호를 분리하는 동기신호 분리기와, 상기 동기신호 분리기로 부터 입력되는 수평동기 신호를 분리하여 화소클럭을 발생하는 클럭 발생기와, 상기 화소클럭에 동기하여 아날로그 R,G,B 신호를 각각 일정 디지털 신호로 변환하는 A/D 변환부와, 상기 디지털 신호로 변환된 R,G,B 신호를 저장하는 듀얼포트 램과, 상기 디지털 R,G,B 신호가 상기 듀얼포트 램에 쓰여질 어드레스를 발생시키는 라이트 어드레스 발생기와, 상기 듀얼포트 램으로 부터 저장된 R,G,B 신호를 출력시키기 위해 어드레스를 발생시키는 리드 어드레스 발생기와, 상기 듀얼포트 램으로 부터 출력된 디지털 R,G,B 신호를 아날로그 신호로 변환시키는 D/A 변환부와, 상기 아날로그 R,G,B 신호를 PAL 방식의 복합영상 신호로 엔코딩하여 출력하는 아날로그 엔코더로 구성됨에 특징이 있다.The video signal conversion apparatus of the present invention includes an analog decoder for decoding an NTSC composite video signal into analog R, G, and B signals, a sync signal separator for separating horizontal and vertical sync signals from the NTSC composite video signal, A clock generator for generating a pixel clock by separating a horizontal synchronizing signal input from the synchronizing signal separator, an A / D converter for converting analog R, G, B signals into a predetermined digital signal in synchronization with the pixel clock, A dual port RAM for storing R, G and B signals converted into the digital signals; a write address generator for generating an address to which the digital R, G and B signals are to be written to the dual port RAM; A read address generator for generating an address for outputting stored R, G, B signals from the dual port RAM; On the day D / A conversion unit for converting into analog signals, adapted to the analog R, G, B signals to an analog encoder for encoding the output of a composite video signal of the PAL system is characterized.

따라서, 현재 PAL방식을 방송 규격으로 채택하고 있는 국가에서도 PAL방식의 영상기기에서 NTSC 방식의 다양한 영상화면을 사용할 수 있는 이점이 있다.Therefore, even in a country where the PAL system is adopted as a broadcasting standard, there is an advantage that various video screens of the NTSC system can be used in the PAL system.

Description

Video signal conversion device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is a trivial issue, I did not include the contents of the text.

제1도는 본 발명에 따른 영상신호 변환장치의 구성블럭도.FIG. 1 is a block diagram of a video signal conversion apparatus according to the present invention; FIG.

제2도는 본 발명에 따른 라이트 어드레스 발생기의 상세 구성블록도.FIG. 2 is a detailed block diagram of a write address generator according to the present invention; FIG.

제3도는 본 발명에 따른 리드 어드레스 발생기의 상세 구성블럭도.FIG. 3 is a detailed block diagram of a read address generator according to the present invention; FIG.

Claims

An analog decoder for decoding an NTSC composite video signal into analog R, G, and B signals; a synchronous signal separator for separating receipt and vertical synchronization signals from the NTSC composite video signal; An A / D converter for converting the analog R, G, and B signals into a predetermined digital signal in synchronization with the pixel clock; A dual port RAM for storing R, G, and B signals; a write address generator for generating addresses to which the digital R, G, and B signals are to be written to the dual port RAM; A D / A converter for converting digital R, G, and B signals output from the dual port RAM into analog signals; Video signal conversion device, characterized by consisting of a unit and the analog R, G, B analog encoder for encoding and outputting the signal as a composite video signal of the PAL system.

2. The dual-port RAM according to claim 1, wherein the write address generator comprises: a first counter section for counting a pixel clock and outputting a 9-bit count output as a column address of a write address of the dual port RAM; An AND gate for outputting a horizontal synchronizing signal, a half dividing signal and a half dividing signal for outputting a horizontal synchronizing signal and a half dividing signal for outputting a low pulse, And a second counter for outputting the count output as a row address of the write address of the dual port RAM.

2. The apparatus of claim 1, wherein the read address generator includes: a PAL sync generator for generating horizontal and vertical sync signals of a PAL system by counting pixel clocks; a low pulse generator for generating a low pulse once every 12 periods of the vertical sync signal to reset the PAL sync generator A first counter section for counting a pixel clock and outputting a binary count of 9 bits as a column address of a read address of a dual port RAM; A horizontal synchronous signal of the PAL system, and an AND gate and a PAL system which counts the horizontal synchronous signal of the PAL system and the two-divided and single-stage outputs and outputs it to the clear input terminal of the first counter unit and outputs a binary count of 9 bits A second counter section, a 6-minute period for outputting a clock by dividing the horizontal synchronous signal of the PAL system by 6, and a 6-minute period for counting the output of the 6-minute period, Third counter unit, and a video signal conversion apparatus of the second counter portion and the characteristics of the car 3 consists counter subtraction unit group for outputting in a read address of the row address of the dual port RAM to the agent output.

※ Note: It is disclosed by the contents of the first application.