JPH02246685A - Synchronous signal generator - Google Patents

Abstract

PURPOSE:To prevent the disturbance of the synchronization of character generation by preventing an input synchronizing signal from passing through with a gate circuit during both a period from the leading edge of the output of a synchronism generation circuit to the detection of a horizontal synchronism leading edge and the period from the trailing edge of the output of a switch to the trailing edge of the output of the synchronism generation circuit. CONSTITUTION:The output of the gate circuit 29 among the input synchronizing signals passes through only during the period when a synchronism generating flip flop 27 is reset. Therefore, even when false synchronism exists in the input synchronizing signal, it does not appear in the output of the gate circuit. Namely, the synchronizing signal to be outputted to an output terminal 32 falls down slightly before the leading edge of the horizontal synchronism of the input synchronizing signal and rises up at the trailing edge of the horizontal synchronism. Then, even when a pseudo synchronous signal exists in the input synchronizing signal, it is not outputted, and when dropout exists in the horizontal synchronism of the input synchronizing signal, the output of the synchronism generating flip flop 27 is outputted as substitute for it. Accordingly, even if the pseudo synchronous signal is added, the output is not influenced.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a synchronization signal generation device for superimposing characters on the screen of a video signal reproducing device such as a video disc player.

2. Description of the Related Art In recent years, video signal reproducing devices such as video disc players have become popular. In particular, these video signal playback devices display the operating status of the device, the location being played, the time, etc. by inserting characters into the playback screen (generally called superimpose or on-screen display). Increasingly, there are many products with added functions. The biggest problem in realizing this character insertion function is the synchronization signal generator that is input to the character generation circuit, and the synchronization signal generator is equipped with various protection methods against loss of synchronization due to dropouts, etc. has been devised.

An example of the above-mentioned conventional synchronization signal generation device will be described below with reference to the drawings.

FIG. 6 is a block diagram showing the configuration of a conventional synchronization signal generator. In the figure, 1 is an input terminal, 2 is a horizontal synchronization leading edge edge detection circuit, 3 is a counter, 4 is a first decoder, 6 is a second decoder, 6 is a third decoder, 7 is a synchronization generation flip-flop, and 8 9 is a negative OR circuit, 9 is a gate circuit, 10 is a first flip-flop, 11 is a switch, and 12 is an output terminal.

The operation of the conventional synchronizing signal generator configured as described above will be explained below.

A negative polarity synchronization signal is input to the input terminal 1 .

The horizontal synchronization leading edge detection circuit 2 detects the horizontal synchronization leading edge edge of the synchronization signal input to the input terminal 1 and generates a negative pulse. The output of the horizontal synchronization leading edge edge detection circuit 2 is input to a negative OR circuit 8. The output of the negative OR circuit 8 is input to the reset input of the counter 3. The counter 3 is reset by the output of the negative OR circuit 8 and counts the clock input.

The first decoder 4 generates a pulse when the output of the counter 3 reaches a constant value, and inputs the pulse to the reset input of the synchronization generation flip-flop 7 and the set input of the first flip-flop 1o. The second decoder 6 generates a Halless signal when the output of the counter 3 reaches a constant value, and inputs it to the cent input of the synchronization generation flip-flop 7. The third decoder 6 generates a pulse when the output of the counter 3 reaches a constant value,
It is input to one input of the negative OR circuit 8. The output of the synchronization generation flip-flop 7 is input to the a input of the switch 11 and simultaneously input to the gate circuit 9. An input synchronization signal is input to the other input of the gate circuit 9, and its output is connected to the reset input of the first flip-flop,
It is input to the b input of switch 11. The switch 11 is
It is switched by the output of the first flip 70 knob 1o, and the output is outputted to the outside through the output terminal 12.
Used for timing control of external character generation circuit.

FIG. 6 shows the operation of a synchronization generation flip-flop in a conventional synchronization signal generation device.

In FIG. 6, the input synchronization signal input to input terminal 1,
The output of the horizontal synchronization leading edge edge detection circuit 2, the output of the negative OR circuit 8, the output of the first decoder 4, the output of the second decoder 6, the output of the third decoder 6, and the synchronization generation The time relationship of the output of the flip-flop 7 is shown over approximately one horizontal scanning period. As shown in FIG. 6, the pulse generation position of the first decoder 4 is set slightly before the next horizontal synchronization signal, and the pulse generation position of the second decoder 6 is set slightly after the next horizontal synchronization signal. , and the pulse generation position of the third decoder 6 is set at the leading edge of the next horizontal synchronizing signal. Therefore, as shown in the figure, the output of the synchronization generation flip-flop 7 falls slightly before the next horizontal synchronization signal and rises slightly after it.

If the horizontal synchronization signal in the input synchronization signal shown in FIG. 8 is missing due to a dropout or the like as shown by the dotted line, the horizontal synchronization leading edge detection circuit 2 will not operate, but instead, The pulse of the third decoder 6 causes the counter 3 to
is reset, there is no change in the output of the synchronization generation flip-flop 7. That is, the synchronous generation flip-flop 7
The output is a signal in which loss of the synchronization signal due to dropout etc. has been compensated for.

FIG. 7 is a diagram showing the operation of a conventional synchronization signal generator.

As shown in the figure, the output of the gate circuit 9 passes through the input synchronization signal only during the period when the synchronization generation flip-flop 7 is reset, so if there is false synchronization in the input synchronization signal (at the point indicated by A in the figure) ) does not appear in the gate circuit output. The first flip 7o tube 10 is set by the output of the first decoder 4 and reset by the output of the gate circuit 9. If there is a loss in horizontal synchronization of the input synchronization signal (B in the figure)
1), the first flip-flop 1o is not reset. Now, in FIG. 7, the switch 11 is the first
When the first flip-flop 1o is set, it is set to the a side, and when the first flip-flop 1o is reset, it is set to the b side, so the output terminal output becomes as shown in the figure.

That is, the synchronization signal output to the output terminal 12 falls slightly before the leading edge of the horizontal synchronization of the input synchronization signal, and rises at the trailing edge of the horizontal synchronization. Even if there is a false synchronization signal in the input synchronization signal, it is not output, and if there is a lack of horizontal synchronization in the input synchronization signal, the output of the synchronization generating flip-flop 7 is output instead.

Only when there is a lack of horizontal synchronization in the input synchronization signal, the output of the synchronization generation flip-flop 7 is output instead, and normally it falls just υ before the leading edge of the horizontal synchronization of the input synchronization signal, causing horizontal synchronization. The reason why it is set to rise at the trailing edge of is to establish a synchronization relationship between the character signal generated by the character generation circuit and the input synchronization signal.

That is, the signal generated by the synchronization generation flip-flop 7 is generated by the counter 3 counting its input clock, and when comparing the input synchronization signal and the output of the synchronization generation flip-flop 7, it is determined that the signal is generated by the input clock frequency. There is a variation (jitter) in the time being determined. Since the synchronization of the PACKGROUND screen where characters are inserted matches the synchronization of the input synchronization signal, when the output of the synchronization generating flip-flop is always output from the output terminal 12, the characters to be inserted will be inserted by the amount of jitter described above. There is a problem with shaking on the playback screen. Generally, in a character generation circuit, the character position is determined by the rising edge of its input synchronization signal. Therefore, only when there is a lack of horizontal synchronization in the input synchronization signal, the output of the synchronization generation flip-flop 7 is substituted. is output to
Normally, it is set so that it falls slightly before the leading edge of the horizontal synchronization of the input synchronizing signal and rises at the trailing edge of the horizontal synchronization.

FIG. 8 is a diagram showing the operation of the horizontal synchronizing signal section of the conventional synchronizing signal generator.

Problems to be Solved by the Invention However, in the synchronization signal generator having such a configuration,
While the synchronization generation flip-flop 7 is being reset, all synchronization signals input to the input terminal are passed through and output to the output terminal 12. Therefore, as shown in Figure 8,
Even if a synchronization signal is input due to noise etc. while the synchronization generation flip-flop 4 is being reset, it cannot be compensated for.
As a result, there was a drawback that the synchronization of character generation was disrupted.

The present invention provides a synchronization signal generator that eliminates the above-mentioned drawbacks.

Means for Solving the Problems In order to solve the above problems, the synchronization signal generation device of the present invention includes a synchronization edge detection circuit that detects the horizontal synchronization leading edge of the input synchronization signal, and a synchronization edge detection circuit that detects the horizontal synchronization leading edge of the input synchronization signal. a sync generation circuit that generates a horizontal sync signal with a period in which the leading edge is before the horizontal sync leading edge of the input sync signal and the trailing edge is after the horizontal sync trailing edge of the input sync signal; A gate circuit that gates the input synchronization signal with a gate signal and a synchronization generation circuit that are not in the set state at the leading edge of the horizontal synchronization signal generated by the gate signal, and are in the reset state at the leading edge of the horizontal synchronization signal of the gate circuit output synchronization signal. When the first flip-flop and the first flip-flop are in the set state, the first flip-flop outputs the synchronization generating circuit output, and the first flip-flop
When the flip-flop is in the reset state, there is a switch that outputs the gate circuit output, and a second switch that is set at the trailing edge of the synchronization edge of the switch output and reset at the leading edge of the horizontal synchronization signal that generates the output of the synchronization edge detection circuit. a flip-flop, an output of a second flip-flop,
Outputs the logical sum of the outputs of the synchronization signal generation participant circuit, and outputs the input synchronization signal to the gate circuit (7) when the synchronization signal generation circuit is not generating a synchronization signal and when the second flip-flop is in the set state. and an OR circuit that inputs a gate signal to the gate circuit so that the gate signal does not occur.

Operation In the present invention, with the above-described configuration, the period from the leading edge of the output of the synchronization generation circuit until the synchronization edge detection circuit detects the leading edge of horizontal synchronization of the input synchronization signal, and the trailing edge of the switch output. By using a gate circuit to prevent the input synchronization signal from passing between the edge and the trailing edge of the synchronization generator output, even if a false synchronization signal due to noise etc. is added during the above period, the output will not be affected. It becomes possible to provide a synchronization signal generator.

Embodiment Hereinafter, a synchronization signal generator according to an embodiment of the present invention will be described.
This will be explained with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a synchronization signal generator according to an embodiment of the present invention.

In the figure, 21 is an input terminal, 22 is a horizontal synchronization leading edge edge detection circuit, 23 is a counter, 24 is a first decoder,
26 is a second decoder, 26 is a third decoder, 27 is a synchronization generation flip-flop, 28 is a negative OR circuit, 29
is a gate circuit, 30 is a first flip-flop, 31 is a switch, 32 is an output terminal, 33 is a first OR circuit,
34 is a trailing edge detection circuit, 36 is a second flip-flop, and 36 is a second OR circuit.

The operation of the conventional synchronizing signal generator configured as described above will be explained below.

A negative polarity synchronization signal is input to the input terminal 21 . The horizontal sync leading edge detection circuit 22 detects the horizontal sync leading edge of the sync signal input to the input terminal 21 and generates a negative pulse. The output of the horizontal synchronization leading edge edge detection circuit 22 is input to a negative OR circuit 28. The output of the negative OR circuit 28 is input to the reset input of the counter 23. The counter 23 is reset by the output of the negative OR circuit 28 and counts the clock input. The first decoder 24 generates a pulse when the output of the counter 23 reaches a constant value, and inputs the pulse to the reset input of the synchronization generation flip-flop 27 and the set input of the first flip-flop 3o. The second decoder 26 generates a pulse when the output of the counter 23 reaches a constant value, and inputs the pulse to the set input of the synchronization generation flip-flop 27 .

The third decoder 2e generates a pulse when the output of the counter 23 reaches a constant value, and inputs the pulse to one input of the negative OR circuit 28. The output of the synchronization generation flip-flop 27 is input to the d input of the switch 31 and simultaneously input to the second OR circuit 36. The output of the second flip-flop 36 is connected to the other input of the second OR circuit 36, and the output of the second OR circuit 36 is connected to the gate circuit 2.
9 input. An input synchronizing signal is input to the other input of the gate circuit 29, and its output is connected to the reset input of the first flip-flop 30 and the b input of the switch 31. The switch 3 is switched by the output of the first flip-flop 30, and the output is outputted to the outside through the output terminal 32 and used for timing control of an external character generation circuit.

FIG. 2 shows the operation of the synchronization generation flip-flop in the synchronization signal generation device of the present invention.

In FIG. 2, the input synchronization signal input to the input terminal 21, the output of the horizontal synchronization leading edge edge detection circuit 22, the output of the negative OR circuit 28, the output of the first decoder 24, and the second
The time relationship between the output of the decoder 26, the output of the third decoder 26, and the output of the synchronization generation flip-flop 27 is expressed as follows:
The figure is shown over one horizontal scanning period.

As shown in the figure, the pulse generation position of the first decoder 24 is set slightly before the next horizontal synchronization signal, and the pulse generation position of the second decoder 26 is set slightly after the next horizontal synchronization signal. The pulse generation position of the third decoder 2e is set at the leading edge of the next horizontal synchronizing signal.

Therefore, the output of the synchronization generation flip-flop 27 falls slightly before the next horizontal synchronization signal, as shown in the figure.
Sumire stands up behind her.

If the input synchronization signal in FIG. 2 is missing a horizontal synchronization signal due to dropout or the like as shown by the dotted line, the horizontal synchronization leading edge detection circuit 22 does not operate, but instead Since the counter 23 is reset by the pulse from the decoder 26 of No. 3, there is no change in the output of the synchronization generation flip-flop 27. In other words, the output of the synchronization generation flip-flop 27 is a signal in which the loss of synchronization signals due to dropouts and the like has been compensated for.

FIG. 3 is a diagram showing the operation of the embodiment of the synchronization signal generator of the present invention.

As shown in the figure, the output of the gate circuit 29 passes through the input synchronization signal only during the period when the synchronization generation flip-flop 27 is reset, so if there is false synchronization in the input synchronization signal (at the point indicated by A in the figure) ) does not appear in the gate circuit output. The first flip-flop 30 is set by the output of the first decoder 24 and reset by the output of the gate circuit 29. If there is a loss in horizontal synchronization of the input synchronization signal (point indicated by B in the figure), the first flip-flop 30
is not reset. Now, in Figure 3, switch 3
1 is set to the a side when the first flip-flop 3o is set, and is set to the b side when the first flip-flop 3o is reset, so the output terminal output is shown in FIG. It will be like that.

That is, the synchronization signal output to the output terminal 32 falls i times before the leading edge of the horizontal synchronization of the input synchronization signal, and rises at the trailing edge of the horizontal synchronization. Even if there is a false synchronization signal in the input synchronization signal, it is not output, and if there is a lack of horizontal synchronization in the input synchronization signal, the output of the synchronization generating flip-flop 27 is output instead.

Only when there is a lack of horizontal synchronization in the input synchronization signal, the output of the synchronization generation flip-flop 27 is output instead,
Normally, the input synchronization signal is set to fall slightly before the leading edge of the horizontal synchronization signal and rise at the trailing edge of the horizontal synchronization signal, which is synchronized with the character signal generated by the character generation circuit and the input synchronization signal. This is to establish a relationship.

That is, the signal generated by the synchronization generation flip-flop 27 is generated by the counter 23 counting its input clock, and when the input synchronization signal and the output of the synchronization generation flip-flop 2 are compared, the input clock is There is a time variation (jitter) that is determined by the frequency in °C. Since the synchronization of the background screen on which characters are inserted matches the synchronization of the input synchronization signal, when the output of the synchronization generation flip-flop 2T is always output from the output terminal 32, the characters to be inserted will be inserted by the amount of jitter described above. There is a problem with shaking on the playback screen. Generally, in a character generation circuit, the character position is determined by the rising edge of the input synchronization signal, so only when there is a lack of horizontal synchronization of the input synchronization signal, the output of the synchronization generation flip-flop 2 is output instead. Normally, the setting is such that the input synchronization signal falls just before the old edge of horizontal synchronization and rises at the trailing edge of horizontal synchronization.

FIG. 4 is a diagram showing the operation of the horizontal synchronizing signal section of the synchronizing signal generator according to the embodiment of the present invention.

As shown in the figure, the second flip-flop 36 is set by the output of the first decoder 24 and the output of the trailing edge detection circuit 34, and is reset by the output of the horizontal synchronization leading edge detection circuit 22. As shown in the figure, the second OR circuit 36 opens the gate of the gate circuit 29 only from the horizontal synchronization leading edge of the input synchronization signal to the trailing edge of the output synchronization signal, and closes the gate at other times. Output seeds. Therefore, as shown in the figure, the synchronization generation flip-flop 27
Even if a false synchronization signal is input due to noise or the like while the synchronization generating flip-flop 4 is being reset, it will be gated by the gate circuit 29 and will not be output.

As described above, one embodiment of the present invention includes an input terminal, a horizontal synchronization leading edge edge detection circuit, and a counter.

a first decoder, a second decoder, a third decoder, a synchronous generation flip-flop, a negative OR circuit, a gate circuit, a first flip-flop, a switch,
By providing an output terminal, a first OR circuit, a trailing edge edge detection circuit, a second flip-flop, and a second OR circuit, the horizontal synchronization leading edge of the input synchronization signal can be detected. By outputting a seed that opens the gate of the gate circuit only until the trailing edge of the output synchronization signal and closes the gate otherwise, it is possible to prevent false synchronization signals from being generated due to noise etc. while the synchronization generation flip-flop is being reset. It is possible to provide a synchronization signal generator that is gated by a gate circuit and is not output even if it is input.

Effects of the Invention As described above, the synchronization signal generating device of the present invention includes a synchronization edge detection circuit that detects the horizontal synchronization leading edge edge of the input synchronization signal, and a synchronization edge detection circuit that detects the horizontal synchronization leading edge edge of the input synchronization signal. A sync generation circuit that generates a horizontal sync signal whose edge is before the horizontal sync leading edge of the input sync signal and whose trailing edge is after the horizontal sync trailing edge of the input sync signal; a gate circuit for gating the signal; a first flip-flop that is set to a set state at the leading edge of the horizontal synchronization signal generated by the synchronization generation circuit; and a first flip-flop that is set to the reset state at the leading edge of the synchronization signal output from the gate circuit; a switch that outputs a synchronization generation circuit output when the first flip-flop is in a set state and outputs a gate circuit output when the first flip-flop is in a reset state; and a switch that is set at the synchronization trailing edge of the switch output; A second flip-flop that is reset at the front edge of the horizontal synchronization signal generated by the output of the synchronization edge detection circuit; and a logical sum of the output of the second flip-flop and the output of the synchronization signal generation circuit; Synchronization is achieved by providing an OR circuit that inputs the gate signal to the gate circuit so that the input synchronization signal is not output to the gate circuit when the second flip-flop is not generating a synchronization signal and when the second flip-flop is in the set state. From the leading edge of the generator output until the synchronous edge detection circuit detects the horizontal synchronous leading edge of the input synchronous signal, and from the trailing edge of the switch output to the trailing edge of the synchronous generator output, By preventing the input synchronization signal from passing through using the gate circuit, it is possible to provide a synchronization signal generating device that does not affect the output even if a false synchronization signal due to noise or the like is added during the above period.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a synchronization signal generation device according to an embodiment of the present invention, and FIG. 2 is a waveform diagram showing the operation of a synchronization generation flip-flop in the synchronization signal generation device of the present invention.
FIG. 3 is a waveform diagram showing the operation of the synchronizing signal generator according to the embodiment of the present invention, FIG. The figure is a block diagram showing the configuration of a conventional synchronization signal generator.
FIG. 6 is a waveform diagram showing the operation of the synchronization generation flip-flop in the conventional synchronization signal generator, FIG. 7 is a waveform diagram showing the operation of the conventional synchronization signal generation device, and FIG. 8 is the synchronization signal of the conventional example. FIG. 3 is a waveform diagram showing the operation in the horizontal synchronization signal section of the generator. 21...Input terminal, 22...Horizontal synchronization leading edge edge detection circuit, 23...Counter, 24
...First decoder, 26... Second decoder, 26... Third decoder, 27...
...Synchronous generation flip-flop, 28...
Negative OR circuit, 29... Gate circuit, 30...
...First flip-flop, 31...Switch, 32...Output terminal, 33...First
34... trailing edge detection circuit;
36... Second flip-flop, 36...
...Second OR circuit.

Claims (1)

[Claims] a synchronization edge detection circuit for detecting a horizontal synchronization leading edge of an input synchronization signal; , a synchronization generation circuit that generates a horizontal synchronization signal whose trailing edge is after the horizontal synchronization trailing edge of the input synchronization signal; a gate circuit that gates the input synchronization signal with a gate signal; a first flip-flop that is set to a set state at the leading edge of the horizontal synchronizing signal output from the gate circuit and reset to a reset state at the leading edge of the synchronizing signal output from the gate circuit; and when the first flip-flop is in the set state, a switch that outputs a synchronization generation circuit output and outputs the gate circuit output when the first flip-flop is in a reset state;
a second flip-flop that is set at the trailing edge of the synchronization edge of the switch output and reset at the leading edge of the horizontal synchronization signal generated by the output of the synchronization edge detection circuit; outputting a logical sum of the outputs of the synchronization signal generation circuit, and not outputting an input synchronization signal to the gate circuit when the synchronization signal generation circuit is not generating a synchronization signal and when the second flip-flop is in a set state; 1. A synchronous signal generating device comprising: an OR circuit for inputting a gate signal to the gate circuit.