JPS60111577A - Vertical synchronizing device - Google Patents

Abstract

PURPOSE:To continue to have synchronizing at a regular timing and to improve synchronization at the time of a weak electric field by generating a reset signal immediately after a window is closed when a vertical synchronizing signal does not exist at the inside of the window, and by discriminating the reset signal from the regular television signal. CONSTITUTION:A frequency equivalent to 2 times that of a horizontal synchronizing signal from a clock input terminal 1 is inputted to a dividing circuit 2 and a delay circuit 15. The output of the pulse width of the required timing from the circuit 2 is inputted to a gate circuit 4, reset signal generation circuits 5 and 6, window circuits 8 and 9, and a window circuit 18. Outputs of the circuit 6 and a counter circuit 21 are added to an AND gate 7, and the generation of the reset signal is controlled by the output of the circuit 21. When a vertical synchronizing signal does not exist at the inside of the window, the reset signal is generated after the window is closed, and the signal is discriminated from the regular television signal. Then, synchronization at the time of the weak electric field is improved by having the synchronization at the regular timing.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a vertical synchronization device for a television receiver.

Conventional configuration and its problems Conventionally, multiple window circuits have been installed to generate output with a constant pulse width at the required timing from a frequency twice the horizontal synchronization frequency using a frequency divider circuit, and the composite synchronization signal is integrated to form a waveform. There is a window control type vertical synchronization device in which one of the window circuits is selected using the vertical synchronization signal obtained by shaping, the vertical synchronization signal is gated in that window, and vertical synchronization is applied with the output thereof.

This type of vertical synchronizer can obtain stable synchronization even when the vertical synchronization frequency changes, such as during VTR special playback (still, slow, fast forward, 9 rewinds), and has excellent noise resistance. However, it has the disadvantage that correct synchronization cannot be obtained in a weak electric field where the vertical synchronization signal obtained by integrating the composite synchronization signal frequently disappears. This drawback is due to the following reasons.

Assuming that you are currently receiving a normal television signal sent from a broadcasting station and a narrow window is selected, if there is no vertical synchronization signal within the window due to a weak electric field etc. After the widest window different from the above windows is closed, the circuit itself applies a reset signal. If this reset signal is used for vertical output, synchronization will be performed at a timing that is much later than the actual one, and synchronization will be disrupted.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned conventional problems, and to provide a window control type vertical synchronization device with good vertical synchronization characteristics in a weak electric field.

Composition of the Invention The vertical synchronization device according to the present invention generates a reset signal immediately after the window closes if there is no vertical synchronization signal within the window even in a win-win situation, and This reset signal is distinguished from a regular television signal, and if it is less than the number of consecutive drops in the vertical synchronization signal or the count value set in the counting circuit, the window does not change and the timing is close to the regular one. By continuing to apply synchronization, vertical synchronization characteristics can be improved even in weak electric fields.

DESCRIPTION OF THE EMBODIMENTS An embodiment of the present invention will be described below with reference to all the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention.
A clock signal having twice the frequency of the horizontal synchronizing signal is input to the input circuit 2, and is connected to the input of the frequency divider circuit 2 and the input of the delay circuit 150. The frequency dividing circuit 2 is constructed by connecting ten T-type flip-flops in series, and by combining the outputs of the respective flip-flops, an output f of a constant pulse width can be obtained at a required timing. The output of the frequency divider circuit 2 is the gate circuit 4. Reset signal generation circuit 5゜Reset signal generation circuit 6. Window circuit 8. Window circuit 9. They are connected to the inputs of the window circuit 1B and form the respective required timing pulses. The output of the reset signal generation circuit 6 and the output of the counting circuit 21 are connected to the input of the NAND gate 7, and the output of the counting circuit 21 controls generation of the reset signal. The output of the window circuit 9 and the output of the counting circuit 21 are connected to the input of the NAND gate 10, and the output of the counting circuit 21 controls the window generation by the window circuit 9. The output of the window circuit 8 and the output of the HAND gate 1o are connected to the input of an AND gate 11, and the gate circuit 13 is connected to the output of the AND gate 11.

A vertical synchronization signal obtained by integrating and waveform shaping the composite synchronization signal is input to the terminal 12, and is connected to a reset terminal of the gate circuit 13. The output of gate circuit 13, the output of NAND gate 7, and the output of reset signal generation circuit 5 are connected to the input of NAND gate 14, and the output of this NAND gate 14 is connected to the input of delay circuit 15. The delay circuit 15 outputs this input signal in synchronization with the clock to prevent malfunction. The output of the delay circuit 16 is connected to the vertical output terminal 3, the reset terminal of the frequency divider circuit 2, and the gate circuit 4.
The reset terminal of the NAND gate 16 and the input of the inverter 170 are connected to each other.

The output of the gate circuit 4 is connected to the cent signal generation circuit 6 and the reset signal generation circuit 6, and the generation of the reset signal is controlled. The output of the counting circuit 21 is connected to the other input of the NAND gate 16, and the output of the N'AND gate 16 is connected to the clock terminal of the counting circuit 21. The output of the counting circuit 21 becomes L when the set count value is reached.
level, the reset signal generation circuit 6 and the window circuit 9 are canceled, and the reset signal generation circuit 5 and the window circuit 8 are selected. In this state, the counting circuit 20
It is held until it is reset by the output of .

The output of the window circuit 18 and the output of the inverter 17 are A
It is connected to the input of the ND gate 19, and the output of the AND gate 19 is connected to the counting circuit 20.

Inverter 1 within the window by window circuit 18
If there is a vertical output which is the output of 7, the AND gate 19
It detects whether it is a legitimate television signal by producing more output.

The counting circuit 20 receives the output of the AND gate 19 or the output of the inverter 1, counts the number of times the output of the A to D gate 19 occurs continuously in a vertical period, and calculates the set count/value. When it reaches, an output is generated, and this output resets the counting circuit 21. At the same time, the output of the counting circuit 21 becomes H level, and the reset signal generating circuit 6 and the window circuit 9 are selected.

FIG. 2 shows a specific example of the main part. In FIG. 2, parts corresponding to those in FIG. 1 explained earlier are given the same reference numerals, and detailed explanation thereof will be omitted.

Next, in FIG. 3, a, b, c, and d are the waveforms of the main parts when a normal television signal or a signal during standard reproduction of a VTR is received and the window circuit 9 is selected. a is the waveform of the vertical synchronization signal obtained by integrating and shaping the composite synchronization signal, and is input to the input terminal 12. The window waveform is formed by the window circuit 9 and output from the AND gate 11. C is gate circuit 1
This is the output waveform of No. 3. d is the waveform of the vertical output appearing at the terminal 3, and the waveform of C is synchronized with the clock by the delay circuit 16.

For example, when the pulse B does not exist within the window b, the signal 7'L is output from the reset signal generating circuit 6, and f is the waveform of the vertical output appearing at the terminal 3 at that time.

g, h+il] are the waveforms of the main parts when the vertical synchronization signal, such as a signal during special playback of a VTR, fluctuates and the window circuit 8 is selected, and respectively a.

Corresponds to b, c, and d. k is within 1 to 1 win of h
4 is a signal output from the reset signal generating circuit 6 when the pulse 1 does not exist, and 4 is the waveform of the vertical output appearing at the terminal 3 at that time.

If the count value set in the counting circuit 21 is M, then b
(61 as an example in the case of the NTSO method)
If the pulse B is likely to exist continuously for M vertical periods from the 2nd clock to the 624th clock 1), the output of the counting circuit 21 will change the window from bJ' to h (for example, at the 384th clock in the case of the NTSC system). to the 544th clock). If the count value set in the number circuit 2o is N, then the vertical output of j within the window of the window circuit 18 (from the 623rd clock to the 626th clock in the case of NTSC system, for example) is N vertical cycles. If they exist continuously, the output of the counting circuit 2o resets the counting circuit 21, and the window is switched from h to b.

The features of this circuit are the reset signal generation circuit 6 and the window circuit 1B, which will be explained below. m in Figure 3
is a window waveform formed by the window circuit 18. This window output connects the vertical output to inverter 1.
7 is input to the AND gate 19 together with the inverted signal, and if the vertical output is at the timing of a regular television signal, the AND gate 19 produces an output. Therefore, this window is generated by combining the vertical output d during normal operation, and is generated by the seven-level signal generation circuit 6 at the terminal 3.
The vertical output f-(H not included is the condition.) As an example in the case of the NTSC system, as shown in FIG. Even in the case of , the pulse is from the 524th clock to the 525th clock.Also, assuming that the reset signal e is generated at the 526th clock,
The vertical output f is generated at the 627th cross. Therefore, the window m Vi is the 525th clock or the 52nd clock.
Just close it on the 6th Chronok. - As an example, the window m is from the 623rd clock to the 625th clock.

In the bovine blood synchronization device configured in this way, even if the vertical synchronization signal input to the terminal 12 is no longer in a nap, the timing close to the normal vertical output within a certain set number of times (
In the example shown in Figure 3, the vertical output is generated at a 2-crotch difference), so there is little synchronization disturbance, and since the vertical output is counted and determined whether it is normal or normal, the window can be switched accurately. be able to.

Effects of the Invention As detailed above, according to the present invention, in addition to the conventional advantages of the window control method, such as after-sound resistance and synchronization stability during VTR special playback, the present invention improves synchronization characteristics during weak electric fields. This is something that can be improved.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of a vertical synchronization device according to an embodiment of the present invention, Fig. 2 is a circuit diagram showing the wiring of the main parts of the device, and Fig. 3 is a, b, c, d, e, f, g. . h, 1. 41m is a waveform diagram of each part to explain the operation of each part of the Hashirama device. 1... Clock input terminal, 3... Horizontal output terminal, 12... Terminal for inputting the vertical synchronization signal obtained by integrating the composite synchronization signal and shaping the waveform. 7,10,
14゜16...NAND gate, 11. 19
...AND gate, 17... Inno Kuichita. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 2

Claims (1)

[Claims] a clock signal input terminal for inputting a clock signal having repeat synchronization twice that of a horizontal synchronization signal; a frequency division circuit for dividing the frequency of this clock signal and being reset by a reset signal;
a first window circuit that generates an output with a constant pulse width at a required timing from the output of the frequency divider circuit; A second window circuit that generates different outputs, and either the output of the first window circuit or the output of the second window circuit are input, and the composite synchronization signal is inspected and waveform-shaped. a first gate circuit that receives a vertical synchronization signal and generates a reset signal only when the vertical synchronization signal is present within a window; and a state in which the first gate circuit receives the output of the first window circuit. a first reset signal generation circuit that generates a reset signal after the window closes when there is no vertical synchronization signal within the window; and the first gate circuit generates an output of the second window circuit. Vertical sync 1 in the window in the input state
a second reset signal generation circuit that generates a reset signal after this window closes if no. a third window circuit that generates outputs narrowly and with different timings; a second gate circuit that generates an output only when the predetermined signal is present within the window of the third window circuit; a first counting circuit that counts the output of the gate circuit and generates an output when this output occurs in N vertical periods (N is an integer greater than O) consecutively;
is an integer larger than N); a second counting circuit that generates an output every time it counts and is reset by the output of the first counting circuit;
means for selecting one of the window circuit and the second window circuit, and also selecting one of the first reset signal generation circuit and the second reset signal generation circuit; and the first gate. 1. A vertical synchronization device, comprising means for resetting by any of the output of the circuit and the output of the second reset signal generation circuit.