JPH09320177A - Frame-synchronizing signal processing circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To secure regular frame synchronizing signals in a short time, even when inputted signals including frame synchronizing signals also contain irregular frame synchronizing signals. SOLUTION: This circuit is provided with a counter 2 which counts clock signals, synchronized with data string with one frame as a period. The frame- synchronizing signal FSS of an input signal is detected by a frame synchronizing signal detecting circuit 1. With the timing of this frame synchronizing pulse FSP, the count values of the counter 2 are alternately held by first counter holding circuits 3, 4. The held value and the count value of the counter 2 are compared by comparison circuits 6, 7, and when their difference is less than a specified value, a coincidence pulse SP 1 or SP 2 is outputted. The count value at that time is held by a second counter value holding circuit 8. From this value and the count value of the counter 2, the frame-synchronizing signal is secured to obtain a symbol latch signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frame synchronization signal processing circuit for a signal having a frame synchronization signal, in which frames having a constant bit length appear consecutively.

[0002]

2. Description of the Related Art For example, a compact disc (hereinafter referred to as a CD
In this case, an 8-bit sub-code is added to a total of 32 symbols of 24 information symbols (8 bits) and 8 parity symbols (8 bits).
The signal is FM (8-14) converted and recorded with one frame consisting of 588 channel bits together with a 24-bit frame synchronization signal and 3 combined bits.

When reproducing a CD, a signal of 14 channel bits following the 24 channel bits of the frame synchronization signal is read and converted into an 8-bit symbol. Therefore, the frame synchronization signal is detected from the read signal, and the 14-channel-bit EFM-converted symbol is extracted with this as a reference. Therefore, if there is an error in the detection of the frame synchronization signal, the correct symbol cannot be read.

As a conventional frame synchronization signal processing circuit, there is one described as "CD reproducing integrated circuit" in Japanese Patent Publication No. 7-75101. This frame synchronization signal processing circuit will be described with reference to FIG.

The frame synchronization signal detection circuit 41 is a circuit for detecting whether or not the input signal read by the clock signal PCK synchronized with the input signal is the frame synchronization signal FSS, and when the frame synchronization signal is detected. The frame synchronization pulse FSP is transmitted to the second counter 43 and the reset circuit 44.

The first counter 42 is a counter that counts the clock signal PCK for one frame, and is reset by a reset signal sent from the reset circuit 44. The symbol latch signal SLS is generated based on the count value of the counter 42.

The second counter 43 is a counter that counts the clock signal PCK for one frame, and is reset by the frame synchronization pulse FSP. When the frame synchronization pulse FSP comes one frame later, the reset circuit 4 is used.
The frame sync pulse is output to 4.

The reset circuit 44 is the window control circuit 4
5, the frame synchronization pulse FSP controlled by 5, the interpolation frame synchronization pulse from the interpolation pulse generation circuit 46, or the second
A reset signal for resetting the first counter 42 is generated by any one of the frame synchronization pulses after one frame from the counter.

The window control circuit 45 controls, based on the count output of the first counter 42, whether or not to pass the frame synchronization signal FSP. The interpolation pulse generation circuit 46 outputs an interpolation frame synchronization pulse based on the count output of the first counter.

Next, the operation of the frame sync signal detection circuit will be described with reference to FIG. First, the operation while the frame synchronization signal is normal will be described. The window control circuit 45 opens the window based on the count value of the first counter 42 at the timing when the next frame sync pulse will be generated. The reset circuit 44 allows the frame synchronization pulse FSP generated by the frame synchronization signal detection circuit 41 to pass through this window and resets the first counter 42.

If the frame sync signal is missing,
The interpolation pulse output circuit 46 generates a frame synchronization pulse based on the count value of the first counter 42, and resets the first counter 42 via the reset circuit 44. In this way, even if the frame synchronization signal is lost, the counter 42 will be reset at almost accurate timing. Then, the value of the first counter 42 can be used to generate the symbol latch signal SLS for extracting the symbol.

When the frame synchronization signal changes due to disturbance due to disturbance due to search or the like, the second counter 4
3 is reset by the first frame sync pulse,
The frame synchronizing pulse is fetched by the pulse generated after one frame, the frame synchronizing pulse is sent to the reset circuit 44, and the first counter 42 is reset. Then, the generation of the window and the output of the interpolation pulse are synchronized with the changed frame synchronization signal.

[0013]

However, in the conventional method, it is assumed that there is only one frame synchronization signal in one frame, and an irregular frame synchronization signal is generated due to a failure or defect in the recording device. There is no assumption of the case.

FIG. 5 showing processing of a conventional frame synchronization signal.
At point (a), the frame sync pulse FSP has come at the specified number of clock signals PCK, but at point (b), the frame sync pulse FSP does not fall within the window due to disturbance or the like. afterwards,
Before the next regular frame synchronization pulse FSP comes at point (d), the irregular frame synchronization pulse F indicated by the broken line
It is assumed that SP occurs at point (c). Then, the second counter 43 is reset at the first point (b),
It can be reset at point (c). Therefore, even if the regular frame synchronization pulse FSP arrives at point (d), it is not judged that it is one frame after, and the first counter 42 is not reset. Therefore, the first counter 42 is reset to the correct timing only when the next regular frame synchronization pulse FSP comes at the point (e).

Therefore, the correct symbol latch signal SLS can be generated only at the point (e).
If there is always an irregular frame synchronizing signal between the regular frame synchronizing signals, the conventional method has a drawback that the regular frame synchronizing signal cannot be secured forever.

The present invention has been made in view of the above problems of the conventional frame sync signal processing circuit. If the regular frame sync pulse is generated even if the irregular frame sync pulse is generated, The purpose is to be able to generate a correct symbol latch signal.

[0017]

Since the regular frame synchronization signal and the irregular frame synchronization signal have the same shape,
Depending on the shape of the signal, it is not possible to judge whether it is regular or irregular. However, in the case of a regular frame synchronization signal, since the frame synchronization signal exists even after the bit for one frame, it is judged whether the frame synchronization signal is present after the bit for one frame. can do.

Therefore, in the present invention, a frame synchronization signal detection circuit that detects a frame synchronization signal from the input data sequence and outputs a frame synchronization pulse, and a clock signal that is created in synchronization with the input data sequence are input. With a counter that counts the clock signal with one frame period as a cycle, a plurality of first counter value holding circuits that hold the count value of the counter, and a frame synchronization pulse output by the frame synchronization signal detection circuit. An instruction circuit for instructing one of the first counter value holding circuits to sequentially hold the value of the counter, and a count value of the counter when a frame sync pulse output by the frame sync signal detection circuit is generated. And the count value held by the first counter value holding circuit are compared, and the difference between the values is set within the set range. A comparator circuit for outputting a match pulse when the inner, is characterized in that it comprises a second counter value holding circuit for holding the value of the counter by the coincidence pulse from the comparator circuit.

According to the present invention having such characteristics,
The frame sync signal is detected by the frame sync signal detection circuit and the plurality of first counter value holding circuits are operated at the timing. The counter is a free counter that operates with one frame period as a cycle, and if the correct frame cycle continues, the counter value at the timing when the synchronization signal is obtained is almost the same. Therefore, the counter value at the time when the frame synchronization signal is obtained is held by the first counter value holding circuit, and the correct frame synchronization signal is detected by comparing this with the current counter value. In this way, the legal position of the frame sync signal can be quickly captured.

[0020]

Embodiments of the present invention will be described below with reference to the drawings. (Embodiment) FIG. 1 is a block diagram showing an embodiment of the present invention. The frame synchronization signal detection circuit 1 is a circuit that determines whether or not the input signal read by the clock signal PCK synchronized with the input signal is the frame synchronization signal FSS, and the instruction circuit when the frame synchronization signal FSS is detected. 5, the frame synchronization pulse FSP is transmitted to the comparison circuit 6 and the comparison circuit 7.

The counter 2 is a counter for counting the clock signal PCK for one frame. When the clock signal PCK for one frame is counted, the counter 2 automatically returns to 1 and repeatedly counts the clock signal PCK. This counter 2 is not reset by the frame sync pulse FSP. Therefore, as long as a normal signal is input, the current count value and 1
The count value before the frame is almost the same, but the value itself is not fixed.

The first counter value holding circuit 3 and the first counter value holding circuit 4 hold the value of the counter 2 each time the frame synchronization pulse FSP selected and sent by the instruction circuit 5 is input. Circuit.

The instruction circuit 5 is a circuit for alternately sending the frame synchronization signal FSP to the first counter value holding circuit 3 and the first counter value holding circuit 4. Further, since the signals are sent alternately, the information as to which of the first counter value holding circuits the frame synchronization signal FSP is sent next is held, and the frame synchronization signal FS is held.
The information is updated each time P is sent.

The comparison circuit 6 compares the value of the counter 2 with the value of the first counter value holding circuit 3 when the frame synchronization pulse FSP is transmitted from the frame synchronization signal detection circuit 1, and determines a certain difference, for example. In the case of "3" or less, the frame synchronization pulse FSP is passed as the coincidence pulse SP1 and transmitted to the second counter value holding circuit 8.

When the frame synchronizing pulse FSP is transmitted from the frame synchronizing signal detecting circuit 1, the comparing circuit 7 compares the value of the counter 2 with the value of the first counter value holding circuit 4, and determines a certain difference, For example, in the case of "3" or less, the frame synchronization pulse FSP is passed as the coincidence pulse SP2 and transmitted to the second counter value holding circuit 8.

The second counter value holding circuit 8 has the coincidence pulse (SP1 or SP2) from the comparison circuits 6 and 7.
Holds the value of counter 2.

Further, the symbol latch signal SLS for latching the symbol following the frame synchronization signal can be generated from the difference between the counter 2 and the counter value of the second counter value holding circuit 8 (not shown).

Next, the operation of the circuit shown in FIG. 1 will be described with reference to FIG. In FIG. 2, for simplification, it is assumed that the frame synchronization signal is composed of 5 bits and the information symbol is composed of 4 bits, and if one frame is composed of 100 information symbols, the length of one frame is 40 including the frame synchronization signal.
It will be 5 bits.

It is also assumed that the comparison circuit 6 passes the frame synchronization pulse FSP as the coincidence pulse SP1 when the values of the counter 2 and the first counter value holding circuit 3 are 3 or less.
Similarly, the comparison circuit 7 passes the frame synchronization pulse FSP as the coincidence pulse SP2 when the difference between the values of the counter 2 and the first counter value holding circuit 4 is 3 or less.

The frame synchronization signal detection circuit 1 receives the frame synchronization signal FSS and then receives the frame synchronization pulse FS.
Generate P. The frame synchronization pulse FSP is an instruction circuit 5
Is sent to the comparison circuit 6 and the comparison circuit 7. The instruction circuit 5 refers to the information held to alternately send the frame synchronization pulse FSP to the first counter value holding circuits 3 and 4, and refers to the information held in the first counter value holding circuit 3 or 4 to the frame synchronization pulse. Send FSP. If the internal information is “3 (first counter value holding circuit 3)” this time, the first counter value holding circuit 3 (shown as CVH3 in FIG. 2)
To the frame sync pulse FSP. Then, information inside the instruction circuit 5 is set to "4 (first counter value holding circuit 4,
Change to CVH4) ”in the figure. The first counter value holding circuit 3 takes in the value “24” of the counter 2 in response to the frame synchronization pulse sent from the instruction circuit 5. Since the difference between the value of the first counter value holding circuit 3 (“0” in this case) and the value of the counter 2 (“24” in this case) before being updated is 4 or more, the comparison circuit 6 causes the frame Sync signal F
Do not pass SP.

Also in the case of the comparison circuit 7, the difference between the value "0" of the first counter value holding circuit 4 (CVH4 in FIG. 2) and the value "24" of the counter 2 is 3 or less, like the comparison circuit 6. Therefore, the frame sync pulse FSP is not passed.

After one frame, when the frame synchronization signal FSS is input again, the frame synchronization signal detection circuit 1 generates a frame synchronization pulse FSP and sends it to the instruction circuit 5, the comparison circuit 6, and the comparison circuit 7. The instruction circuit 5 refers to the internal state, and this time sends the frame synchronization pulse FSP to the first counter value holding circuit 4. Then, the internal information is changed to "3 (first counter value holding circuit 3)". The first counter value holding circuit 4 takes in the value “24” of the counter 2 in response to the frame synchronization pulse sent from the instruction circuit 5.

At this time, when the value of the first counter value holding circuit 3 (“24” in this case) and the value of the counter 2 (“24” in this case) are compared, the difference is 3 or less, so the comparison circuit 6 Passes the frame synchronization pulse FSP and sends it to the second counter value holding circuit 8 as a coincidence pulse SP1. In the case of the comparison circuit 7, the value of the first counter value holding circuit 4 immediately before being updated is “0”, the value of the counter 2 is “24”, and the difference is 4 or more. FSP is not passed. The second counter value holding circuit 8 fetches the value “24” of the counter 2 by the coincidence pulse SP1 (frame synchronization pulse FSP) passed from the comparison circuit 6.

The same process is performed one frame later,
Since the count value of the first counter value holding circuit 4 is "24", the coincidence pulse SP2 is output. The second counter value holding circuit 8 receives the counter 2 by the coincidence pulse SP2.
The value "24" of is acquired.

The above-described operation is performed when the frame synchronization signal normally arrives and is detected. However, when the frame synchronization signal is lost due to scratches on the disk or the like, the value of the second counter value holding circuit 8 becomes Not updated. Therefore, the value of the second counter value holding circuit 8 fetched at the very end and the counter 2
And the signal SLS for latching the symbol is generated from the difference.

Next, the operation when there is an irregular frame synchronization signal will be described with reference to FIG. Similar to the conventional example, the frame synchronization signal FSP has come up to the point (a) at the specified number of clock signals PCK, but at the point (b), the frame synchronization pulse FSP is displaced due to disturbance or the like. After that, it is assumed that an incorrect frame synchronization signal occurs at the point (c) before the next regular frame synchronization pulse FSP reaches the point (d).

At the point (b), the value of the counter 2 is "30".
The value "0" means the value "100" of the first counter value holding circuit 3 and the value "10" of the first counter value holding circuit 4 immediately before.
However, no coincidence pulse is sent to the second counter value holding circuit 8 because the values are different from each other by the specified difference “3” or more. Then, the value “300” of the counter 2 at that time is taken into the first counter value holding circuit 3.

Similarly, when an irregular frame sync pulse occurs at the point (c), the value "150" of the counter 2 is the first counter value holding circuit 3 immediately before.
Is compared with the value of "300" in the comparison circuit 6 and also with the value of "100" in the first counter value holding circuit 4 in the comparison circuit 7. In both cases, the value is different from the specified difference "3" or more. Therefore, no coincidence pulse is sent to the second counter value holding circuit 8. Then, the value of the counter 2 at that time is “150”
Are taken into the first counter value holding circuit 4. Next, when the normal frame synchronization pulse FSP occurs at the point (d), the value “300” of the counter 2 is the value “300” of the first counter value holding circuit 3 and the value “300” of the first counter value holding circuit 4. It is compared with the value “150”. At this time, since the difference from the first counter value holding circuit 3 is smaller than the specified size “3”, the comparison circuit 6 outputs the coincidence pulse SP1 to the second value.
Is sent to the counter value holding circuit 8 of
00 ”is taken into the second counter value holding circuit 8.

In the embodiment of the present invention, the latch signal of the symbol included in the input signal is the second counter value holding circuit 8
And the value of the counter 2 is generated, the latch signal of the correct symbol can be generated at the time of (d) in the present embodiment. That is, the normal frame synchronization signal can be captured at the time of (d). In the conventional example, the frame sync signal can be captured at the time (e) when the next normal frame sync signal is input. In this case, the instruction circuit 4 sequentially transfers the frame synchronization signal ESP to the first counter value holding circuits 3 and 4 alternately.

In the above description, the case where the number of the first counter value holding circuits is two has been described, but the case where the number of the first counter value holding circuits is three or more is also possible. N between regular frame sync signals
Assuming that there are irregular frame sync signals, by using n + 1 first counter value holding circuits,
A regular frame sync signal can be secured quickly.

Further, in the above description, the case where the pulse is generated from the comparison circuit when the difference between the values of the counter and the first counter value holding circuit is 3 or less has been described. However, it can be realized similarly. Further, this value does not have to be constant, and may be changed depending on whether or not the coincidence pulse from the comparison circuit is continuously generated for several frames.

In the above description, the frame sync signal is 5
I explained the case where the bits and information symbols are 4 bits.
In the case of a signal in which frames of the same length repeatedly appear, a frame synchronization signal of any length or an information symbol can be similarly realized.

[0043]

As described above, according to the present invention, the value of the counter at the time when the frame synchronization signal pulse is generated is held even when an irregular frame synchronization signal exists, and the value and the subsequent value are retained. By comparing the value of the counter at the time when the frame sync signal pulse is generated, the position of the valid frame sync signal can be quickly captured.

Further, even when an irregular frame synchronizing signal continuously occurs between the regular frame synchronizing signals, it is possible to detect the regular frame signal and secure the frame synchronizing signal.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a frame synchronization signal processing circuit according to an embodiment of the present invention.

FIG. 2 is a time chart showing the operation of the frame synchronization signal processing circuit according to the present embodiment.

FIG. 3 is a time chart showing an operation when an irregular frame synchronization signal is input to the frame synchronization signal processing circuit according to the present embodiment.

FIG. 4 is a block diagram showing an example of a conventional frame synchronization signal processing circuit.

5 is a time chart showing an operation when an irregular frame synchronization signal is added to the conventional frame synchronization signal processing circuit shown in FIG.

[Explanation of symbols]

 1 frame synchronization signal detection circuit 2 counter 3,4 first counter value holding circuit 5 instruction circuit 6,7 comparison circuit 8 second counter value holding circuit 41 frame synchronization signal detection circuit 42 first counter 43 second counter 44 reset circuit 45 window control circuit 46 interpolation pulse generation circuit

Claims (1)

[Claims] 1. A frame synchronization signal detection circuit that detects a frame synchronization signal from an input data sequence and outputs a frame synchronization pulse; and a clock signal that is created in synchronization with the input data sequence, and inputs one frame. With a period as a cycle, a counter that counts the clock signal, a plurality of first counter value holding circuits that hold the count value of the counter, and a frame synchronization pulse output by the frame synchronization signal detection circuit An instruction circuit for instructing any one of the counter value holding circuits 1 to sequentially hold the value of the counter; a count value of the counter when a frame sync pulse output by the frame sync signal detection circuit is generated; Compare with the count value held by the first counter value holding circuit, and match if the difference between the values is within the set range A comparator circuit for outputting a pulse, a frame synchronizing signal processing circuit, characterized by comprising a second counter value holding circuit, the holding value of the counter by the coincidence pulse from the comparator circuit.