JPH08249822A - Sync detection method and sync detection circuit - Google Patents

Abstract

PURPOSE: To prevent malfunction of synchronization processing due to pseudo- sync pattern detection, etc., in the transfer of digital data modulated by frame synchronization. CONSTITUTION: When a sync pattern is detected from inputted data, a sync pattern detecting circuit 10 outputs a sync pattern detection signal. When a frame counter 20 counts clock signals by bit numbers for one frame, a frame count signal is outputted. A sync managing circuit 30 sets a window time area inside depending upon the timing when the sync pattern detection signal and the frame count signal are inputted and outputs the sync signal only when the sync pattern detection signal is inputted to the window time area.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sync detection method and a sync detection circuit for detecting a sync sync pattern from frame sync modulated digital data. The present invention relates to a sync detection method and a sync detection circuit which prevent malfunction of sync detection due to a pseudo sync pattern or the like by controlling pattern detection conditions.

[0002]

2. Description of the Related Art In the transmission of digital data, data is divided into a certain number of bits to form one frame, and a sync pattern is added to the header portion of each frame data at the time of modulation to indicate a frame delimiter. However, a so-called frame synchronous modulation method has been conventionally used in which a data receiving unit performs a synchronous process by detecting the sync pattern.

A mini disk (MD) device will be described as an example in which the frame synchronous modulation method is used.
FIG. 12 is a block diagram showing an outline of the configuration of the mini disk device.

During audio reproduction, the EFM signal read from the disc is converted into digital data by EFM demodulation and then temporarily stored in a memory. After being error-corrected by the ECC circuit, it is decompressed and converted into music digital data. Digital data for music is D
/ A converted and output from the speaker, or P
It is sent to another device as a CM signal.

A PC input from the outside during voice recording
M signal or audio signal input by microphone etc. is A / D
The converted digital data for music is compressed,
After an error correction code or the like is added by the ECC circuit, it is EFM-modulated and written on the disc.

An ADIP signal indicating a disk address is converted into digital data by an ADIP circuit and then sent as an address signal to an external control circuit or the like.

The EFM signal, the ADIP signal, and the digital data in the mini disc device all include a sync pattern, and each unit of the mini disc device performs synchronization by detecting the sync pattern to perform processing. There is.

FIG. 13 is a block diagram showing an outline of the configuration of the EFM demodulation circuit. E input to the EFM demodulation circuit
The FM signal is input to the sync detection circuit 60 and the 14-8 conversion circuit 62. The sync detection circuit 60 outputs a sync signal when a sync pattern is detected for the EFM signal. The 14-8 conversion circuit 62 includes the sync detection circuit 60.
Synchronize with the sync signal output from the
Demodulate the signal into EFM demodulated data.

FIG. 14 is an example of an actual sync pattern. (A) is a sync pattern in the EFM signal,
(B) is a sync pattern in the ADIP signal.
In the sync pattern decode value, "1" means signal inversion, and "0" means signal non-inversion. As the sync pattern, a signal pattern that never appears in the data part of each signal is selected.

Therefore, in a device such as the mini disk device shown in FIG. 12, it is extremely important to accurately detect the sync pattern. That is, the adoption of an excellent sync detection method with few malfunctions is a major point for allowing the device to operate normally.

[0011]

However, the conventional sync detecting method has the following problems.

The sync pattern is defined so as not to pattern-match with the modulation result of the data portion of each signal. Therefore, when the reliability of the transmission path of the digital signal is extremely high, the frame demodulation is accurately performed. However, since a transmission error occurs with a certain probability in an actual transmission line, the frame may not be demodulated accurately as described below.

First, there is a case where the sync pattern itself changes due to a transmission error. At this time, since the sync pattern cannot be detected on the data receiving side, the frame cannot be demodulated.

In addition, the data part of the signal changes due to a transmission error, and the same signal pattern as the sync pattern, that is, a so-called pseudo sync pattern is generated. At this time,
On the data receiving side, the pseudo sync pattern is recognized as a normal sync pattern and the frame is erroneously demodulated.

In order to prevent such malfunction, in the past,
For example, as shown in Japanese Patent Laid-Open No. 61-101139, a method of setting a window time region in the vicinity of a correct sync position and not performing sync pattern detection outside the window time region, or a sync pattern at an expected sync position If it is not detected, a method such as interpolating a temporary sync pattern detection signal is adopted.

However, the structure disclosed in Japanese Patent Laid-Open No. 61-101139 has the following problems.

First, when the area width of the window time area is fixed and the sync pattern is not detected, the area width of the window time area is set to infinity to search for a sync pattern. The probability of occurrence of malfunction due to detection of is significantly increased.

Further, although the result of data error judgment is used to improve the accuracy of sync pattern detection, the error judgment is based on the assumption that the correct sync pattern is originally detected. The detection of the sync pattern based on the error judgment that is not always guaranteed is
There is a contradiction in the composition itself, and no effect can be obtained.

Further, no consideration is given to a case of an unusual operation such as a skip-and-play reproduction in a mini disk device.

In view of the above problems, the present invention can prevent malfunction of sync detection due to a pseudo sync pattern or the like when detecting a sync pattern from frame-synchronized modulated digital data, and is much more accurate than conventional detection accuracy. It is an object of the present invention to provide an excellent sync detection method and sync detection circuit.

[0021]

To achieve the above object, the present invention sets a variable length window time region,
The area width of the window time area is controlled according to the past sync pattern detection accuracy. In addition, the area width of the window time area can be made infinite by an external interrupt signal.

Specifically, the means for solving the problems of the second aspect of the present invention is that, from the digital signal in which the sync pattern signal is inserted for every fixed number of bits by frame synchronous modulation,
A sync pattern that outputs a sync pattern detection signal when the same signal pattern as that of the sync pattern signal is detected from the digital signal, targeting a sync detection method for detecting the sync pattern signal and outputting the sync signal A step of detecting and setting a variable-length window time domain having the same time period as the insertion of the sync pattern signal, and detecting a correct sync pattern signal when the sync pattern detection signal is output in the window time domain And a sync management step of outputting a sync signal indicating that the above has been performed.

According to the second aspect of the present invention, when the frame sync modulated digital signal has the same signal pattern as the sync pattern signal, the sync pattern detection signal is output in the sync pattern detection step. In the sync managing step, the window time domain having the same time period as the correct sync pattern signal is set, and when the sync pattern detection signal is output in the window time domain, the sync signal is output. As a result, the sync pattern matching is performed only in the vicinity of the timing when the correct sync pattern signal is inserted, the sync pattern detection signal in which the pseudo sync pattern is detected is removed, and the sync signal is the correct sync pattern. It is output only when a signal is detected. Also, since the area width of the window time area is variable, it can be arbitrarily set according to the reliability of the transmission path of the digital signal, and is appropriately controlled according to the detection status of the sync pattern signal. be able to.

According to a third aspect of the present invention, in addition to the configuration of the second aspect, the number of clock signals synchronized with the digital signal is counted, and the number of bits of one frame composed of the fixed number of bits and the sync pattern signal. Further comprises a frame counting step of outputting a frame count signal when the count number reaches
A first process of setting a region width of the window time region based on a timing of outputting the sync pattern detection signal and a timing of outputting the frame count signal; and detecting the sync pattern in the window time region. A second process of outputting the sync signal when a signal is output, and a third process of outputting a reset signal when the sync pattern detection signal or the frame count signal is output within the window time region. In addition, the frame counting step adds a configuration having a process of resetting the count number of the clock signal when the reset signal is output.

According to the third aspect of the invention, the area width of the window time area is set based on the timing of the sync pattern detection signal and the timing of the frame count signal output in the frame counting step.
Further, since the reset signal is output when the sync pattern detection signal or the frame count signal is output in the window time region, and the count in the frame counting step is reset by the reset signal, the timing of the frame count signal Is fixed. By this, even if the timing of the sync pattern signal is shifted, the area width of the window time area can be appropriately controlled.

According to a fourth aspect of the present invention, in the configuration of the third aspect, the sync managing step outputs the sync signal when the frame count signal is output within the window time domain. A configuration having further processing is added.

According to the configuration of the fourth aspect of the present invention, even in the frame in which the sync pattern cannot be detected, the sync signal is output when the frame count signal is output in the window time domain. This prevents the sync signal from being lost in each frame of the digital signal.

According to a fifth aspect of the present invention, in addition to the configuration of the fourth aspect of the present invention, a configuration further including an error determination step of determining the presence or absence of an error in the digital signal based on the sync signal is added. is there.

With the configuration of the fifth aspect of the invention, it is possible to determine the presence or absence of an error in the error determining step based on the sync signal having no omission.

According to a sixth aspect of the present invention, in the configuration according to any one of the third to fifth aspects, the sync managed step makes the area width of the window time area infinite by an external interrupt signal. The configuration further having the fifth processing is added.

According to the configuration of the sixth aspect of the invention, since the area width of the window time area becomes infinite by the external interrupt signal, it is possible to immediately deal with the case where an operation different from the normal operation is performed.

According to a seventh aspect of the present invention, in the structure of the fourth aspect, the same process as each of the first, second and fourth processes and the window time region when the frame count signal is output are set. The configuration further includes another sync managed process having a closing process.

According to an eighth aspect of the present invention, in the configuration of the sixth aspect, the same processing as each of the first, second, fourth and fifth processing, and the window when the frame count signal is output. The configuration further includes another sync managed process having a process of closing the time domain.

According to the seventh and eighth aspects of the invention, when the frame count signal is output, the window time domain is closed in another sync managed step. If the timing of the sync pattern signal is shifted backward, the sync signal is output because the frame count signal is output, and then the sync pattern detection signal is output in the window time domain in the sync management step, and the sync signal is output. Although a signal may be output, the sync signal is not output in the other sync management step because the window time region is always closed when the sync pattern detection signal is output. As a result, no more than one sync signal is output per frame in the other sync management step.

According to a ninth aspect of the invention, in the configuration of the invention according to any one of the third to eighth aspects, the first process initially sets the window width of the window time region to infinity, and 1
When the timings of the sync pattern detection signal and the frame count signal coincide with each other for a predetermined number of times, the window time region is set at the same timing as the frame count signal after making the region width a finite length, and , The width of the window time area is set to the second
When the timings of the sync pattern detection signal and the frame count signal are continuously matched for a predetermined number of times, the process is narrowed, and when the timings are not matched for the third predetermined number of times, the process is widened. It is something to add.

According to the ninth aspect of the present invention, the window time region has an infinite region width at first, and the timings of the sync pattern detection signal and the frame count signal coincide with each other for the first predetermined number of times. At this time, the area width is set to a finite length and set at the same timing as the frame count signal. Further, when the timings of the sync pattern detection signal and the frame count signal match the second predetermined number of times consecutively, the area width is narrowed, and when the timings of the third predetermined number of times do not match continuously, the area width is widened. . By this, even if the timing of the sync pattern signal is shifted, the area width of the window time area can be appropriately controlled.

According to a tenth aspect of the invention, in the configuration of the invention according to any one of the third to eighth aspects, the first processing initially sets the window width of the window time region to infinity. When the timings of the sync pattern detection signal and the frame count signal coincide with each other for a predetermined number of times of 1, the window time region is set at the same timing as the frame count signal after making the region width a finite length. Further, the region width of the window time region is narrowed when the sync pattern detection signal is output within the window time region for the second predetermined number of times, while the width of the window time region is reduced. In addition, a configuration having a process of widening the case where the sync pattern detection signal is not output occurs for a third predetermined number of times is added. It is.

According to the tenth aspect of the present invention, the window time region has an infinite region width at the beginning, and the timings of the sync pattern detection signal and the frame count signal coincide with each other for the first predetermined number of times. At this time, the area width is set to a finite length and set at the same timing as the frame count signal. Further, when the sync pattern detection signal is output in the window area continuously for the second predetermined number of times, the area width is narrowed and the sync pattern detection signal is not output in the window area. If it occurs a predetermined number of times in succession, the area width is expanded. By this, even if the timing of the sync pattern signal is shifted, the area width of the window time area can be appropriately controlled.

Further, the means for solving the problems according to the eleventh aspect of the present invention takes as input a digital signal in which a sync pattern signal is inserted by a fixed number of bits by frame synchronous modulation, and outputs the sync pattern signal from the digital signal. Targeting a sync detection circuit that detects and outputs a sync signal, the digital signal is input, and when the same signal pattern as the sync pattern signal has is detected from the digital signal, a sync pattern detection signal is output. A sync pattern detection circuit and a variable length window time domain having the same time period as the insertion of the sync pattern signal are internally set, and a correct sync pattern is input when the sync pattern detection signal is input in the window time domain. A sync that outputs the sync signal indicating that a signal has been detected. It is an arrangement and a managed circuit.

According to the eleventh aspect of the present invention, when the frame sync modulated digital signal has the same signal pattern as the sync pattern signal, the sync pattern detection circuit outputs the sync pattern detection signal. Inside the sync managed circuit, the window time domain with the same time period as the correct sync pattern signal is set,
When the sync pattern detection signal is input within the window time domain, the sync managed circuit outputs the sync signal. As a result, the sync pattern matching is performed only in the vicinity of the timing when the correct sync pattern signal is inserted, the sync pattern detection signal that detects the pseudo sync pattern is removed, and the sync signal is the correct sync pattern. It is output only when a signal is detected. Also, since the area width of the window time area is variable, it can be arbitrarily set according to the reliability of the transmission path of the digital signal, and is appropriately controlled according to the detection status of the sync pattern signal. be able to.

According to a twelfth aspect of the present invention, in addition to the configuration of the eleventh aspect of the invention, the number of clock signals synchronized with the digital signal is counted, and the number of bits of one frame consisting of the fixed number of bits and the sync pattern signal. Further comprises a frame counter for outputting a frame count signal when the count number reaches
A function of setting the area width of the window time area based on the timing of inputting the sync pattern detection signal and the timing of inputting the frame count signal, and inputting the sync pattern detection signal in the window time area. Has a function of outputting the sync signal when it is, and a function of outputting a reset signal to the frame counter when the sync pattern detection signal or the frame count signal is input in the window time region, The frame counter is added with a configuration having a function of resetting the count number of the clock signal when the reset signal is input.

According to a thirteenth aspect of the present invention, in the configuration of the twelfth aspect of the invention, the sync managed circuit sets the window time domain based on the timing at which the sync pattern detection signal is input and the timing at which the frame count signal is input. A window width control circuit that sets a region width and outputs a signal having different logic levels in the window time region and outside the window time region, and a signal output from the window width control circuit as an input, A configuration including a logic circuit that outputs a sync signal when the sync pattern detection signal is input while the logic level is within the window time domain is added.

According to a fourteenth aspect of the present invention, in the structure of the thirteenth aspect, the window width control is performed when the logic circuit is instructed to output an interpolation sync signal by a sync interpolation permission signal from the outside. A configuration is added in which the sync signal is output when the frame count signal is input while the logic level of the output signal of the circuit is the logic level within the window time region.

According to a fifteenth aspect of the present invention, in the configuration of the thirteenth aspect, the window width control circuit sets the logic level of the output signal outside the window time region when the sync signal is output from the logic circuit. The configuration for changing to the logical level in is added.

Further, the means for solving the problems according to the sixteenth aspect of the present invention takes as input a digital signal in which a sync pattern signal is inserted by a fixed number of bits by frame synchronous modulation, and the sync pattern signal is converted from the digital signal. Targeting a sync detection circuit that detects and outputs a sync signal, the digital signal is input, and when the same signal pattern as the sync pattern signal has is detected from the digital signal, a sync pattern detection signal is output. A sync pattern detection circuit and a clock signal synchronized with the digital signal are counted, and a frame count signal is output when the count number reaches the bit number of one frame including the fixed number of bits and the sync pattern signal. Frame counter and the sync pattern signal A first window time region and a second window time region of variable length having the same time cycle as the above are internally set based on the timing at which the sync pattern detection signal is input and the timing at which the frame count signal is input. Then, when the sync pattern detection signal is input in the first window time domain, the first sync signal is output, while the sync pattern detection signal is input in the second window time domain. A sync managed circuit that outputs a second sync signal and closes the second window time domain, the sync managed circuit including the sync pattern detection signal or the frame in the first window time domain. When a count signal is input, a reset signal is output to the frame counter and the frame counter is Mukaunta is,
The count number of the clock signal is reset when the reset signal is input.

According to the sixteenth aspect of the invention, when the frame sync modulated digital signal has the same signal pattern as the sync pattern signal, the sync pattern detection circuit outputs the sync pattern detection signal. First and second window time regions having the same time period as the correct sync pattern signal are set in the sync managed circuit, and when the sync pattern detection signal is input in the first window time region. While the first sync signal is output, the second sync signal is output when the sync pattern detection signal is input in the second window time region. Therefore, the sync pattern matching is performed only in the vicinity of the timing when the correct sync pattern signal is inserted, and the sync pattern detection signal detecting the pseudo sync pattern is removed. Further, since the area width of the window time area is variable, it can be arbitrarily set according to the reliability of the transmission path of the digital signal, and can be appropriately controlled according to the detection status of the sync pattern signal. it can. Furthermore, since the second window time region is closed when the second sync signal is output, it is possible to reliably prevent the output of two or more second sync signals per frame. it can.

According to a seventeenth aspect of the present invention, in the configuration of the sixteenth aspect of the invention, the sync managed circuit is based on the timing at which the sync pattern detection signal is input and the timing at which the frame count signal is input. First
A first window width control circuit for setting a region width of the window time region and outputting signals having different logic levels in the first window time region and outside the first window time region; The signal output from the window width control circuit is input, and when the sync pattern detection signal is input while the logic level of the signal is the logic level in the first window time region, the first pattern A first logic circuit that outputs a sync signal, and sets the area width of the second window time area based on the timing when the sync pattern detection signal is input and the timing when the frame count signal is input, A second signal that outputs a signal having a different logic level in the second window time domain and outside the second window time domain And Indou width control circuit, said second
When the signal output from the window width control circuit is input and the sync pattern detection signal is input while the logic level of the signal is the logic level within the second window time region, the second pattern A second logic circuit that outputs a sync signal, and the second window width control circuit sets the logic level of the output signal when the second sync signal is output from the second logic circuit. A configuration for changing to a logic level outside the second window time domain is added.

[0048]

BEST MODE FOR CARRYING OUT THE INVENTION A sync detecting method and a sync detecting circuit according to embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) FIG. 1 shows a first embodiment of the present invention.
3 is a configuration diagram of a sync detection circuit according to the embodiment of FIG. FIG.
In the figure, 10 is a sync pattern detection circuit, 20 is a frame counter, and 30 is a sync managed circuit.

The sync pattern detection circuit 10 performs sync pattern matching on the input digital data, and outputs a sync pattern detection signal when the same bit pattern as the sync pattern is detected.

The frame counter 20 outputs a frame count signal when the input clock signal is counted by the number of bits of one input digital data frame. Further, when the reset signal is input from the sync managed circuit 30, the count of the clock signal is reset.

The sync managed circuit 30 sets a variable length window time region having the same period as the sync signal in the circuit according to the input sync pattern detection signal and frame count signal. When the sync pattern detection signal is input within the window time domain, the sync signal is output, and when the sync pattern detection signal is input outside the window time domain, the sync signal is not output.
Also, when the sync detection signal is input in the window time domain and when the frame count signal is input,
The reset signal is output to the frame counter 20.

A sync detecting method implemented in the sync detecting circuit shown in FIG. 1 will be described.

FIG. 2 is a flow chart showing the method of setting the window time domain in this embodiment. Also,
3, 4, and 5 are timing charts for explaining the operation of the sync detecting method according to the present embodiment. The window time domain is shown in the form of a pulse signal, and when the pulse signal is at the “H” level, it indicates that the window time domain is set.

First, in step S1, the area width of the window time area is set to infinity. In FIG. 3, initially, the pulse signal representing the window time domain remains at the “H” level. At this time, the sync managed circuit 30 outputs the sync signal as it is when the sync pattern detection signal is input. At the same time, it also outputs a reset signal. The frame counter 20 to which the reset signal is input resets the count of the clock signal once and starts counting again. In a normal state, the sync pattern detection signal and the frame count signal have the same timing.

Next, in steps S2 and S3, it is determined whether or not the sync pattern detection signal and the frame count signal have been simultaneously input a specific number of times consecutively. FIG.
In, the specific number is set to two. Since the sync pattern detection signal and the frame count signal have been input twice consecutively at the same time, in step S4, the area width of the window time area is set to a finite length, and step S4 is performed.
In 5, the window time domain is set near the frame count signal. By setting the window time region in the vicinity of the frame count signal, it is possible to prevent an erroneous operation of detecting a pseudo sync pattern.

Next, in step S6, it is determined whether or not the sync pattern detection signal and the frame count signal are simultaneously input. If they are input at the same time, it is determined in step S7 whether or not they are input a specific number of times consecutively, and if they are input a specific number of times, the area width of the window time region is narrowed in step S9. To do.

FIG. 4 shows a timing chart when the area width of the window time area is narrowed. However, in FIG. 4, the specific number of times is two. Since the sync pattern detection signal and the frame count signal are input simultaneously twice in succession, the next window time region is narrowed, and further, the sync pattern detection signal and the frame count signal are input simultaneously twice in succession. Therefore, the next window time region is narrowed.

Although the area width of the window time area is narrowed to the same width as the sync pattern detection signal in FIG. 4, when it is used in an actual circuit, it depends on the reliability of the transmission path. It does not matter if there is some margin. Also, FIG. 4 does not follow FIG.

If it is determined in step S6 that the sync pattern detection signal and the frame count signal are not simultaneously input, in step S8.
It is determined whether or not the data are not input at the same time for a specific number of times.
In 10, the region width of the window time region is widened.

FIG. 5 shows a timing chart when the area width of the window time area is widened. The second sync pattern detection signal is out of the window time domain because the timing is shifted earlier, and the sync signal is no longer output. At this time, since no reset signal is output, the timing of the frame count signal does not change. Therefore, the sync pattern detection signal and the frame count signal are not input at the same time.

When the sync pattern detection signal and the frame count signal are not simultaneously input for a certain number of times consecutively, the next window time region is widened. In FIG. 5, the specific number of times is two. Since the window time domain is expanded, the next sync pattern detection signal falls within the window time domain, so that the sync signal is output.
At this time, since the reset signal is also output, the frame counter 20 is reset, the timing of the frame count signal changes, and thereafter, the sync pattern detection signal and the frame count signal are simultaneously input. The timing of the window time domain also changes with the timing of the frame count signal.

As described above, by making the area width of the window time area variable and changing the area width according to the timing of the sync pattern detection signal and the frame count signal, it is possible to prevent malfunction due to detection of the pseudo sync pattern, Moreover, even if the timing of the sync pattern is deviated, it is possible to synchronize immediately.

Further, the judgment conditions in step S6 are
It may be changed to whether or not the sync pattern detection signal is input in the window time domain. That is, when the sync pattern detection signal is continuously input in the window time domain a specific number of times, the area width of the next window time domain is narrowed and the sync pattern detection signal is continuously input in the window time domain a specific number of times. If not, even if control is performed such that the width of the next window time area is widened, the same effect as this embodiment can be obtained.

(Second Embodiment) An error detection circuit not shown in FIG. 1 determines whether or not there is an error in the input data, and outputs the result of the error determination. At this time, the data is separated based on the sync signal output from the sync managed circuit 30, and error determination is performed. Also, when an external circuit reads input data,
The sync signal output from the sync management circuit 30 is used as a reference.

Here, the loss of the sync signal becomes a problem.
When the sync signal is missing as in the timing chart shown in FIG. 5, the error detection circuit recognizes a time when the sync signal is missing as one frame, and malfunctions. Also, when an external circuit reads input data,
A plurality of frame data are recognized as one frame data. In order to prevent such a malfunction, it is necessary to generate at least one sync signal for one frame.

This embodiment is characterized in that an interpolated sync signal is output in a frame in which no sync signal is output. The interpolated sync signal is output when the frame count signal is input. The output method of the sync signal other than the interpolated sync signal, the output method of the reset signal, and the setting method of the window time domain are the same as those in the first embodiment.

FIG. 6 is a timing chart for explaining the operation of the sync detecting method according to the second embodiment of the present invention.

First, when the correct sync pattern cannot be detected due to a data transmission error, that is, when the sync pattern signal is not input, when the frame count signal is input, the interpolating sync signal is output.

When the timing of the sync pattern detection signal is shifted backward and out of the window time domain,
No sync signal is output. However, when the frame count signal is input, the interpolated sync signal is output.

Since the sync pattern detection signal and the frame count signal have not been input twice consecutively and simultaneously, the next window time region becomes wider. Then, since the next sync pattern detection signal is input in the window time domain, the sync signal is output. Further, when the frame count signal is input, the interpolating sync signal is output.

The error judgment circuit makes an error judgment based on this sync signal including the interpolated sync signal.

According to the first embodiment, when a correct sync pattern cannot be detected due to a data transmission error, the sync signal is not output. However, according to this embodiment, since the interpolated sync signal is output at the timing of the frame count signal, the sync signal is not lost. Therefore, for example, the error determination by the error determination circuit is also correctly performed, so that it can be accurately determined whether or not the data is adopted.

(Third Embodiment) In the minidisk device as shown in FIG. 12, when an operation different from the usual one such as skipping the music or tracking off is performed,
Sync pattern detection in the ADIP signal must be performed immediately.

In order to deal with such an operation, the sync detecting method according to the third embodiment of the present invention is provided with the processing by the window interrupt signal, and when the window interrupt signal is input, the window time domain The area width is made infinite. The method of outputting the sync signal and the interpolated sync signal, the method of outputting the reset signal, and the method of setting the window time domain other than when the window interrupt signal is input are the same as those in the second embodiment.

FIG. 7 is a timing chart for explaining the operation of the sync detecting method according to the third embodiment of the present invention.

Since the first sync pattern detection signal is input at the same time as the frame count signal, the reset signal and the sync signal are simultaneously output. The second sync pattern detection signal is out of the window time domain because the timing is shifted backward, and therefore neither the sync signal nor the reset signal is output. When the frame count signal is input, the interpolating sync signal and the reset signal are output.

Here, it is assumed that the window interrupt signal is input. Then, the area width of the window time area is set to infinity.

In this window time domain, first,
When the sync pattern detection signal or the frame count signal, whichever is earlier, is input, the sync signal is output. After that, from the time when this sync signal is output until the window time region is closed (in FIG. 7, the lower right diagonal line), when either one of the sync pattern detection signal or the frame count signal is input, the sync No signal is output. The sync signal is output only when the sync pattern detection signal and the frame count signal are input at the same time. The reset signal is output when the sync pattern detection signal or the frame count signal is input.

When the sync pattern detection signal and the frame count signal are simultaneously input, the window time region set to infinity is closed after the sync signal is output.

By doing so, even if the timing of the sync pattern is shifted, the correct sync pattern can be immediately detected by inputting the window interrupt signal.

Here, the condition for closing the window time region is that the sync pattern detection signal and the frame count signal are input at the same time, but the sync pattern detection signal and the frame count signal are consecutively specified times. It may be input at the same time.

FIG. 8 is a block diagram showing the structure of the sync managed circuit in the sync detection circuit according to the third embodiment, and corresponds to the sync managed circuit 30 shown in FIG. A clock signal, a sync pattern detection signal, a frame count signal, and a window interrupt signal are input from the outside, and a sync signal and a reset signal are output.
Further, a sync interpolation permission signal for controlling whether or not to output the interpolation sync signal is externally given.

The coincidence detection circuit 31 outputs a signal when the sync pattern detection signal coincides with the frame count signal. The mismatch detection circuit 32 outputs a signal when the sync pattern detection signal and the frame count signal do not match. The match counter 33 includes a match detection circuit 3
The signal output from 1 is counted, but when the output signal of the mismatch detection circuit 32 is input from the reset terminal R, the count value is reset. That is, the count value of the coincidence counter 33 is the number of times that the sync pattern detection signal and the frame count signal successively coincide. Further, the mismatch count counter 34 counts the signals output from the mismatch detection circuit 32, but the match detection circuit 31 from the reset terminal R is counted.
When the output signal of is input, the count value is reset. That is, the count value of the mismatch count counter 34 is the number of times that the sync pattern detection signal and the frame count signal do not match continuously.

The window width control circuit 35 sets the width of the window time region on the basis of the count value of the coincidence counter 33 and the count value of the non-coincidence counter 34, and sets the output signal to the "H" level during the set width. To Logic circuit 36
Outputs the sync signal when the sync pattern detection signal is input while the output signal of the window width control circuit 35 is at the "H" level. Further, when the sync-interpolation permission signal is at "H" level, only the frame count signal is input, and the interpolating sync signal is output. The logic circuit 37 is
When the sync pattern detection signal or the frame count signal is input while the output signal of the window width control circuit 35 is at "H" level, the reset signal is output.

When the window interrupt signal is input, the window width control circuit 35 sets the width of the window time region to infinity and sets the output signal to the "H" level.

By using the sync managed circuit as shown in FIG. 8, the sync detection circuit according to the third embodiment can be realized.

(Fourth Embodiment) The method of outputting the interpolated sync signal when only the frame counter signal is input as shown in the second embodiment is the reliability of the operation of the circuit using the sync signal. It is extremely effective in increasing the However, as can be seen from the timing chart of FIG. 6, when the sync pattern detection signal is delayed from the frame count signal and is input in the window time domain, the interpolated sync signal and the sync signal by the sync pattern detection signal are Two sync signals are output in one frame. Therefore, the reliability of the operation of the circuit that uses the sync signal may decrease.

The fourth embodiment prevents the output of two or more sync signals per frame.

FIG. 9 is a block diagram of a sync detection circuit according to the fourth embodiment of the present invention. In FIG. 9, 10 is a sync pattern detection circuit, 20 is a frame counter, and 40.
Is a sync managed circuit, and 50 is an error detection circuit.

The sync pattern detection circuit 10 performs sync pattern matching on the input digital data and outputs a sync pattern detection signal when the same bit pattern as the sync pattern is detected.

The frame counter 20 outputs a frame count signal when the input clock signal is counted by the number of bits of one frame of the input digital data. When the reset signal is input from the sync managed circuit 40, the count of the clock signal is reset.

The sync managed circuit 40, in accordance with the input sync pattern detection signal and the frame count signal, provides a variable-length first window time domain and second window time domain having the same period as the sync signal in the circuit. Set to. The first sync signal is output when the sync pattern detection signal is input within the first window time domain, and the first sync signal is output when the sync pattern detection signal is input outside the first window time domain. No signal is output. When the sync pattern detection signal is input within the second window time domain, the second sync signal is output, and when the sync pattern detection signal is input outside the second window time domain, the second sync signal is output. Do not output sync signal. In addition, when the sync pattern detection signal is input and the frame count signal is input in the first window time region, the reset signal is set to the frame counter 2
Output to 0.

The error detection circuit 50 determines the error of the input digital data based on the first sync signal output from the sync management circuit 40.

FIG. 10 is a timing chart for explaining the operation of the sync detecting method according to the fourth embodiment of the present invention.

Here, the method of setting the first window time domain and the method of outputting the first sync signal and the reset signal are the same as those in the third embodiment. The second window time domain setting method and the second sync signal output method are the same as those in the third embodiment.
The difference is that the second window time domain is closed when the sync signal is output.

First, since the first sync pattern detection signal is input at the correct timing, the reset signal, the first sync signal and the second sync signal are output.

It is assumed that the timing is shifted backward from the second sync pattern detection signal. The first sync signal and the second sync signal are not output because they are out of the first window time domain and the second window time domain.
When the frame count signal is input, the interpolated sync signal is output as the first sync signal and the second sync signal.

Since the sync pattern detection signal and the frame count signal are not input at the same time twice in a row, the area widths of the next first window time area and second window time area become wider. Then, since the next sync pattern detection signal enters the first window time region, the first sync signal is output. Further, since the interpolating sync signal is output when the frame count signal is input, two first sync signals are output in this frame.

However, since the second window time domain is closed while the first second sync signal is output, the second second sync signal is not output. Therefore, as the second sync signal, only the interpolated sync signal is output in this frame.

Further, since the reset signal is output when the sync pattern detection signal is input, the timing is matched with the frame count signal from the next sync pattern signal.

As described above, according to the sync detecting method of the fourth embodiment, only one second sync signal is always output per frame, and two or more second sync signals are never output. Therefore, by using this second sync signal, the reliability of the operation of the circuit using the sync signal can be improved.

FIG. 11 is a block diagram showing the structure of the sync managed circuit in the sync detecting circuit according to the fourth embodiment, and corresponds to the sync managed circuit 40 shown in FIG. A clock signal, a sync pattern detection signal, a frame count signal, and a window interrupt signal are input from the outside, and a sync signal and a reset signal are output. Further, a sync interpolation permission signal for controlling whether or not to output the interpolation sync signal is externally given. Note that FIG.
The same reference numerals are used for the elements common to the components of the sync managed circuit shown in FIG.

The first window width control circuit 41 uses the count value of the match counter 33 and the mismatch counter 34.
Set the width of the window time domain based on the count value of
The output signal is set to the "H" level for the set width. The logic circuit 42 as the first logic circuit outputs the first sync signal when the sync pattern detection signal is input when the output signal of the first window width control circuit 41 is at the “H” level. Further, when the sync-interpolation permission signal is at "H" level, only the frame count signal is input, and the interpolating sync signal is output. The logic circuit 43 outputs a reset signal when the sync pattern detection signal or the frame count signal is input when the output signal of the first window width control circuit 41 is at “H” level.

The second window width control circuit 44 uses the count value of the match counter 33 and the mismatch counter 34.
Set the width of the window time domain based on the count value of
The output signal is set to the "H" level for the set width. The logic circuit 45 as the second logic circuit outputs the second sync signal when the sync pattern detection signal is input when the output signal of the second window width control circuit 44 is at the “H” level. The second sync signal is fed back to the second window width control circuit 44, and the second window width control circuit 44 sets the output signal to the “L” level when the second sync signal is input. Further, when the sync-interpolation permission signal is at "H" level, only the frame count signal is input, and the interpolating sync signal is output.

When the window interrupt signal is input, the first window width control circuit 41 and the second window width control circuit 44 set the window time region width to infinity and set the output signal to "H". To level.

By using the sync managed circuit as shown in FIG. 11, the sync detection circuit according to the fourth embodiment can be realized.

[0108]

As described above, according to the present invention,
By setting the window time region, since the sync pattern matching is performed only in the vicinity of the timing when the correct sync pattern signal is inserted, it is possible to prevent the malfunction due to the detection of the pseudo sync pattern. In addition, since the area width of the window time area is variable, even if the timing of the sync pattern detection signal is deviated, the area width of the window time area can be controlled each time. , Can be more flexible.

Furthermore, by outputting the interpolated sync signal, the sync signal is not lost in each frame of the digital signal, so that the reliability of the operation of the circuit using the sync signal can be improved.

Further, since processing by an interrupt signal from the outside is provided, it is possible to immediately deal with an operation different from the ordinary one such as skipping reproduction of music in the mini disk device.

Furthermore, since it is possible to prevent two or more sync signals from being output per frame, it is possible to improve the reliability of the operation of the circuit using the sync signals.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a sync detection circuit according to first to third embodiments of the present invention.

FIG. 2 is a flowchart showing a window time domain setting method in the sync detection method according to the present invention.

FIG. 3 is an operation timing chart in the sync detecting method according to the first embodiment of the present invention.

FIG. 4 is an operation timing chart in the sync detecting method according to the first embodiment of the present invention.

FIG. 5 is an operation timing chart in the sync detecting method according to the first embodiment of the present invention.

FIG. 6 is an operation timing chart in the sync detecting method according to the second embodiment of the present invention.

FIG. 7 is an operation timing chart in the sync detecting method according to the third embodiment of the present invention.

FIG. 8 is a configuration diagram of a sync managed circuit in a sync detection circuit according to a third embodiment of the present invention.

FIG. 9 is a configuration diagram of a sync detection circuit according to a fourth embodiment of the present invention.

FIG. 10 is an operation timing chart in the sync detecting method according to the fourth embodiment of the present invention.

FIG. 11 is a configuration diagram of a sync managed circuit in the sync detection circuit according to the fourth embodiment of the present invention.

FIG. 12 is a block diagram showing a schematic configuration of a mini disk device.

FIG. 13 is a block diagram showing a schematic configuration of an EFM demodulation circuit.

FIG. 14 is a diagram showing an example of a sync pattern.

[Description of Codes] 10 Sync Pattern Detection Circuit 20 Frame Counter 30 Sync Managed Circuit 31 Match Detection Circuit 32 Mismatch Detection Circuit 33 Match Count Counter 34 Mismatch Count Counter 35 Window Width Control Circuit 36 Logic Circuit 37 Logic Circuit 40 Sync Managed Circuit 41 1st 1 window width control circuit 42 logic circuit (first logic circuit) 43 logic circuit 44 first window width control circuit 45 logic circuit (second logic circuit) 50 error detection circuit

Claims (17)

[Claims] 1. When detecting a sync pattern from frame synchronously modulated digital data, a variable length window time region is set, and the region width of the window time region is controlled according to past sync pattern detection accuracy. A sync detection method characterized by the above. 2. A sync detection method for detecting the sync pattern signal from a digital signal in which a sync pattern signal is inserted for every fixed number of bits by frame synchronous modulation, and outputting the sync signal. When a signal pattern that is the same as the signal pattern of the sync pattern signal is detected, a sync pattern detection step of outputting a sync pattern detection signal, and a variable-length window time region having the same time period as the insertion of the sync pattern signal are set. And a sync manage step of outputting the sync signal indicating that the correct sync pattern signal is detected when the sync pattern detection signal is output within the window time domain. Sync detection method. 3. The sync detection method according to claim 2, wherein the clock signal synchronized with the digital signal is counted, and the count number is the bit number of one frame including the fixed number of bits and the sync pattern signal. Further includes a frame counting step of outputting a frame count signal, wherein the sync managing step includes the window based on a timing at which the sync pattern detection signal is output and a timing at which the frame count signal is output. A first process of setting a region width of the time region; a second process of outputting the sync signal when the sync pattern detection signal is output in the window time region; and a sync process in the window time region. When the pattern detection signal or the frame count signal is output A third process of outputting a reset signal, wherein the frame counting step has a process of resetting the count number of the clock signal when the reset signal is output. Sync detection method. 4. The sync management step according to claim 3, further comprising a fourth process of outputting a sync signal when the frame count signal is output in the window time domain. Sync detection method. 5. The sync detecting method according to claim 4, further comprising an error determining step of determining whether or not there is an error in the digital signal based on the sync signal. 6. The sync managed step further includes a fifth process for making the area width of the window time area infinite by an interrupt signal from the outside. The sync detection method according to item 1. 7. The sync detection method according to claim 4, further comprising the same processing as each of the first, second, and fourth processing, and processing for closing a window time domain when the sync signal is output. A sync detecting method, further comprising another sync managing step. 8. The sync detection method according to claim 6, wherein the same processing as each of the first, second, fourth and fifth processings,
A sync detecting method, further comprising another sync managing step having a process of closing a window time domain when the sync signal is output. 9. The first processing initially sets the window width of the window time area to infinity, and when the timings of the sync pattern detection signal and the frame count signal coincide with each other for the first predetermined number of times, The window time region is set to have a finite width and is set at the same timing as the frame count signal, and the region width of the window time region is set to a second value.
When the timings of the sync pattern detection signal and the frame count signal coincide with each other a predetermined number of times, the process is narrowed, and when the timings of the third predetermined number of times are not consistent, the process is widened. 9. The sync detecting method according to claim 3, wherein the sync detecting method is a sync detecting method. 10. The first process initially sets the window width of the window time region to infinity, and when the timings of the sync pattern detection signal and the frame count signal coincide with each other for the first predetermined number of times, The window time region is set at the same timing as the frame count signal after making the region width a finite length, and further, the region width of the window time region is output in the window time region by the sync pattern detection signal. If the sync pattern detection signal is not output in the window time region, it is widened when the second predetermined number of consecutive occurrences occurs. The sync detection method according to claim 3, further comprising: 11. A sync detection circuit which receives as input a digital signal in which a sync pattern signal is inserted in every fixed number of bits by frame synchronous modulation, and detects the sync pattern signal from the digital signal and outputs the sync signal. And a sync pattern detection circuit that outputs a sync pattern detection signal when the same signal pattern as the sync pattern signal is detected from the digital signal as an input, and the insertion of the sync pattern signal. A variable length window time domain having the same time cycle as that of the above is internally set, and the sync signal indicating that the correct sync pattern signal is detected when the sync pattern detection signal is input in the window time domain is output. And a sync managed circuit that That sync detection circuit. 12. The sync detection circuit according to claim 11, wherein the clock signal synchronized with the digital signal is counted, and the count number is the bit number of one frame including the fixed number of bits and the sync pattern signal. Further includes a frame counter for outputting a frame count signal, wherein the sync managed circuit is configured to perform the window time based on a timing at which the sync pattern detection signal is input and a timing at which the frame count signal is input. A function of setting the area width of the area, a function of outputting the sync signal when the sync pattern detection signal is input in the window time area, and the sync pattern detection signal or the frame count in the window time area. When a signal is input A counter that outputs a reset signal to the counter, and the frame counter has a function of resetting the count number of the clock signal when the reset signal is input. Detection circuit. 13. The sync managed circuit sets an area width of a window time area on the basis of a timing of inputting a sync pattern detection signal and a timing of inputting a frame count signal, and sets the area width of the window time area and the window time area. A window width control circuit that outputs a signal having a different logic level outside the time domain, and a signal output from the window width control circuit as an input, while the logic level of the signal is the logic level within the window time domain 13. The sync detection circuit according to claim 12, further comprising a logic circuit that outputs a sync signal when the sync pattern detection signal is input to. 14. The sync detection circuit according to claim 13, wherein when the logic circuit is instructed to output an interpolation sync signal by a sync interpolation permission signal from the outside, the output of the window width control circuit is output. A sync detection circuit which outputs the sync signal when the frame count signal is input while the logic level of the signal is within the window time domain. 15. The sync detection circuit according to claim 13, wherein the window width control circuit, when the sync signal is output from the logic circuit, sets the logic level of the output signal to a logic level outside the window time region. Sync detection circuit characterized by changing to. 16. A sync detecting circuit for inputting a digital signal in which a sync pattern signal is inserted at every fixed number of bits by frame synchronous modulation, detecting the sync pattern signal from the digital signal, and outputting the sync signal. And a sync pattern detection circuit that outputs a sync pattern detection signal when the same signal pattern as the sync pattern signal is detected from the digital signal as an input, and a sync pattern detection circuit that synchronizes with the digital signal. A clock counter that counts the number of clock signals, and outputs a frame count signal when the count number reaches the bit number of one frame composed of the fixed number of bits and the sync pattern signal; and inserting the sync pattern signal. Variable length first wi with the same time period Window time domain and second window time domain are internally set based on the timing at which the sync pattern detection signal is input and the timing at which the frame count signal is input, and the window time domain and the second window time domain are set in the first window time domain. The first sync signal is output when the sync pattern detection signal is input, while the second sync signal is output when the sync pattern detection signal is input within the second window time region. A sync managed circuit that closes a second window time region, wherein the sync managed circuit resets the frame counter when the sync pattern detection signal or the frame count signal is input within the first window time region. The frame counter outputs the reset signal. Sync detection circuit, characterized in that resetting the count of said clock signal when. 17. The sync detection circuit according to claim 16, wherein the sync managed circuit is configured to detect the sync pattern detection signal based on a timing at which the sync pattern detection signal is input and a timing at which the frame count signal is input. A first window width control circuit that sets a region width of the window time region and outputs signals having different logic levels in the first window time region and outside the first window time region; When the signal output from the window width control circuit is input and the sync pattern detection signal is input while the logic level of the signal is the logic level in the first window time region, the first sync A first logic circuit that outputs a signal, a timing at which the sync pattern detection signal is input, and the frame The area width of the second window time area is set based on the timing at which the count signal is input, and signals having different logic levels are set in the second window time area and the second window time area. A second window width control circuit for outputting, and a signal output from the second window width control circuit as input, while the logic level of the signal is at the logic level in the second window time domain, A second logic circuit that outputs the second sync signal when the sync pattern detection signal is input, wherein the second window width control circuit includes the second logic circuit and the second logic circuit. A sync detection circuit, wherein when a sync signal is output, the logic level of the output signal is changed to a logic level outside the second window time region.