JP2001236742A - Information reproducing device and method and synchronous circuit and method for reproducing information - Google Patents

Abstract

PROBLEM TO BE SOLVED: To take synchronism of the data in a short time when the data recorded on an information recording medium are reproduced. SOLUTION: A reproducing device 5 reproduces the block of the information recording medium, and a synchronous circuit 10 of an MPU 1 detects respective address data reproduced from the block, and counts respectively the number of address data detection from being detected initially until being detected again at every address data, and compares the number of respective address data detection with a prescribed value to judge whether or not they agree, and when they agree, sets the detected address data as the address of a data read-out destination, and when not agree, corrects the address data to be reproduced next of the address data based on the address data set as the address of the data read-out destination-just before and is set.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information reproducing method for reproducing data recorded on an information recording medium such as an optical disk, a magneto-optical disk, a magnetic disk, a magnetic tape, and a memory card, and a method for reproducing reproduced data in an information reproducing apparatus. The present invention relates to a synchronization method and a synchronization device for achieving synchronization.

[0002]

2. Description of the Related Art When reproducing data (information) recorded on an information recording medium, after detecting a synchronization code, a time position at which a next synchronization code is detected is predicted, and whether or not the prediction is correct is determined. A synchronizer (for example, Japanese Patent Application Laid-Open No. H10-134515) that determines whether to continue the current synchronization or to detect a synchronization code other than the predicted position and perform resynchronization.
Reference).

[0003]

However, in the above-mentioned conventional synchronizer, data is synchronized by detecting a synchronization code recorded at a predetermined cycle, so that when the first synchronization code is detected, the information recording medium is not recorded. If the synchronization code cannot be detected correctly or a false synchronization code is detected due to a defect such as a defect, it takes a long time to correctly synchronize the data. In addition, after detecting a synchronization code, the necessity of resynchronization is determined based on whether or not the next synchronization code is detected at the predicted position. There was a problem that it took time.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problem, and has as its object to synchronize data in a short time when reproducing data recorded on an information recording medium.

[0005]

According to the present invention, in order to achieve the above object, one block is composed of a plurality of data and address data indicating the order of each data in the block, and the plurality of blocks are recorded. A plurality of address data detecting means for respectively detecting each address data reproduced from the block, and an address data detected by each means. A plurality of address data detection number counting means for counting the number of address data detections from the detection of the address data to the detection of the address data each time, and the number of address data detections counted by each means are preset. Determining means for comparing with a predetermined value to determine whether or not they match each other; When it is determined that they match, the address data detected by each of the address data detecting means is set as a data read destination address, and when it is determined that they do not match, the address data set immediately before as the data read destination address Address data setting means for correcting and setting the address data to be reproduced next to the address data based on the address data.

Further, in the information reproducing apparatus as described above, the judging means compares each address data detection number counted by each address data detection number counting means with a predetermined value set in advance, and determines whether or not they match. It is preferable to include a plurality of judging means for judging whether or not each is not.

[0007] Further, one block is composed of a plurality of data and address data indicating the order of each data in the block, and the information reproducing means includes means for reproducing data of an information recording medium in which the plurality of blocks are recorded. In the device,
First counting means for setting address data reproduced from the block and counting addresses sequentially from the address data; and comparing the address data counted by the means with the address data reproduced from the block. A first judging means for judging whether or not the address data coincides with each other; and, based on the judgment by the means, the address data reproduced from the block starting from the setting of the address data and the first counting means. A second counting means for counting the number of times the counted address data continuously matches, and comparing the number counted by the means with a predetermined value to determine whether the number is greater than or equal to the predetermined value. Second determining means for determining whether the number of times is equal to or greater than the predetermined value. At this time, the address data counted by the first counting means or the address data reproduced from the block is set as a data read destination address, and when it is determined that the number of times is not more than the predetermined value, It is preferable to provide third counting means for correcting and setting the address data to be reproduced next to the address data based on the address data set as the data read destination address immediately before.

Further, in the above information reproducing apparatus, it is preferable to provide a means for externally inputting and holding the predetermined value set in the second counting means.

Also, in the information reproducing method for reproducing data of an information recording medium in which one block is composed of a plurality of data and the order of each data in the block, and the plurality of blocks are recorded, Detect each address data reproduced from within the block,
For each of the detected address data, the number of detected address data from the detection of the address data to the detection of the address data again is counted, and each of the counted number of detected address data is set to a predetermined predetermined value. Compare and determine whether or not they match each other. When each of the determinations indicates a match, set the detected address data as the address of the data readout address. It is preferable to correct the address data to be reproduced next to the address data based on the address data set as the data read destination address.

Also, in the information reproducing method for reproducing data on an information recording medium in which one block is composed of a plurality of data and address data indicating the order of each data in the block, The address data reproduced from the block is set, the addresses are counted sequentially from the address data, and the counted address data is compared with the address data reproduced from the block to determine whether or not they match. Judging, based on the judgment, counting the number of times that the address data reproduced from the block and the counted address data continuously match starting from the time when the address data is set, and counting the number of times. The number of times is compared with a predetermined value set in advance to determine whether the number is equal to or greater than the predetermined value. If the number is determined to be equal to or more than the predetermined value, the counted address data or the address data reproduced from the block is set as a data read destination address, and the number of times is reduced. When it is determined that the address data is not equal to or larger than the predetermined value, the address data to be reproduced next to the address data may be corrected and set based on the address data set immediately before as the data read destination address.

Further, in the information reproducing method as described above, it is preferable that the predetermined value is externally input and held.

Also, one block is composed of a plurality of data and address data indicating the order of each data in the block, and the information is synchronized when reproducing the data of the information recording medium in which the plurality of blocks are recorded. A plurality of address data detecting circuits for detecting each address data reproduced from the block in the reproducing synchronizing circuit, and detecting the address data for each address data detected by each circuit, and then detecting the address data again A plurality of address data detection number counting circuits for counting the number of address data detections until the address data detection is performed, and comparing each address data detection number counted by each of the circuits with a predetermined value to determine whether or not they match. And a judgment circuit for judging whether The address data detected by the address data detection circuit is set as a data read destination address, and when it is determined that they do not match, the address data is set next to the address data based on the address data set immediately before as the data read destination address. It is preferable to provide an address data setting circuit for correcting and setting the address data to be reproduced.

Further, in the information reproduction synchronous circuit as described above, the determination circuit compares each address data detection number counted by each address data detection number counting circuit with a predetermined value set in advance to match. It is preferable to include a plurality of determination circuits for determining whether or not to perform the determination.

Further, one block is composed of a plurality of data and address data indicating the order of each data in the block, and the information is synchronized when reproducing the data of the information recording medium in which the plurality of blocks are recorded. In a reproduction synchronizing circuit, a first count circuit for setting address data reproduced from the block and counting addresses in order from the address data; an address data counted by the circuit; A first determination circuit that compares the address data with the address data to determine whether they match, and based on the determination by the circuit,
A second counting circuit for counting the number of times that the address data reproduced from within the block and the address data counted by the first counting circuit continuously coincide with each other starting from when the address data is set; A second determining circuit that compares the number counted by the circuit with a predetermined value set in advance to determine whether the number is equal to or greater than the predetermined value, and the circuit determines that the number is equal to or greater than the predetermined value. The address data counted by the first counting circuit or the address data reproduced from the block is set as a data read destination address, and when it is determined that the number of times is not more than the predetermined value. Is the address based on the address data set as the data read destination address immediately before. It may be provided with a third counting circuit to be set by correcting the address data to be reproduced next over data.

Further, in the information reproducing synchronous circuit as described above, it is preferable to provide a circuit for externally inputting and holding the predetermined value set in the second count circuit.

Also, one block is composed of a plurality of data and address data indicating the order of each data in the block, and the information is synchronized when reproducing the data of the information recording medium in which the plurality of blocks are recorded. In the reproduction synchronizing method, each address data reproduced from the block is detected, and the number of detected address data from the detection of the address data to the detection of the address data for each of the detected address data is determined. It counts and compares each counted address data detection number with a predetermined value set in advance to judge whether or not they match, and when it is judged by each judgment that they match, each detected address is detected. Set the data as the data read destination address, and if it is determined that they do not match, read the data immediately before Based on the address data set as the previous address may be set to correct the address data to be reproduced next the address data.

Also, one block is composed of a plurality of data and address data indicating the order of each data in the block, and the information to be synchronized when reproducing the data of the information recording medium in which the plurality of blocks are recorded. In the reproduction synchronization method, address data reproduced from the block is set, addresses are sequentially counted from the address data, and the counted address data is compared with the address data reproduced from the block. The number of times that the address data reproduced from the block and the counted address data successively match, starting from when the address data is set, based on the determination. Count,
The counted number is compared with a predetermined value set in advance to determine whether or not the number is equal to or greater than the predetermined value. If the number is determined to be equal to or greater than the predetermined value, the counted address is determined. Data or address data reproduced from the block is set as a data read destination address, and when it is determined that the number of times is not equal to or greater than the predetermined value, the address data set immediately before as the data read destination address , The address data to be reproduced next to the address data may be corrected and set.

Further, in the information reproducing synchronization method as described above, it is preferable that the predetermined value is externally input and held.

[0019]

Embodiments of the present invention will be specifically described below with reference to the drawings. FIG. 2 is an explanatory diagram showing an example of a data format recorded on the information recording medium used in the embodiment of the present invention.

This information recording medium is a CD, CD-R, C
Various types of disk-shaped media such as D-RW, DVD, MO, magnetic disk, etc., which are read-only, recordable, and rewritable for information.

A plurality of blocks are recorded on this information recording medium. As shown in FIG. 2, 16 blocks of 8-bit data are stored in one block. Is added with 4-bit in-block address data (hereinafter abbreviated as "address data") indicating the order in each block.

When reproducing address data and data from an information recording medium having such a format, an error may occur in reading the address data and data due to a defect such as a defect of the information recording medium. Usually, when a reading error occurs, it takes a long time to synchronize with the correct address data.

Therefore, in the information reproducing apparatus, the information reproducing method, the information reproducing synchronizing circuit and the information reproducing synchronizing method of this embodiment, the address data on the information recording medium is obtained by performing the following configuration or processing procedure. During reproduction, even if a reading error occurs, synchronization with the correct address data can be performed in a short time.

(1) First Embodiment of the Present Invention FIG. 1 is a functional block diagram showing a schematic configuration of an information reproducing apparatus according to a first embodiment of the present invention.

This information reproducing device is a device for reproducing information on a disk-shaped recording medium such as an optical disk device, a magneto-optical disk device, and a magnetic disk device, and has an arithmetic processing unit (Micro Programming Unit: M).
PU) 1, a memory 2, a data input unit 3, a data output unit 4, a reproducing device 5, and an input device 6, etc., which are connected to each other via a data bus 7 so as to be able to exchange data.

The MPU 1 is a microcomputer realized by a CPU, and includes a synchronization circuit 10 having a plurality of address data detection units, a plurality of data counters, a comparison unit, an address counter, and the like. Output and arithmetic processing are performed, and the synchronization circuit 10 executes the synchronization processing according to the first, second and fifth aspects of the present invention.

The memory 2 is a storage device for storing various data. The data input unit 3 inputs the data of each block reproduced from the information recording medium 8 by the reproducing device 5, and inputs the address data and the data in the block into 12 blocks.
Output as bit data. The data output unit 4 outputs the MP
U1 outputs data processed in block units.

The reproducing device 5 reproduces the data of the block of the information recording medium 8 and sends it to the data input section 3. Input device 6
Is input means such as a keyboard for inputting data such as various predetermined values (parameters).

That is, the reproducing apparatus 5 reproduces data of an information recording medium in which one block is composed of a plurality of data and address data indicating the order of each data in the block, and the plurality of blocks are recorded. Acts as a means.

The synchronizing circuit 10 includes a plurality of address data detecting means for detecting each address data reproduced from the block, and detecting the address data for each address data detected by each means. A plurality of address data detection number counting means for respectively counting the number of address data detections from when the address data is detected until the address data is detected again, and compares each address data detection number counted by each means with a predetermined value set in advance. And performs the function of a judging means for judging whether or not they match.

Further, when it is determined by the determining means that they match, the synchronization circuit 10 sets the address data detected by the respective address data detecting means as a data read destination address, and determines that they do not match. In this case, the address data setting means corrects and sets the address data to be reproduced next to the address data based on the address data set as the data read destination address immediately before.

Next, a description will be given of a synchronization process at the time of reproduction in the information reproducing apparatus of the first embodiment. In this process, only the process of reading address data of a data amount corresponding to a plurality of blocks input to the memory 2 and detecting a break of each block is shown.

First, the data input unit 3 converts the address data and data of each block reproduced from the information recording medium 8 by the reproducing device 5 into MPUs as 12-bit data.
1 and the MPU 1 inputs it to the memory 2 and stores it.

Next, the outline of the synchronization processing by the synchronization circuit 10 of the MPU 1 will be described. First, the synchronization circuit 10 reads 4-bit address data, counts the number of address data until the next time the same address data is read by a data counter, and reads out the data if the count value is the number of data for one block. It is determined that there is no error in the address data, and the address data is set in the address counter.

On the other hand, when the count value of the number of address data by the data counter is not the number of data of one block, the address counter reads one address data and simultaneously reads the value of the data counter corresponding to another address data. Increase by one.

In this way, the synchronization circuit 10 detects each piece of address data reproduced from within the block of the information recording medium, and for each detected address data, from when the address data is detected until it is detected again. Are detected, and the counted number of detected address data is compared with a predetermined value to determine whether or not they match.

When it is determined in each determination that the addresses match, the detected address data is set as the address of the data read destination, and when it is determined that they do not match, the address is set immediately before as the address of the data read destination. Based on the address data, the address data is corrected and set to the next address data to be reproduced.

Thus, by preparing 16 data counters for counting the number of data and counting the number of data for each address data, correct address data can be set in the address counter in a short time.

FIG. 3 shows the M of the information reproducing apparatus according to the first embodiment.
4 is a flowchart illustrating a synchronization process in a synchronization circuit of a PU. First, variables of the address counter and the data counter described in the flowchart of FIG. 3 will be described.

The address counter (AD_CNT) is 4
Address counter of bit counter, initial value = 0
And counts cyclically through the values 0-15. The data counter (D_CNT (i)) is composed of 16 data counters. Each data counter is a 4-bit counter corresponding to the read address value (i = 0 to 15). The values 0 to 15 are circulated and counted.

As shown in FIG. 3, in this processing, an initial value is set in step (indicated by “S” in the figure) 1 and
The process proceeds to step 3 to read the address data, proceeds to step 3, adds "1" to the value of AD_CNT, sets the address counter again, proceeds to step 4, sets the read address data to i, and proceeds to step 5. And D_C
It is determined whether NT (i) = 0.

D_CNT (i) = 0 in the judgment of step 5
If not, proceed to step 8 and D_CNT (i) = 0
And proceed to step 7. On the other hand, if D_CNT (i) = 0 in the judgment of step 5, "i" is set in AD_CNT and the process proceeds to step 7. In step 7, “1” is added to the value of D_CNT (j) for j = 0 to 15, the value is set to D_CNT (j) again, and the process returns to step 2.

Next, the above processing will be described using specific numerical values with reference to FIG. First, when address data “0” is read, the address counter counts up to “1” and determines whether D_CNT (0) = 0.

At first, since D_CNT (0) = 15,
The determination result is NO, D_CNT (0) is reset to 0, and D_CNT (i) is incremented by “1” for each of i = 0 to 15, and D_CNT (0) = 1, D_CNT (0) = 1.
_CNT (1) to D_CNT (15) = 0.

Thus, the address data 1 to 15
When the same address data is read out and the same address data is read out again, the same processing can be performed as the correct address data.

As described above, in the data counting process by the data counter, D_CNT (i) corresponding to the read address value (i) is set to 0, and is incremented by 1 every time address data is read. If the address value read at the 16th time is the same, D_CNT (i) goes around once and becomes 0 again.

At this time, the same address data is read out in one block cycle, and it can be determined that the address data is correct. Therefore, the address data is set in the address counter.

On the other hand, when the address data is incorrect,
The address counter increments the value of the data counter corresponding to the other address data by one while reading one address data.

Therefore, only when it is determined that the read address data is correct, the address value is set in the address counter, and when the read address data is not correct, the address is counted up without using the read address data. To provide synchronization.
After that, according to the address data output by the address counter, the MPU 1 performs data processing in block units and outputs data.

In the above information reproducing apparatus, the synchronization circuit 1
It is preferable to provide a plurality of 0 comparison circuits. That is, the synchronization circuit 10 includes a plurality of judging means for comparing each detected address data number counted by each address data detected number counting means with a predetermined value, and judging whether each address data coincides with each other. Fulfills the function of means consisting of

The processing in this case is the same as the processing shown in FIGS. 3 and 4, and a description thereof will be omitted. However, since comparison can be made for each address data, synchronization can be achieved in a shorter time.

In the information reproducing apparatus of the first embodiment, whether or not a specific value of an address in a block is detected in a block cycle is determined in parallel for a plurality of pieces of address data. Can be synchronized.

(2) Second Embodiment of the Invention The information reproducing apparatus according to the second embodiment has almost the same configuration as the apparatus shown in FIG. And a plurality of comparison circuits, and the synchronization processing to be executed is also different.

That is, the synchronizing circuit 10 sets address data reproduced from the block, counts the addresses sequentially from the address data, and counts the address data counted by the means. The function of the first judging means is to be compared with the address data reproduced from within the block to judge whether or not they match.

Further, based on the judgment by the first judging means, starting from when the address data is set, the address data reproduced from the block and the first
A second counting means for counting the number of times that the address data counted by the counting means are continuously matched; and comparing the number counted by the means with a predetermined value to set the number to the predetermined value. The function of the second determining means for determining whether or not the above is also fulfilled.

When the number of times is determined by the second determining means to be equal to or greater than the predetermined value, the address data counted by the first counting means or the address data reproduced from the block is read out. If the number of times is determined not to be equal to or greater than the predetermined value, the address data to be reproduced next to the address data based on the address data previously set as the data read destination address And performs the function of third counting means for setting the correction.

Further, the input device 6 and the synchronization circuit 10 function as means for externally inputting and holding the predetermined value set in the second counting means.

Next, a description will be given of a synchronization process at the time of reproduction in the information reproducing apparatus according to the second embodiment. In this process, as in the process of the information reproducing apparatus of the first embodiment, only the process of reading the address of data corresponding to a plurality of blocks input to the memory and detecting a block break is shown. .

Next, an outline of the synchronization processing by the synchronization circuit 10 of the MPU 1 will be described. The synchronization circuit 10 first reads a 4-bit address and a first counter (first counting means)
Set to. The first counter is incremented by one each time address data is read.

Further, the address data read by the first comparison circuit is compared with the count value of the first counter,
The number of times that both match continuously is counted by a second counter (second counting means). In this way, it is confirmed that the read address data is increased one by one and is continued a plurality of times.

If the address data read by the first comparison circuit does not match the count value of the first counter, the address data read out is set in the first counter, and at the same time, 1 is set in the second counter. Prepare for the count of the next consecutive address match.

When the count value of the second counter becomes equal to or greater than the specified value held from the outside by the second comparison circuit, the address data read during that time is correct because the specified value is continuous. It is determined that the address data is the address data, and the read address data or the first counter has the same value, and the address data based on the count value is set in the third counter (third counting means) corresponding to the address counter. Count.

On the other hand, if the read address data is incorrect, the third counter, which is the address counter,
At the same time as reading one address data value, the count values of the other first and second counters are also incremented by one.

Thus, the synchronization circuit 10 sets the address data reproduced from within the block of the information recording medium,
Count addresses sequentially from that address data,
The counted address data is compared with the address data reproduced from the block to determine whether or not they match.

Based on the judgment, starting from the time when the address data is set, the number of times that the address data reproduced from the block and the counted address data successively coincide with each other is counted. The number of times is compared with a predetermined value, and it is determined whether the number is equal to or greater than the predetermined value.

When it is determined that the number of times is equal to or more than the predetermined value, the counted address data or the address data reproduced from the block is set as a data read destination address. When it is determined that the number of times is not equal to or greater than the predetermined value, the address data to be reproduced next to the address data is set based on the address data set immediately before as the data read destination address.

FIG. 5 is a block diagram of the information reproducing apparatus according to the second embodiment.
4 is a flowchart illustrating a synchronization process in a synchronization circuit of a PU. First, each counter and the variable of the designated value described in the flowchart of FIG. 5 will be described.

The first counter (CNT1) is a 4-bit counter, and sets the read address data when the read address data does not match the count value. The initial value is 0, and counting is performed by circulating from 0 to 15.

The second counter (CNT2) has an initial value = 0.
The number of times that the read address data and the count value of the first counter match continuously is counted, and if they do not match, 1 is set.

The third counter (CNT3) is a 4-bit counter. When the count value of the second counter exceeds a predetermined value, the third counter (CNT3) sets the count value of the first counter to indicate a correctly corrected address. It is an address counter. It counts by circulating 0 to 15 with the initial value = 0.

The specified value is set in the second comparison circuit,
This is a value to be compared with the count value of the counter, and is a threshold value for determining how long the read address data continues to be determined to be correct. An arbitrary parameter value according to the degree of error occurrence of the recording information medium can be externally set from the input device 6, but may be a fixed value set in advance.

As shown in FIG. 5, in this processing, an initial value is set in a step (indicated by "S" in the figure) 11 and the process proceeds to a step 12 to read address data.
The program proceeds to step 14 to add "1" to the values of CNT3 and CNT1, respectively.
It is determined whether or not the count value of T1 matches the read address data.

If it is determined in step 14 that the count value of CNT1 does not match the read address data, the flow advances to step 18 to set the read address data to CNT3, and the flow advances to step 19 to set "1" to CNT2. Then, the process returns to step S12.

On the other hand, if it is determined in step 14 that the count value of CNT1 matches the read address data, the flow advances to step 15 to add "1" to the count value of CNT2. By CN
It is determined whether or not the count value of T2 is equal to or greater than the specified value. If not, the process returns to step S12.
If it is greater than the specified value, proceed to step 17
The count value of 1 is set, and the process returns to step S12.

Next, the processing of the flowchart of FIG. 5 will be described with specific numerical values based on the explanatory diagram of FIG. FIG. 6A shows the read address data, and FIG.
(D) shows a change in the count value of the first counter (first CNT) to the third counter (third CNT) for each read address data.

As an example, the read address data starts from 13 as shown in FIG. 6A, and at the time of reading indicated by the mark “x”, 1 which is the address data to be originally read becomes 3 and 4 becomes 7 Each of these figures shows a case where the data is read out erroneously. The specified value is set to 3.

First, the first reset causes the first CNT
0 is set to the third CNT. By comparison of the first comparison circuit, the read address data “13” and the first CN
Since the count value “0” of T does not match, the read address data “13” is set in the first CNT, and the second CN
The count value “1” is set in T.

When the next address data "14" is read, the first CNT and the third CNT each increase by one. Since the read address data "14" matches the first CNT "14", the count value of the second CNT is reduced. Increase by one. Similarly, the read address data and the first CNT
When the count value of the second CNT matches, the count value of the second CNT is increased by one.

Then, the second comparison circuit compares the second
When the count value of CNT becomes more than the specified value “3”,
The count value of the first CNT is set to the third CNT. Here, the read address data “15” and “0” are sequentially set in the third CNT.

Since "3" of the next read address data is erroneous, the first comparison circuit compares the first CNT with the first CNT.
Therefore, the count value “1” is set in the second CNT, and incorrect address data “3” is set in the first CNT. Further, since it does not match the next correctly read address data "2", the first
The read address data “2” is set in the CNT,
The count value “1” is set again in the second CNT.

Thereafter, the read address data "7"
Is incorrect, the count value of the second CNT does not become 3 or more, and the third CNT is incremented by one to correct the address data. When it is confirmed by the comparison of the second comparison circuit that the read address data is continuously correct at 5 to 7, the count value of the first CNT is set to the third CNT.

In this way, when it is determined that the address data is continuously correct for the number of times equal to or greater than the designated value, the first CNT
Count value (= read address data)
Set to NT.

When the specified value is externally set, an arbitrary parameter value is input from the input device 6 and the MP
It is held so that it can be set in the second comparison circuit of the synchronization circuit 10 by U1.

This parameter value is reduced when the error of the recording information medium is small so that correct address data can be set in the third CNT (address counter) in a short time. It is advisable to adjust it to increase the reliability.

The information reproducing apparatus according to the second embodiment confirms that the addresses in the block have been read correctly consecutively for the specified number of times or more, and sets the read address data in the address counter to correct the address. Therefore, synchronization can be achieved in a short time within one block period.

(3) Third Embodiment of the Present Invention The synchronization circuit of the third embodiment is a combination of the information reproducing apparatus of the first embodiment and the other various information recording media such as a magnetic tape and a memory card. It is applied to a device for reproducing data.

FIG. 7 is a functional block diagram showing a configuration of a synchronization circuit according to a third embodiment of the present invention. This synchronization circuit includes n detection circuits, counters, and comparison circuits, and one OR circuit and an address counter, respectively.

The n detection circuits 20a to 20o have n = 0 to 1
5, and the input 4-bit address data is "n".
Is a circuit for detecting that In order to reduce the circuit scale, n = 0, 4, 8, 12, etc. may be set.

The n address number counters 21a to 21o are:
This is a counter that counts the number of data (that is, the number of addresses) from the detection of the address data “n” to the detection of the next same address data “n”.

The comparison circuits 22a to 22o compare each count value of the n-address number counter with "0" when the address data "n" is detected. To output an OK pulse.
If the comparison results do not match, NG is output to the OR circuit 23.
Output pulse.

The address counter 24 includes a comparator 22a
This is a counter for setting input address data by OK pulses of .about.22o, and outputs corrected address data by NG pulses of comparison circuits 22a to 22o.

That is, in this synchronous circuit, when one block is composed of a plurality of data and address data indicating the order of each data in the block, when reproducing data of an information recording medium on which a plurality of blocks are recorded. It performs the function of a synchronizing circuit for information reproduction that synchronizes with the information.

The n detection circuits 20a to 20o are:
Each of the address data counters 21a to 21o corresponds to a plurality of address data detection circuits for detecting each address data reproduced from the block. This corresponds to a plurality of address data detection number counting circuits that respectively count the number of address data detections from when data is detected until the data is detected again.

Further, the comparison circuits 22a to 22o are
This corresponds to a plurality of determination circuits for comparing each detected number of address data counted by each detected address data count circuit with a predetermined value to determine whether or not they match each other.

Further, when the OR circuit 23 and the address counter 24 determine that they coincide with each other, the address data detected by each of the address data detection circuits is set as a data read destination address. If it is determined that they do not match, it corresponds to an address data setting circuit that corrects and sets the address data to be reproduced next to the address data based on the address data set as the data read destination address immediately before.

Next, a description will be given of the synchronization processing during reproduction in the synchronization circuit of the third embodiment. In the basic synchronization processing of this synchronization circuit, one block is composed of a plurality of data and address data indicating the order of each data in the block, and reproduces data of an information recording medium in which the plurality of blocks are recorded. Each address data reproduced from the block is detected, and the number of detected address data is counted for each detected address data from when the address data is detected until it is detected again.

Then, each counted number of detected address data is compared with a predetermined value which is set in advance to judge whether or not there is a match. The data is set as a data read destination address, and when it is determined that they do not match, the address data to be reproduced next to the address data is corrected based on the address data set immediately before as the data read destination address. Set.

Further, the synchronization processing of the synchronization circuit will be described. This synchronization processing is basically the same operation as the processing shown in the flowchart of FIG.
T stores the above-described D_CNT (i) in the address counter 24.
Correspond to the counters of the n-address number counters 21a to 21o, respectively. First, the n address number counters 21a to 21a
21o is set to 1 each time address data is input.
To increase.

The value of the n-address counters 21a to 21o corresponding to the input address data is "0".
That is, the respective address data are detected by the n detection circuits 20a to 20o, and the n address number counters 21a to 21 corresponding to the address data are detected.
When the count value of “o” is “0”, the address counter 24
Is set, and if the count value is not "0", the n-address number counter 21a
Set "0" in ~ 21o to clear.

As described above, when the same address data is detected, if the number of detected address data since the previous detection of the address data is one block cycle, the address data is set in the address counter 24. .

In the synchronous circuit according to the third embodiment, the above-described operation is performed by a separate circuit for a plurality of address data, so that correct address data can be set in the address counter in a short time. In addition, since it is realized as dedicated hardware, high-speed operation and circuit miniaturization are possible.

(4) Fourth Embodiment of the Present Invention In the synchronization circuit of the fourth embodiment, the plurality of comparison circuits of the synchronization circuit of the third embodiment are shared by one comparison circuit, and The configuration is simplified. FIG. 8 is a functional block diagram showing a configuration of a synchronization circuit according to a fourth embodiment of the present invention.

In this synchronous circuit, n detection circuits 30a to 30a-3
0o is in the n-detection circuits 20a to 20o, and the n-address number counters 31a to 31o are in the n-address number counter 2
1a to 21o, the address counter 34 corresponds to the address counter 24, and the comparison circuits 22a to 22o.
22o and the OR circuit 23, one comparison circuit 32 and n-address number counters 31a to 31
Switching function for inputting each count value of o and n
A selector 36 having a function of clearing the address counters 31a to 31o and AND circuits 35a to 35o are provided.

The synchronization processing in this synchronization circuit is substantially the same as the synchronization processing of the information processing apparatus according to the first embodiment, and a detailed description thereof will be omitted.
The address data detected at 30o and the count value of each of the n address number counters 31a to 31o are compared with one comparison circuit 32
The differences are different.

That is, using the selector 36, the n-address counters 31a to 31o output to the comparison circuit 32
Are switched, and the NG pulse outputs of the comparison circuit 32 and the outputs of the n detection circuits 30a to 30o are AND-processed by the AND circuits 35a to 35o to generate clear signals for the n address number counters 31a to 31o.

In the synchronizing circuit of the fourth embodiment, one comparing circuit is used for comparing the address data of 0 to 15 and the count value of each address counter, so that the circuit configuration is simplified. Cost can be reduced.

(5) Fifth Embodiment of the Present Invention The synchronizing circuit of the fifth embodiment is provided with the information reproducing apparatus of the first embodiment and the various other information recording media such as a magnetic tape and a memory card. It is applied to a device for reproducing data.

FIG. 9 is a functional block diagram showing a configuration of a synchronization circuit according to a fifth embodiment of the present invention. This synchronization circuit is composed of three counters and a comparison circuit.

The first counter (first CNT) 40 is a 4-bit counter, and sets the read address data when the read address data does not match the count value. The initial value is 0, and counting is performed by circulating from 0 to 15.

The second counter (second CNT) 41 has an initial value = 0, and counts the number of times that the address data read by the comparison of the first comparison circuit 43 and the count value of the first counter 40 continuously match. If they do not match, 1 is set.

The third counter (third CNT) 42 is a 4-bit counter. When the count value of the second counter 41 exceeds a predetermined value by comparison of the second comparison circuit 44, the count value of the first counter is incremented. An address counter that indicates the address that has been set and correctly corrected. Initial value =
0 is circulated from 0 to 15 and counted.

The first comparison circuit 43 compares the input address data with the count value of the first counter 40. The second comparison circuit 44 compares the designated value with the count value of the second counter 41.

The specified value is set in the second comparison circuit 44,
This is a value to be compared with the count value of the second counter 41, and is a threshold value for determining how long the read address data continues to be determined to be correct. This value can be externally set to an arbitrary parameter value according to the degree of error occurrence of the recording information medium, but may be a fixed value set in advance.

That is, the first counter 40 sets the address data reproduced from the block and counts the addresses in order from the address data. It corresponds to a first determination circuit that compares the address data counted by the count circuit with the address data reproduced from the block and determines whether or not they match.

Further, based on the judgment by the first judgment circuit, the second counter 41 starts counting from the time when the address data is set and counts the address data reproduced from the block and the first count circuit. The second comparing circuit 44 compares the number counted by the second counting circuit with a predetermined value, and counts the number of times by a second counting circuit that counts the number of times that the address data continuously matches. It corresponds to a second determination circuit that determines whether the value is equal to or more than the predetermined value.

Further, when the third counter 42 determines that the number of times is equal to or more than the predetermined value by the second determination circuit, the address data counted by the first count circuit or reproduced from the block. Set the address data as the data read destination address,
When it is determined that the number of times is not equal to or greater than the predetermined value, the address data to be reproduced next to the address data based on the address data set as the data read destination address immediately before is set. This corresponds to a three count circuit.

Next, a description will be given of a synchronization process at the time of reproduction in the information reproducing apparatus according to the fifth embodiment. This synchronization processing is basically the same operation as the synchronization processing in the information reproducing apparatus of the second embodiment described above.

In this synchronization processing, one block is composed of a plurality of data and address data indicating the order of each data in the block. When reproducing data of an information recording medium on which a plurality of blocks are recorded, The address data reproduced from the block is set, the address is counted sequentially from the address data, and the counted address data is compared with the address data reproduced from the block to determine whether or not they match. to decide.

Based on the determination, starting from the time when the address data is set, the number of times that the address data reproduced from the block and the counted address data successively match is counted, and the counted number is counted. The number of times is compared with a predetermined value, and it is determined whether the number is equal to or greater than the predetermined value.

When it is determined that the number of times is equal to or more than the predetermined value, the counted address data or the address data reproduced from the block is set as a data read destination address. If it is determined that the address data is not equal to or larger than the predetermined value, the address data to be reproduced next to the address data is set based on the address data set as the data read destination address immediately before.

Further, the synchronization processing will be described.
The input address data and the first counter (first CN)
T) The count value output from 40 is compared by the first comparison circuit 43, and if they match, an OK pulse is output and input to the enable terminal of the second counter (second CNT) 41. Accordingly, when the input address data matches the count value of the first CNT 40, the first
The count value of the CNT 40 increases by one.

If they do not match, an NG pulse is output to load the first CNT 40 and the second CNT 41 (loa).
d) An NG pulse is input to the terminal, and the address data input to the first CNT 40 and “1” are set to the first CNT 40, respectively. Thus, the number of times when the input address data and the count value of the first CNT 40 continuously match is counted by the second CNT 41.

Further, the output of the second CNT 41 is compared with the designated value by the second comparing circuit. When the output of the second CNT 41 ≧ the designated value, a load signal is loaded to the load terminal of the third counter (third CNT) 42. And enter the first CNT 40
Is set in the third CNT 42.

Thus, the input address (= the count value of the first CNT 40) is set in the third CNT 42 when the input address is continuous more than the designated value, and even if the input address has an error, the address is correctly set. Can be corrected.

Thereafter, data processing is performed in block units according to the corrected address data. The specified value may be input to the second comparison circuit 44 by holding an external input value in a register. Further, even if the value input to the third CNT 42 is not used as the count value from the first CNT 40 but the input address data is input as it is,
When both match in the first comparison circuit 43, the third CNT 42
, The same operation is obtained.

Since the synchronization circuit of the fifth embodiment is realized as dedicated hardware, high-speed operation and miniaturization of the circuit are possible. Also, by making it possible to arbitrarily set a designated value that is the number of times the addresses in the block are consecutive from the outside, it is possible to synchronize data in consideration of the degree of defect of the information recording medium. Synchronous operation can be specified according to the status of occurrence of a media error.

[0127]

As described above, according to the information reproducing apparatus, the information reproducing method, the information reproducing synchronizing circuit and the information reproducing synchronizing method of the present invention, the time required for reproducing the data recorded on the information recording medium is short. Data can be synchronized in time.

[Brief description of the drawings]

FIG. 1 is a functional block diagram showing a schematic configuration of an optical disc reproducing device according to a first embodiment of the present invention.

FIG. 2 is an explanatory diagram showing an example of a data format recorded on an information recording medium used in the embodiment of the present invention.

FIG. 3 shows the MP of the information reproducing apparatus according to the first embodiment of the present invention;
9 is a flowchart illustrating a synchronization process in the synchronization circuit of U1.

FIG. 4 is a diagram provided for describing the processing shown in FIG. 3 based on specific numerical values.

FIG. 5 is a diagram showing an MP of an information reproducing apparatus according to a second embodiment of the present invention;
9 is a flowchart illustrating a synchronization process in the synchronization circuit of U1.

FIG. 6 is a diagram provided for describing the processing shown in FIG. 5 based on specific numerical values.

FIG. 7 is a functional block diagram showing a configuration of a synchronization circuit according to a third embodiment of the present invention.

FIG. 8 is a functional block diagram showing a configuration of a synchronization circuit according to a fourth embodiment of the present invention.

FIG. 9 is a functional block diagram showing a configuration of a synchronization circuit according to a fifth embodiment of the present invention.

[Explanation of symbols]

1: MPU 2: Memory 3: Data input unit 4: Data output unit 5: Reproducing device 6: Input device 7: Data bus 8: Information recording medium 10: Synchronous circuit 20a to 20o, 30a to 30o: 0 to 15 detection Circuits 21a to 21o, 31a to 31o: 0 to 15 address number counters 22a to 22o, 32: 0 to 15 comparison circuits 23: OR circuits 24, 34: Address counters 35a to 35o: 0 to 15 AND circuits 36: Selector 40: First CNT 41: Second CNT 42: Third CNT 43: First comparison circuit 44: Second comparison circuit

Claims (14)

[Claims] 1. One block is composed of a plurality of data and address data indicating the order of each data in the block.
An information reproducing apparatus comprising: means for reproducing data on an information recording medium on which a plurality of blocks are recorded; a plurality of address data detecting means for detecting each address data reproduced from within the block; A plurality of address data detection number counting means for counting the number of address data detections from the detection of the address data to the detection of the address data again for each address data detected by the means; Determining means for comparing the number of detected address data with a predetermined value to determine whether or not the address data match each other; and when determining that the address data matches, the address data detected by each of the address data detecting means. Is set as the data read destination address,
Address data setting means for correcting and setting the address data to be reproduced next to the address data based on the address data set immediately before as the data read destination address when it is determined that they do not match; An information reproducing apparatus characterized by the above-mentioned. 2. The information reproducing apparatus according to claim 1, wherein said judging means compares each address data detection number counted by said each address data detection number counting means with a predetermined value which is set in advance. An information reproducing apparatus comprising a plurality of judging means for judging whether or not the information is reproduced. 3. One block is composed of a plurality of data and address data indicating the order of each data in the block.
An information reproducing apparatus, comprising: means for reproducing data of an information recording medium on which a plurality of blocks are recorded, wherein address data reproduced from the blocks are set, and addresses are counted in order from the address data. Counting means; first determining means for comparing the address data counted by the means with the address data reproduced from within the block to determine whether or not the address data matches each other; A second counting means for counting the number of times that the address data reproduced from within the block and the address data counted by the first counting means continuously start from when the data is set, and The counted number is compared with a predetermined value set in advance, and the number is counted as the predetermined value. Second determining means for determining whether or not the address data is greater than or equal to the predetermined value. If the number is determined to be greater than or equal to the predetermined value, the address data counted by the first counting means, or the address data reproduced from the block. Address data is set as a data read destination address, and if it is determined that the number of times is not greater than or equal to the predetermined value, reproduction is performed next to the address data based on the address data set immediately before as the data read destination address. And a third counting means for correcting and setting the address data to be performed. 4. An information reproducing apparatus according to claim 3, further comprising means for externally inputting and holding said predetermined value set in said second counting means. 5. One block is composed of a plurality of data and address data indicating the order of each data in the block.
In an information reproducing method for reproducing data on an information recording medium in which a plurality of blocks are recorded, each address data reproduced from the block is detected, and the detected address data is detected for each detected address data. The number of detected address data from when it is detected until it is detected again is counted, and each counted number of detected address data is compared with a predetermined value to determine whether or not they match each other. When it is determined that each address matches, the detected address data is set as the address of the data read destination, and when it is determined that they do not match, based on the address data set immediately before as the address of the data read destination. Correcting and setting the address data to be reproduced next to the address data. Information reproduction method to be used. 6. One block is composed of a plurality of data and address data indicating the order of each data in the block,
In an information reproducing method for reproducing data of an information recording medium in which a plurality of blocks are recorded, address data reproduced from within the block is set, and addresses are counted in order from the address data. The data is compared with the address data reproduced from the block to determine whether they match, and based on the determination, the address data reproduced from the block starting from when the address data is set is determined. Count the number of times that the address data and the counted address data successively coincide with each other, determine whether the number of times is equal to or more than the predetermined value by comparing the counted number with a predetermined value, When the number is determined to be equal to or more than the predetermined value, the counted address data or the block The address data reproduced from within is set as a data read destination address, and when it is determined that the number of times is not more than the predetermined value, the address is set based on the address data set immediately before as the data read destination address. An information reproducing method, wherein address data to be reproduced next to data is corrected and set. 7. The information reproducing method according to claim 6, wherein the predetermined value is externally input and held. 8. One block includes a plurality of data and address data indicating the order of each data in the block.
An information reproduction synchronization circuit for synchronizing when reproducing data of an information recording medium in which the plurality of blocks are recorded, a plurality of address data detection circuits each detecting each address data reproduced from within the block; A plurality of address data detection number counting circuits for counting the number of address data detections from when the address data is detected until the address data is detected again for each address data detected by each circuit; A determination circuit for comparing each detected number of address data with a predetermined value set in advance to determine whether or not they match each other; and when it is determined that they match, each of the detected address data is detected by each of the address data detection circuits. Address data set as a data read destination address,
An address data setting circuit that corrects and sets address data to be reproduced next to the address data based on the address data set as the data read destination address immediately before when it is determined that they do not match; An information reproduction synchronization circuit characterized by the following. 9. The information reproduction synchronization circuit according to claim 8, wherein the determination circuit compares each address data detection number counted by each address data detection number counting circuit with a predetermined value set in advance. An information reproduction synchronization circuit, comprising a plurality of determination circuits for determining whether or not they match each other. 10. An information block in which one block is composed of a plurality of data and address data indicating an order of each data in the block, and which is synchronized when reproducing data of an information recording medium in which the plurality of blocks are recorded. In a reproduction synchronization circuit, a first count circuit that sets address data reproduced from within the block and counts addresses sequentially from the address data; and an address data counted by the circuit and the address data reproduced from within the block. A first determination circuit that compares the address data with the address data that has been reproduced from the block, starting from when the address data is set, based on the determination by the circuit. Counts the number of times that the address data counted by the first count circuit matches continuously. A second counting circuit that compares the number counted by the circuit with a predetermined value to determine whether or not the number is equal to or greater than the predetermined value; Is determined to be equal to or greater than the predetermined value, the address data counted by the first count circuit or the address data reproduced from the block is set as a data read destination address, and the number of times is set to the predetermined value. A third counting circuit for correcting and setting the address data to be reproduced next to the address data based on the address data set immediately before as the address from which the data is read out, Synchronous circuit for information reproduction. 11. The information reproduction synchronization circuit according to claim 10, further comprising a circuit for externally inputting and holding the predetermined value set in the second count circuit. . 12. One block is composed of a plurality of data and address data indicating the order of each of the data in a block, and is synchronized when reproducing data of an information recording medium in which the plurality of blocks are recorded. In the reproduction synchronization method, each of the address data reproduced from the block is detected, and the number of detected address data from the detection of the address data to the detection of the address data for each of the detected address data is determined. It counts and compares each counted address data detection number with a predetermined value set in advance to judge whether or not they match, and when it is judged by each judgment that there is a match, each detected address is detected. Set the data as the data read destination address, and if it is determined that they do not match, immediately before the data read destination address Synchronous circuit information reproduction and sets to correct the address data to be reproduced next the address data on the basis of the address data set as. 13. One block is composed of a plurality of data and address data indicating the order of each of the data in a block, and the information is synchronized when reproducing the data of the information recording medium in which the plurality of blocks are recorded. In the reproduction synchronization method, address data reproduced from the block is set, addresses are sequentially counted from the address data, and the counted address data is compared with the address data reproduced from the block. The number of times that the address data reproduced from within the block and the counted address data continuously match, starting from the time when the address data is set, based on the determination. Is counted, and the counted number is compared with a predetermined value set in advance. If the number is determined to be greater than or equal to the predetermined value, the counted address data or the address data reproduced from within the block is set as a data read destination address, and the number of times is determined. When it is determined that it is not more than the predetermined value,
A method of synchronizing information reproduction, comprising correcting address data to be reproduced next to the address data based on address data set as a data read destination address immediately before, and setting the corrected address data. 14. The method for synchronizing information reproduction according to claim 13, wherein the predetermined value is externally input and held.