JP3719680B2 - Synchronization generation method and synchronization generation circuit - Google Patents

Description

  The present invention relates to a disk reproducing method and a disk reproducing apparatus for a disk including a defect.

  A conventional disk reproducing apparatus, in reproducing a disk including defects such as scratches and fingerprints, is based on a defect detection result due to a fluctuation in the level of a disk reproduction signal, as shown in "Digital Disc Player" described in JP-A-61-34735. , Tracking servo, focus servo holding method, and “disc drive device” described in Japanese Patent Laid-Open No. 4-268267, when the disc is defective, the pickup is moved to a position where there is no flaw and tracking is performed. Defect adaptive control in tracking servo and focus servo, such as servo and focus servo adjustment methods, is performed to improve the reproduction performance of a disc including defects.

Further, as shown in “Optical Disc Device” described in Japanese Patent Application Laid-Open No. 08-287623, when a disc is defective, the reproduction clock is held at an optimum frequency in binarization of the disc reproduction signal and clock reproduction. By performing appropriate defect adaptive control, the reproduction capability of a disk including a defect is improved.
JP 61-34735 A JP-A-4-268267 JP-A-8-287623

  However, when playing back a defective disk, if the defect adaptive control in tracking servo and focus servo, or the binarization of the RF signal reproduced from the disk and the defect adaptive control of clock reproduction are performed, the frame reproduced from the disk Since the synchronization of the channel clock is lost, there is a problem that even if demodulated modulation data is input to the demodulation means, the modulation data cannot be demodulated until an accurate synchronization pattern is detected. It was.

  Therefore, even if defect adaptive control in tracking servo and focus servo, or binarization of RF signal reproduced from disk and defect adaptive control of channel clock reproduction, the effect is limited by the demodulation capability of the data demodulation means Had the problem of being.

  The present invention has been made in view of the above problems, and even when a frame reproduced from a disc and a channel clock are out of synchronization, a demodulated signal input until a normal synchronization pattern is detected. It is an object of the present invention to provide a disc reproducing apparatus that can demodulate possible modulation data and can minimize the area that cannot be demodulated.

In order to solve the above problems, the disc reproducing method according to claim 1 of the present invention, in the synchronization generation method to detect and interpolating sync pattern of the frame read from the disk, and generates a synchronization signal and the synchronization pattern It is generated by the synchronization detection / interpolation step that generates the capacitive component synchronization signal by performing synchronization detection and synchronization interpolation using the synchronization detection window indicating the position where it should be and the channel clock read from the disk. A channel clock counting step for counting the number of channel clocks read from the disk based on the synchronization, a synchronization detection window generating step for generating the synchronization detection window with reference to the count value counted by the channel clock count step, and always A system with a constant frequency Based on the system clock count step that counts the number of system clocks with the lock input and the capacitance component synchronization signal output from the synchronization detection / interpolation step, normal synchronization is performed from the count value counted by the system clock count step. A synchronization interval measurement step for measuring an interval, and a pseudo synchronization generation step for generating a time component synchronization signal based on a normal synchronization interval measured by the synchronization interval measurement step when the input modulation data is defective. When the input modulation data is not defective, the capacitance component synchronization signal generated using the channel clock is output as a synchronization signal. When the input modulation data is defective, the system clock is output. Outputs the time component synchronization signal generated by using as a synchronization signal A synchronization signal generating step that, when there is no defect in the input modulated data, by using the channel clock that is read from the disk, perform the step of generating a synchronization signal by detecting and interpolating the sync pattern , when there is a defect in the input modulation data, always using the system clock frequency is constant, the interpolation generates a synchronization signal based on the time component synchronizing signal generated in the absence of defects in the modulation data The step to perform is performed .

A synchronization generation method according to claim 2 of the present invention is characterized in that in the synchronization generation method according to claim 1, the frequency of the system clock can be arbitrarily changed.

According to a third aspect of the present invention, there is provided a synchronization generation circuit that detects and interpolates a synchronization pattern of a frame read from a disk, and indicates a position where a synchronization pattern should be present in a synchronization generation circuit that generates a synchronization signal. Synchronization detection and interpolation means for performing synchronization detection and synchronization interpolation using a synchronization detection window and a channel clock read from the disk, and a disk based on the synchronization generated by the synchronization detection and interpolation means A channel clock counter for counting the number of channel clocks read out from the channel, synchronization detection window generating means for generating the synchronization detection window with reference to the count value counted by the channel clock counter, and a system clock whose frequency is always constant System that counts the number of system clocks A clock counter, a synchronization interval measuring means for measuring a normal synchronization interval from a count value counted by the system clock counter based on the capacitance component synchronization signal output from the synchronization detection / interpolation means, and an input modulation When there is a defect in the data, the pseudo-synchronization generation unit that generates the time component synchronization signal based on the normal synchronization interval measured by the synchronization interval measurement unit, and when the input modulation data has no defect The capacitance component synchronization signal generated using the channel clock is output as a synchronization signal, and if the input modulation data is defective, the time component synchronization signal generated using the system clock is output as the synchronization signal. and a synchronizing signal generating means for outputting as, if not defective input modulated data, read from the disk Using the channel clock, it generates a sync signal to detect and interpolating synchronization pattern, when there is a defect in the input modulated data is always frequency using the system clock is constant, modulated data The synchronization signal is generated by interpolation based on the time component synchronization signal generated when there is no defect .

According to a fourth aspect of the present invention, in the synchronous generation circuit according to the third aspect, the frequency of the system clock can be arbitrarily changed.

  According to the disc playback method and the disc playback apparatus of the present invention, the modulation data read from the disc is stored in the temporary storage memory, and the modulation stored in the temporary storage memory based on the correctly detected synchronization pattern By demodulating data, due to physical defects such as scratches and fingerprints contained on the disk, the modulation data and the channel clock are out of synchronization, and the demodulated modulation data is an area that cannot be demodulated (physical Even if there is a region from a defective defect to a detectable synchronization pattern), the demodurable region can be demodulated, and the undemodulable region can be minimized.

  In addition, by controlling so as to minimize the area that cannot be demodulated in this way, flaw adaptive control in tracking servo and focus servo, binarization of the RF signal reproduced from the disk, and flaw adaptive control in channel clock reproduction Even if it is performed, the effect of improving the reproduction ability of the wound adaptive control can be sufficiently obtained.

(Embodiment 1)
Hereinafter, a disc reproducing method and a disc reproducing apparatus according to the present invention will be described with reference to FIGS.
FIG. 1 is a block diagram showing an example of the configuration of a disc playback apparatus according to Embodiment 1 of the present invention.

  In FIG. 1, reference numeral 101 denotes a synchronization generation circuit that generates a synchronization signal 113, which is a reference signal, in order to demodulate modulation data 111 composed of a modulation data string (hereinafter referred to as a frame) starting with a synchronization pattern. When a normal synchronization pattern included in the modulation data 111 can be detected, by detecting the synchronization pattern, a normal synchronization signal is generated and output, and the normal synchronization pattern cannot be generated Generates and outputs a synchronizing signal for interpolating a normal synchronizing signal. In addition, when the synchronization generation circuit 101 outputs a synchronization signal that interpolates a normal synchronization signal and then outputs a normal synchronization signal, the synchronization generation circuit 101 re-demodulates the modulation data until the normal synchronization signal is detected. The operation instruction signal 123 is output to the reading position search circuit 107.

  Reference numeral 102 denotes a defect detection circuit that monitors the input modulation data 111 to detect a physical defect included on the disk and outputs it to the defect detection signal 114. 103 indicates that the data cannot be accurately demodulated from the defect detection signal 114 output from the defect detection circuit 102 and the defect information 112 detected by external means such as tracking servo or focus servo. 2 is a defect signal generation circuit that generates the defect signal 115 shown.

  A memory access control circuit 104 outputs a memory access control signal 116 for storing input modulation data 111 in the temporary storage memory 105. Note that the memory access control signal 116 includes, for example, modulation data to be stored and a storage address. A temporary storage memory 105 stores modulation data output from the memory access control circuit.

  106, when the synchronization signal 113 and the defect signal 115 are input and the defect signal 115 indicates that the modulation data 111 in the frame includes a defect, the frame is regarded as a defective frame, and the frame has no defect. Until the number of detected defective frames is counted up, and the number of detected defective frames is counted, and the number of defective frames is stored.

  107 operates upon receiving the operation instruction signal 123 from the synchronization generation circuit 101, and is based on the memory access control signal 116 output from the memory access control circuit 104 and the defective frame number 118 output from the defective frame number storage circuit 106. Thus, the readout position retrieval circuit retrieves the readout position of the modulation data stored in the temporary storage memory 105 and outputs the readout position instruction signal 119 to the readout determination circuit 108. 108 generates a memory read control signal 117 according to the read position instruction signal 119, thereby reading data from the read position indicated by the read position instruction signal 117 from the temporary storage memory 105, and demodulating the data as the memory storage data 120. 109 is a readout circuit that outputs to 109.

  Reference numeral 109 denotes a demodulation circuit that demodulates the input modulation data 111 and, when the memory storage data 120 is output from the read circuit 108, demodulates the memory storage data 120, and outputs the demodulation data. Outputs demodulated demodulated data 121 and a data selection instruction signal 122 indicating which demodulated data 121 is demodulated from modulated data 111 or memory storage data 120.

  A demodulated data control circuit 110 includes a buffer memory and controls data stored in the buffer memory based on the demodulated data 121 demodulated by the demodulating circuit 109 and the data selection instruction signal 122.

Next, the operation of the disc playback apparatus according to Embodiment 1 of the present invention will be described.
The synchronization generation circuit 101 detects a synchronization pattern included in the modulation data 111 in order to generate a synchronization signal 113 that is a reference signal for demodulating the modulation data 111 divided into units called frames. Generate and output a synchronization signal. Further, when the normal synchronization pattern cannot be generated, the synchronization generation circuit 101 generates and outputs a synchronization signal for interpolating a normal synchronization signal. That is, when the synchronization pattern included in the modulation data 111 is broken, the synchronization signal 113 is interpolated at a position where the synchronization pattern should be included, and when detected at a position where the synchronization pattern should not be included, Generation of the synchronization signal 113 for the synchronization pattern is suppressed.

  The synchronization signal 113 generated by the synchronization generation circuit 101 in this way is output to the defect detection circuit 102, the defective frame number storage circuit 106, the read position search circuit 107, and the demodulation circuit 109. In addition, when the synchronization generation circuit 101 outputs a synchronization signal that interpolates a normal synchronization signal and then outputs a normal synchronization signal, the synchronization generation circuit 101 re-demodulates the modulation data until the normal synchronization signal is detected. The operation instruction signal 123 is output to the reading position search circuit 107.

  The defect detection circuit 102 that has received the synchronization signal 113 detects the defect included in the modulation data 111 by monitoring the input state of the modulation data 111 and generates a defect detection signal 114. Then, the generated defect detection signal 114 is output to the defect signal generation circuit 103.

  Hereinafter, an example of a method for detecting a defect included in the modulation data 111 by the defect detection circuit 102 will be described. In the first embodiment of the present invention, the following two methods will be described as methods for detecting defects included in the modulation data 111 by the defect detection circuit 102.

  First, the defect detection method included in the first modulation data 111 is a method of calculating a DSV (Digital Sum Variation) of the modulation data 111 for each frame, and the DSV calculation result for each frame recognizes a defect. A defect is recognized by exceeding the provided defect threshold (the defect threshold can be set by an external control means such as a microcomputer). FIG. 3 illustrates this process. The DSV is cleared by the synchronization signal, and the calculation of the DSV is started. When the DSV calculation result exceeds the defect threshold, a defect detection signal is generated.

  Note that the synchronization signal, modulation data, and defect detection signal in FIG. 3 are equivalent to the synchronization signal 113, modulation data 111, and defect detection signal 114 in FIG. 1, respectively.

  Next, the defect detection method included in the second modulation data 111 is a method of counting the number of data that cannot be demodulated in the modulation data 111 for each frame, and the number of modulation data that cannot be demodulated for each frame recognizes the defect. Therefore, the defect is recognized as a defect by exceeding a defect threshold (the defect threshold can be set by an external control means such as a microcomputer). FIG. 4 illustrates this process. The number of data that cannot be demodulated is cleared by the synchronization signal, and the count of the number of data that cannot be demodulated is started. When the number of data that cannot be demodulated exceeds the defect threshold, a defect detection signal is generated.

  Note that the synchronization signal, modulation data, and defect detection signal in FIG. 4 are equivalent to the synchronization signal 113, modulation data 111, and defect detection signal 114 in FIG. 1, respectively.

  Next, the defect signal generation circuit 103 is designated by external control means such as a microcomputer from the defect information 112 detected by the external means such as tracking servo and focus servo and the defect detection signal 114 output from the defect detection circuit 102. In accordance with the determined conditions, a defect signal 115 indicating that the data cannot be demodulated accurately is generated. The generated defect signal 115 is output to the synchronization generation circuit 101 and the defective frame number storage circuit 106.

  The memory access control circuit 104 performs control for storing the modulation data 111 in the temporary storage memory 105, that is, converts the input modulation data 111 into a data format that can be stored in the temporary storage memory 105, and temporarily stores the converted data Generates an address for storage in memory. The converted data and storage address generated here are output to the temporary storage memory 105 as the memory access control signal 116.

  The temporary storage memory 105 that has received the memory access control signal 116 stores the conversion data included in the memory access control signal 116 in the area indicated by the storage address.

  Next, the defective frame number storage circuit 106 receives the synchronization signal 113 and the defect signal 115 as inputs, and monitors the defect signal 115 for each frame indicated by the synchronization signal 113. That is, when the defect signal 115 indicates that the modulation data 111 in the frame includes a defect, the frame is counted as a defective frame. The count value counts up the number of defective frames until a frame having no defect is detected, and stores the count value.

  On the other hand, when the defect signal 115 indicates that the modulation data 111 in the frame does not include a defect, it is determined that the frame does not have a defect, and the count value of the defective frame is reset. The number of defective frames stored here is output to the readout position search circuit 107 as the number 118 of defective frames.

  The read position search circuit 107 operates when receiving the operation instruction signal 123 from the synchronization generation circuit 101, and receives the synchronization signal 113, the memory access control signal 116, and the defective frame number 118 as an input, and the frame before the normal synchronization signal. In order to demodulate the data, the data reading position of the modulation data 111 stored in the temporary storage memory 105 is determined.

  Specifically, the read position search circuit 107 holds the storage address of data included in the memory access control signal 116 and the number of read frames that can be arbitrarily set in advance. When the operation instruction signal 123 is received from the synchronization generation circuit 101, the readout position search circuit 107 holds the readout position search circuit 107 rather than the frame indicated by the normal synchronization signal 113 output from the synchronization generation circuit 101. In order to read out the frame before the number of frames from the temporary storage memory 105, the frame head position before the number of frames held by the reading position search circuit 107 is specified, and the read instruction signal 119 is sent based on the storage address of the stored data. Generate.

  At this time, when the number of frames to be read out is larger than the number of defective frames output from the defective frame number storage circuit 106, the readout position search circuit 107 performs the preset readout. Instead of the number of frames to be performed, data of the number of defective frames output from the defective frame number storage circuit 106 is read out.

  By doing so, the number of frames read from the temporary storage memory 105 and decoded can be reduced, the processing speed can be improved, and the power consumption can be reduced.

  Next, the read determination circuit 108 that has received the read instruction signal 119 generates a memory read control signal 117 based on the frame read instruction signal 119 and reads the frame data stored in the temporary storage memory 105. The read frame data is output to the demodulation circuit 109 as memory storage data 120.

  The demodulation circuit 109 demodulates the input modulation data 111 and, when the memory storage data 120 is input from the read determination circuit 108, demodulates the memory storage data 120. Further, when the demodulation circuit 109 outputs the demodulated data 121 which is demodulated data, each of the modulation data 121 to be output is obtained by demodulating the modulation data 111 or the memory storage data 120 is demodulated. The data selection instruction signal 122 indicating whether or not the data has been added is output.

  Further, the demodulation circuit 109 performs the demodulation of the modulation data 111 and the demodulation of the memory storage data 120 simultaneously in parallel when the memory storage data 120 is input from the read determination circuit 108 to improve the processing speed. And

  The demodulated data control means 110 sequentially stores the demodulated data 121 for the inputted modulation data 111 in the buffer memory of the data reproduction control means 110 and data indicating that the memory storage data 120 has been demodulated from the demodulation circuit 109. When the demodulated data 121 with the selection instruction signal 122 is output, the demodulated data is replaced with demodulated data stored in the buffer memory and demodulated from the modulated data 111 at the corresponding data position.

  Next, the operation of the disk reproducing apparatus according to the first embodiment of the present invention will be specifically described with reference to FIGS.

  FIG. 5 is an explanatory diagram for specifically explaining the operation of the disk reproducing apparatus. In FIG. 5, the synchronization signal indicates the synchronization signal 113 generated by the synchronization generation circuit 101, and the modulation data indicates the disk. Modulated data 111, demodulated data (real-time data) input to the playback device indicate demodulated data 121 obtained by demodulating modulated data 111, and demodulated data (temporary storage data) indicates demodulated data 121 obtained by demodulating memory stored data 120. The temporary storage memory is equivalent to the temporary storage memory 105 in FIG. 1, and the buffer memory is a buffer memory included in the demodulated data reproduction control means 110 and stores data to be reproduced.

  When modulation data n, n + 1,... Shown in FIG. 5 is input to the disk reproducing device, the input modulation data is demodulated (real-time data) by the demodulation circuit 109. The memory access control circuit stores the input modulation data in the temporary storage memory. The demodulated data demodulated by the demodulating circuit 109 is output as demodulated data (real time data) n ′, n + 1 ′,... To the demodulated data control circuit 110 and stored in the buffer memory 301 included in the demodulated data control circuit 110. The

  Here, if this demodulated data (real-time data) has the defective area shown in FIG. 5, there is a possibility that an abnormality has occurred in the channel clock in the defective portion of the modulated data, resulting in a synchronization shift. The demodulated data (n ′ to n + 3 ′) until the normal synchronization signal included in the modulation data is detected may have an error.

  For this reason, when there is a defect in the modulation data input to the disk reproducing device, a normal synchronization pattern is detected by the synchronization generation circuit 101, whereby the read position search circuit 107 operates and is stored in the temporary storage memory 105. Instruct to read out the defective modulation data.

  That is, in FIG. 5, when the reading position search circuit 107 has been set in advance to read data for one frame from the temporary storage memory 105, the reading position search circuit 107 reads the normal synchronization signal (n + 4). Is input to the reading circuit 108 to read data (n + 3) for one frame before the position where the normal synchronization signal is input.

  At this time, the number of defective frames 118 output from the defective frame number storage circuit 106 is the number of defective frames up to the time when a normal synchronization signal (synchronization pulse located at the head of n + 4) is generated. , 4 (four from n to n + 3) are output as the number 118 of defective frames. Accordingly, since the number of defective frames is larger than the number of frames to be read out, the reading position search circuit 107 outputs an instruction to read data for one predetermined frame.

  The data (n + 3) is read from the temporary storage memory 105 and demodulated by the demodulating means 109.

  The demodulated data is demodulated (temporary storage data) n + 3 ″, and the demodulated data control circuit 110 overwrites the demodulated data (real-time data) n + 3 ′ stored in the buffer memory.

  Since this demodulated data can accurately grasp the sync pattern storage position of the data stored in the temporary storage memory based on the normal sync pattern included in the modulated data, it can be demodulated among the input modulated data 111 Data is demodulated faithfully.

  In this way, by replacing demodulated data (real-time data) that may be erroneous with demodulated data (temporary storage data) that is faithful to the input modulated data, it is possible to input data in disc playback that includes physical defects. It is possible to minimize the non-demodulable area of the modulated data to be generated.

  Although the number of frames of modulation data that can be stored in the temporary storage memory 105 is not particularly described, only a fixed number of frames can be stored in the temporary storage memory 105 due to the memory capacity of the temporary storage memory 105. In this case, the number of frames to be read instructed by the reading position search circuit 119 may be controlled to be equal to or less than the number of frames stored in the temporary storage memory 105. In this case as well, the same effect of the present invention is achieved. Can be obtained.

  Further, the memory access control circuit 104 may be configured such that the defect signal 115 is input from the defect signal generation circuit 103, and the memory access control circuit 104 may store only modulation data having a defect in the temporary storage memory 105. In this case, the storage area of the temporary storage memory can be used effectively.

  The read position search circuit 107 has been described as generating the read instruction signal 119 so as to read data for each frame stored in the temporary storage memory 105. The read instruction signal 119 may be generated so as to read data from an arbitrary position.

  Further, the demodulation process of the disk reproducing apparatus described in the first embodiment of the present invention and the demodulation mode for demodulating only the modulation data 111 read from the disk may be switched to perform the demodulation process. In this case, the demodulation method can be switched according to a request for high speed and certainty of data reproduction.

(Embodiment 2)
The disc reproducing apparatus according to the second embodiment of the present invention will be described below. Note that the disk reproducing apparatus according to the second embodiment of the present invention is an improvement of the synchronization generation circuit 101 of the disk reproducing apparatus according to the first embodiment, and even when the modulation data 111 has a defect, An accurate synchronization signal is generated to improve the demodulation capability of the disk reproducing apparatus.

  Hereinafter, the synchronization generation circuit of the disc playback apparatus according to the second embodiment of the present invention will be described in more detail with reference to FIG.

FIG. 2 is a diagram showing an example of the configuration of the sync generation circuit 101 of the disc playback apparatus according to the second embodiment of the present invention. The modulation data 212, the sync signal 221 and the defect signal 211 shown in FIG. 1 is equivalent to the modulation data 111, the synchronization signal 113, and the defect signal 115, the channel clock 213 indicates a clock extracted from the frame read from the disk, and the system clock 214 manages the entire disk reproducing apparatus. A clock with a constant frequency is shown. The components other than the sync generation circuit 101 of the disc player according to the second embodiment of the present invention are the same as those of the disc player shown in FIG. 1 (not shown), and in FIG. The clock 213 and the system clock 214 are not shown because the drawing is complicated, but these clock signals are input to each component as timing signals for controlling the operation of the disk reproducing apparatus.

  In FIG. 2, reference numeral 201 denotes a capacitance component that detects a synchronization pattern using a synchronization detection window 216 indicating a range in which the synchronization pattern is detected, or complements the synchronization pattern using a channel clock 213 synchronized with modulation data 212. It is a synchronization detection / interpolation circuit that generates a synchronization signal 215.

  A channel clock counter 202 counts the channel clock 213 based on the capacitance component synchronization signal 215 and outputs a channel clock count value 217. Reference numeral 203 denotes a system clock counter that counts the system clock 214 having a constant frequency based on the capacitance component synchronization signal 215 and outputs a system clock count value 218.

  Reference numeral 204 denotes a synchronization interval measurement circuit that converts the interval of the capacitive component synchronization signal 215 into a system clock count value 218 and outputs a synchronization time interval signal 219. Reference numeral 205 denotes a synchronization detection window generation circuit that outputs a synchronization detection window 216 indicating a range in which a synchronization pattern is detected from the modulation data 212. Reference numeral 206 denotes a pseudo-synchronization generation circuit that generates a synchronization signal in the defect area and generates a time component synchronization signal 220 using the synchronization time interval signal 219. A synchronization signal generation circuit 207 outputs a synchronization signal 221 based on the capacitance component synchronization signal 215 output from the synchronization detection / interpolation circuit 201 and the time component synchronization signal 220 output from the pseudo synchronization generation circuit 206. .

Next, the operation of the synchronization generation circuit 101 configured as described above will be described below.
The synchronization detection / interpolation circuit 201 generates a capacitance component synchronization signal 215 when the input defect signal 211 does not indicate that the modulation data 212 is defective, and is indicated by the input synchronization detection window 216. When the synchronization pattern included in the modulation data 212 can be detected within the area, the synchronization pattern is detected and output as the capacitance component synchronization signal 215, and the synchronization pattern is detected within the area indicated by the synchronization detection window 216. Is not detected, the synchronization is interpolated to generate the capacitive component synchronization signal 215.

  On the other hand, if the input defect signal 211 indicates that the modulation data 212 is defective, the synchronization detection / interpolation circuit 201 stops the synchronization detection / interpolation process and does not generate the capacitance component synchronization signal 215.

The capacitance component synchronization signal 215 generated in this way is output to the channel clock counter 202, the system clock counter 203, the synchronization interval measurement circuit 204, the pseudo synchronization generation circuit 206, and the synchronization signal generation circuit 207.

  The channel clock counter 202 that has received the capacitance component synchronization signal 215 counts the channel clock at each synchronization interval of the capacitance component synchronization signal 215 and outputs the count result as the channel clock count value 217. The channel clock count value 217 indicates the data capacity input from the modulation data 212 with reference to the capacitive component synchronization signal 215.

  The channel clock count value 217 counted by the channel clock counter 202 is output to the synchronization detection window generation circuit 205.

  The synchronization window generation circuit 205 that has received the channel clock count value 217 monitors the position of the synchronization pattern included in the modulation data 212 by comparing the data capacity of the frame with the channel clock count value 217, and the synchronization detection window 216. Is generated. The synchronization detection window 216 rises from the position of the synchronization pattern included in the modulation data 212 before the number of channel clocks (this channel clock number can be set by an external control means such as a microcomputer), and detects the synchronization pattern. The synchronization detection window length (this synchronization detection window length can be set by an external control means such as a microcomputer) is output to the synchronization detection / interpolation circuit 201.

On the other hand, the system clock counter 203 that has received the capacitance component synchronization signal 215 counts the system clock, and outputs the count result as the system clock count value 218 each time the capacitance component synchronization signal 215 is input. The counter value 203 is reset. Note that the system clock count value 218 indicates the time input from the modulation data 212 on the basis of the capacitive component synchronization signal 215 since the system clock has a constant frequency.

The system clock count value 218 is output to the synchronization interval measurement circuit 204 and the pseudo synchronization generation circuit 206 .

The synchronization interval measurement circuit 204 that has received the capacitance component synchronization signal 215 and the system clock count value 218 outputs the capacitance component synchronization signal 215 generated when there is no defect in the modulation data 212 output from the synchronization detection / complementation circuit 201. By monitoring the system clock count value 218 every time, the synchronization interval, that is, the time of one frame can be measured, and a synchronization time interval signal 219 that is the measured synchronization interval is output to the pseudo synchronization generation circuit 206 .

The pseudo-synchronization generation circuit 206 that has received the system clock count value 218 and the synchronization time interval signal 219, when the modulation data 212 includes a defect, that is, when the capacitance detection signal 215 is not generated in the synchronization detection / interpolation circuit 201 The time component synchronization signal 220 is generated and the synchronization signal is generated by interpolating and generating the synchronization signal that is not generated by the capacity component synchronization signal 215 based on the system clock count value 218 and the synchronization time interval signal 219. Output to the circuit 207.

Further, the pseudo synchronization generation circuit 206 resets the counter value of the channel clock counter 202 when the time component synchronization signal 220 is output to the synchronization signal generation circuit 207. This is because there may be an abnormality in the frequency of the channel clock input to the channel clock counter 202 due to a defect area such as a scratch or a fingerprint on the disk.

The synchronization signal generation circuit 207 that has received the capacitance component synchronization signal 215 and the time component synchronization signal 220 outputs the capacitance component synchronization signal 215 as the synchronization signal 221 when the defective area 211 indicates that the modulation data 212 is not defective. If the defect area 211 indicates that the modulation data 212 is defective, the time component synchronization signal 220 is output as the synchronization signal 221.

  The synchronization signal 221 generated by the synchronization signal generation circuit 207 of the synchronization generation circuit in this way is output to the defect detection circuit 102, the defective frame number storage circuit 106, the read position search circuit 107, and the demodulation circuit 109 in FIG. The In addition, the synchronization signal generation circuit 207 of the synchronization generation circuit detects a normal synchronization signal after outputting a synchronization signal for interpolating a normal synchronization signal, and when it is output, until the normal synchronization signal is detected In order to demodulate the modulation data, an operation instruction signal 123 is output to the reading position search circuit 107.

  Here, the normal synchronization signal is a case where the defective area 211 indicates that the modulation data 212 is not defective, and is based on a synchronization pattern detected in the area indicated by the synchronization detection window 216. The synchronization signal that is generated in this manner, and the synchronization signal that interpolates the normal synchronization signal refers to all the synchronization signals other than the normal synchronization signal.

  As described above, in the second embodiment of the present invention, when the modulation data 212 is not defective, a synchronization signal is generated using a channel clock that is generally performed, and the modulation data 212 is defective. Do not use a channel clock that may cause anomalies in frequency due to the effects of defects such as scratches and fingerprints on the disk, and synchronize using a system clock that is not affected by defects and has a constant frequency. By generating a signal, it is possible to provide a synchronization generation circuit that can accurately generate a synchronization signal even when the modulation data 212 is defective.

  Further, since the count point in the system clock counter 203 is increased by increasing the frequency of the system clock input to the system clock counter 203, the time component synchronization signal 220 generated in the pseudo synchronization generation circuit 206 is more accurately represented. Can be generated.

(Embodiment 3)
Hereinafter, a disk reproducing method and a disk reproducing apparatus according to Embodiment 3 of the present invention will be described with reference to FIG. 6 and FIG.

  The disc reproducing apparatus according to the third embodiment of the present invention stores all the input modulation data 611 in the temporary storage memory, and always reads data from the temporary storage memory a plurality of frames before the frame where the synchronization signal is generated. The point of demodulation is different from the first embodiment in which data before the frame from which the synchronization signal is generated is read and demodulated only when a defective frame exists.

  In FIG. 6, reference numeral 601 denotes a synchronization generation circuit that generates a synchronization signal 601 that is a reference signal in order to demodulate modulation data 611 including a modulation data string (hereinafter referred to as a frame) starting with a synchronization pattern.

  Reference numeral 602 denotes a memory access control circuit that outputs a memory access control signal 613 for storing input modulation data 601 in the temporary storage memory 603. Note that the memory access control signal 613 includes, for example, modulation data to be stored and a storage address. A temporary storage memory 603 stores modulation data output from the memory access control circuit.

  Reference numeral 604 denotes a frame arbitrarily set in advance from the frame indicated by the synchronization signal based on the synchronization signal 612 output from the synchronization generation circuit 601 and the memory access control signal 613 output from the memory access control circuit 602. This is a read circuit that generates a memory read control signal 614 to read the previous data, and outputs the read data to the demodulation circuit 605 as memory storage data 615.

  Reference numeral 605 denotes a demodulation circuit that demodulates the memory storage data 615 output from the read circuit 604 and outputs demodulated data 616.

  Next, the operation of the disk reproducing apparatus according to Embodiment 1 of the present invention will be described with reference to FIGS.

  FIG. 7 is an explanatory diagram for specifically explaining the operation of the disk reproducing apparatus. In FIG. 7, the synchronization signal indicates the synchronization signal 612 generated by the synchronization generation circuit 611, and the modulation data indicates the disk. Modulated data 611 and demodulated data (temporary storage data) input to the playback device indicate demodulated data 616 obtained by demodulating the memory storage data 615, respectively. The temporary storage memory is equivalent to the temporary storage memory 603 in FIG.

  When modulation data n, n + 1,... Are input as modulation data 611 to the disc reproducing apparatus, the input modulation data 611 is stored in the temporary storage memory 603 by the memory access control circuit 602. .

  Next, the read circuit 604 reads out data from the temporary storage memory 603 from a frame number that is arbitrarily set in advance from the frame indicated by the synchronization signal 612 output from the synchronization generation circuit 601. Based on the memory access control signal 613 output from, the storage address of the frame to be read is specified, and the data of the frame is read.

  For example, when the readout circuit 604 is always set to read out data one frame before the frame indicated by the synchronization signal 612, for example, the synchronization signal indicating the beginning of the modulation data n + 4 to the readout circuit 604. Is input, the memory read control signal 614 is generated so as to read from the temporary storage memory 105 the data of n + 3 that is one frame before the modulation data n + 4, and the data is read from the temporary storage memory 603. Do.

  Next, when the read circuit 604 reads data of a frame that is arbitrarily set in advance from the temporary storage memory 105 before the frame indicated by the synchronization signal 612, the read circuit 604 outputs the data to the demodulation circuit 605 as memory storage data 615. To do.

  The memory storage data 615 output to the demodulation circuit 605 is demodulated by the demodulation circuit 605 and output as demodulated data (temporary storage data) n−1 ′, n ′, n + 1 ′,... Shown in FIG.

  The demodulated data 616 output from the demodulation circuit 605 is stored in the buffer memory as shown in FIG.

  As described above, in the disk reproducing apparatus according to the third embodiment of the present invention, the modulation data 611 read from the disk is stored in the temporary storage memory 603, and at the time of data demodulation, from the frame indicated by the generated synchronization signal 612. However, it is possible to demodulate the modulation data stored in the temporary storage memory with reference to the correctly detected synchronization signal by always reading and demodulating the data of the frame before the predetermined frame. The impossible area can be minimized.

  Although the number of frames of modulation data that can be stored in the temporary storage memory 105 is not particularly described, only a fixed number of frames can be stored in the temporary storage memory 105 due to the memory capacity of the temporary storage memory 105. In this case, the number of frames read by the reading circuit 604 may be controlled to be equal to or less than the number of frames stored in the temporary storage memory 603. In this case, the same effect as the present invention can be obtained. it can.

  The read circuit 604 has been described as generating the memory read control signal 614 so as to read data for each frame stored in the temporary storage memory 603. However, the read circuit 604 is, for example, an arbitrary in a frame. The memory read control signal 614 may be generated so as to read data from the position.

It is a block diagram which shows an example of a structure of the disc reproducing | regenerating apparatus in Embodiment 1 of this invention. It is a block diagram which shows an example of a structure of the synchronous production | generation circuit of the disc reproducing | regenerating apparatus by Embodiment 2 of this invention. It is explanatory drawing for demonstrating an example of the defect detection method of the defect detection circuit by Embodiment 1 of this invention. It is explanatory drawing for demonstrating an example of the defect detection method of the defect detection circuit by Embodiment 1 of this invention. It is explanatory drawing for demonstrating the specific operation | movement of the disc reproducing | regenerating apparatus by Embodiment 1 of this invention. It is a block diagram which shows an example of a structure of the disc reproducing | regenerating apparatus in Embodiment 3 of this invention. It is explanatory drawing for demonstrating the specific operation | movement of the disc reproducing | regenerating apparatus by Embodiment 3 of this invention.

Explanation of symbols

101, 601 Sync generation circuit 102 Defect detection circuit 103 Defect signal generation circuit 104, 602 Memory access control circuit 105, 603 Temporary storage memory 106 Defective frame number storage circuit 107 Read position search circuit 108, 604 Read determination circuit 109, 605 Demodulation circuit 111, 212, 611 Modulation data 112 Defect information 113, 612 Sync signal 114 Defect detection signal 115, 211 Defect signal 116, 613 Memory access control signal 117, 614 Memory read control signal 118 Number of defective frames 119 Frame read instruction signal 120, 615 Memory storage data 121, 616 Demodulated data 122 Data selection instruction signal 201 Synchronization detection / interpolation circuit 202 Channel clock counter 203 System clock counter 204 Synchronization interval measurement circuit 205 synchronization detection window generation circuit 206 pseudo synchronization generation circuit 207 synchronization signal generation circuit 213 channel clock 214 system clock 215 capacity component synchronization signal 216 synchronization detection window 217 channel clock count value 218 system clock count value 219 synchronization time interval signal 220 time component synchronization Signal 221 Sync signal

Claims (4)

In a synchronization generation method for detecting and interpolating a synchronization pattern of a frame read from a disk and generating a synchronization signal,
A synchronization detection / interpolation step that performs synchronization detection and synchronization interpolation using a synchronization detection window indicating a position where the synchronization pattern should be, and a channel clock read from the disk, and generates a capacitance component synchronization signal;
A channel clock count step for counting the number of channel clocks read from the disk based on the synchronization generated by the synchronization detection / interpolation step;
A synchronization detection window generating step of generating the synchronization detection window with reference to the count value counted by the channel clock counting step;
A system clock count step that receives a system clock whose frequency is always constant and counts the number of system clocks;
A synchronization interval measurement step for measuring a normal synchronization interval from the count value counted by the system clock count step with reference to the capacitance component synchronization signal output from the synchronization detection / interpolation step;
A pseudo-synchronization generating step for generating a time component synchronization signal based on the normal synchronization interval measured by the synchronization interval measurement step when the input modulation data is defective;
When there is no defect in the input modulation data, the capacitance component synchronization signal generated using the channel clock is output as a synchronization signal, and when the input modulation data is defective, the system clock is used. A synchronization signal generation step of outputting the time component synchronization signal generated as a synchronization signal,
If there is no defect in the input modulated data, by using the channel clock that is read from the disk, it performs the step of generating a synchronization signal by detecting and interpolating the sync pattern,
If there is a defect in the input modulation data, always using the system clock is a frequency constant, interpolating generates a synchronization signal based on the time component synchronizing signal generated when there is no defect in the modulation data A synchronization generation method characterized by executing steps. The synchronization generation method according to claim 1 ,
The method for generating synchronization, wherein the frequency of the system clock can be arbitrarily changed. In the sync generation circuit that detects and interpolates the sync pattern of the frame read from the disk and generates the sync signal,
Synchronization detection / interpolation means for performing synchronization detection and synchronization interpolation using a synchronization detection window indicating the position where the synchronization pattern should be, and a channel clock read from the disk, and generating a capacitance component synchronization signal;
A channel clock counter that counts the number of channel clocks read from the disk based on the synchronization generated by the synchronization detection / interpolation means;
Synchronization detection window generating means for generating the synchronization detection window with reference to the count value counted by the channel clock counter;
A system clock counter that counts the number of system clocks, taking as input the system clock whose frequency is always constant,
Synchronization interval measurement means for measuring a normal synchronization interval from a count value counted by the system clock counter with reference to the capacitance component synchronization signal output from the synchronization detection / interpolation means,
Pseudo-synchronization generation means for generating a time component synchronization signal based on the normal synchronization interval measured by the synchronization interval measurement means when the input modulation data is defective;
When there is no defect in the input modulation data, the capacitance component synchronization signal generated using the channel clock is output as a synchronization signal, and when the input modulation data is defective, the system clock is used. Synchronization signal generating means for outputting the time component synchronization signal generated as a synchronization signal,
If there is no defect in the input modulation data, a synchronization signal is generated by detecting and interpolating the synchronization pattern using the channel clock read from the disk,
If there is a defect in the input modulation data, always using the system clock is a frequency constant, interpolating generates a synchronization signal based on the time component synchronizing signal generated when there is no defect in the modulation data A synchronization generation circuit characterized by that. The synchronization generation circuit according to claim 3 ,
The frequency of the system clock can be arbitrarily changed.

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