CN100407326C - Sync Signal Protection Circuit - Google Patents

Abstract

The synchronizing signal protection circuit of the present invention is applied to an optical recording medium read/write device for correctly generating a synchronizing signal. The invention uses a pulse signal with fixed frequency as reference pulse, and counts the period of synchronous signal to obtain the count value of a frame period, thus when the synchronous signal is lost or noise is generated due to the defect of the disc, the reference pulse is used as the basis for calculating the frame period, and the correct synchronous signal is provided. Therefore, even if the PLL device produces drift of output pulse when the synchronous signal is lost or noise is generated due to the defect of the disk, the poor compensation period of the synchronous signal will not be affected.

Description

Sync Signal Protection Circuit

technical field

The present invention relates to a synchronous signal protection circuit (Sync Protection Circuit) applied to an optical recording medium read/write device, to use a fixed frequency pulse to estimate the correct frame period when a defect occurs on the disc, and interpolate Correct frame sync signal.

Background technique

The reading of existing optical recording media, such as CD (Compact Disc) and DVD, is to scan the digital data recorded on the optical recording media with a laser beam. In the case of CDs, digital data is recorded in the form of EFM (eight-bit to fourteen-bit modulation), and the digital data is arranged into a frame according to a set format before it can be recorded on the CD. Each frame contains a frame sync signal at the beginning of the frame. The frame synchronization signal is composed of 24 channel bits and has a special variation pattern to locate the start position of the frame.

In an optical disc playback system, the synchronous signal is used to generate a control signal to separate different frames. Therefore, a synchronous signal detection circuit is provided in an existing read/write device for an optical recording medium. At the same time, the device also needs to include a sync signal protection circuit (Sync Signal Protecting Circuit) combined with a sync signal detecting circuit, so that when the disc is defective and the sync signal is lost, the correct sync signal is inserted, So that the decoding of the data is not affected.

FIG. 4 is a structural diagram of an existing synchronous signal protection circuit. As shown in the figure, the synchronization signal protection circuit uses the PLL output pulse (PLCK) as a reference signal to estimate the interval period of the frame. However, when the surface of the optical recording medium is flawed or scratched and the synchronization signal is lost or noise occurs, the PLL output pulse cannot be locked and the frequency drift occurs, thereby causing a calculation error of the frame synchronization signal.

Figure 5 is a schematic diagram of the downward drift of the PLL output pulse due to the loss of synchronization signal or noise. As shown in FIG. 5 , when a defect occurs on the disk, that is, the defect signal is H, the PLL output pulse cannot be locked, which causes a period error of the interpolated synchronous signal, and causes an error in the processing of digital data. Taking the EFM pulse signal as an example, an EFM frame has 588T. When the noise appears at N+5, PLCK will have an error, so the frame period found in the fixed range (window) may be 560T, 540T, 520T etc. The cycle of 588T is not returned until the data is correct. If it is processed according to this period, the calculated frame synchronization signal will be wrong. The frame synchronization indication signal will appear periodically only when the data is normal. The actual synchronization signal (REAL SYNC) is used to determine whether the cycle of the frame synchronization signal is repeated in a fixed period. After finding that the actual synchronization signal disappears for several consecutive frames, the synchronization indicator signal falls to reflect that the cycle of the current frame synchronization signal is abnormal, and it does not rise until the actual synchronization signal is found again continuously. Relatively, the frame synchronization signal (FRAMESYNC) is generated according to the actual synchronization signal. When the actual synchronization signal is normal, the frame synchronization signal will be generated synchronously with the actual synchronization signal; but when the actual synchronization signal is abnormal and cannot appear, the frame The synchronization signal will calculate the position of the frame according to 588T. Taking Figure 5 as an example, the frame synchronization signal will gradually shift in the defect area, and when the actual synchronization signal is found again, the frame synchronization signal will re-synchronize with the actual synchronization signal, but due to the PLCK frequency drift in the defect area, the number of frames will be counted An error occurs, so an error occurs at position n+13.

Contents of the invention

Based on the above problems, the object of the present invention is to propose a synchronous signal protection circuit, which can correctly estimate the frame period by using a fixed pulse signal as a reference signal, and interpolate the synchronous signal in real time, so that the processing of digital data can be restored to normal.

In order to achieve the above object, the synchronous signal protection circuit of the present invention includes: a synchronous signal detection device, which is used to detect the synchronous signal according to the output pulse of the EFM signal and the PLL device, and output a synchronous indication signal; The number of pulses of the fixed-frequency reference pulse signal contained in each cycle of the indicator signal, and output the frame cycle; a judging device, used to judge whether the frame cycle is normal, and output an update signal when it is judged to be normal; a register A device for storing the frame period, and updating the stored frame period according to the update signal; a search device for finding a legal frame synchronization signal according to the frame period of the registration device, and outputting a search range; a synchronization signal judging device for Determine whether the synchronization indication signal is a correct synchronization signal according to the search range, and output the determination signal; a synchronization signal latch determination device, which is used to determine whether the period of the frame is normal according to the determination signal, and output a synchronization signal, and provide the synchronization The medium signal is given to the search device; and a synchronous signal generator is used to generate a synchronous signal according to the frame period and the determination signal.

Therefore, even if the output pulse of the PLL device drifts due to the loss of the synchronous signal or noise due to the defect of the disk, it will not affect the interpolation cycle of the synchronous signal.

Description of drawings

FIG. 1 is a system structure of an optical recording medium read/write device of the present invention.

Fig. 2 is the main structure of the synchronous signal protection circuit of the present invention.

FIG. 3 is a timing diagram of various signals of the synchronous signal protection circuit of the present invention.

FIG. 4 is a structural diagram of an existing synchronous signal protection circuit.

FIG. 5 is a timing diagram showing various signals of a conventional synchronous signal protection circuit.

Detailed ways

Embodiments of the synchronous signal protection circuit of the present invention will be described in detail below with reference to the accompanying drawings.

FIG. 1 shows the system structure of an optical recording medium read/write device. The signal picked up by the optical recording medium 10 via the read head is processed by the analog signal processor 13 to generate an RF signal. When the surface of the optical recording medium is damaged, it can be judged from the RF signal whether it is normal or not. For example, a normal RF signal has a fixed voltage level (level). If it contains noise, the reflection of the laser light will be attenuated. Therefore, it can be judged that it contains noise by its voltage value. Therefore, the defect determination signal (Defect) is generated by the signal noise detector 14 according to the RF signal. The defect determination signal can be provided to the signal cutter (Slicer) 15 and the phase locked loop (Phase Lock Loop, PLL) 16 to prevent the signal cutter 15 from shifting the slicer voltage when noise or defect occurs. , and avoid the phenomenon that the output pulse of the phase-locked loop is prevented from drifting when noise or flaw occurs.

The RF signal is input into the signal cutter 15 and then converted into a digital signal in EFM format. The EFM signal is input to the phase locked loop 16 to generate the PLL output pulse (PLCK). At the same time, the EFM signal is input into the sync signal protection circuit 17 to output a correct sync signal (Frame Sync signal) for data decoding and motor speed control.

The synchronization signal protection circuit 17 uses the fixed pulse signal VCK generated by the fixed pulse generator 18 as a reference pulse to estimate the frame period and output a synchronization signal. The demodulator 19 captures data in the frame for demodulation according to an indicator contained in the synchronization signal. The obtained data is processed by the CIRC decoder 110 and the CD-ROM decoder 111 to obtain desired data.

In addition, the fixed pulse signal VCK, the synchronization signal and the PLL output pulse PLCK are also provided to the motor speed controller 11 to control the speed of the spindle motor 12 according to the CAV or CLV mode.

According to this structure, the design of the signal noise detector 14 to the signal slicer 15 can protect and avoid the shift phenomenon caused by the noise or defect of the data slicer level. The drift of the cutting voltage will cause the digital data to have poor initialization after leaving the section where the noise occurs. The design of the signal noise detector 14 through the PLL 16 is to protect the PLL 16 from large drifts in the PLL output pulse during the occurrence of noise or glitches, which would take too long for the PLL 16 to recover to correct frequency. Moreover, in the tracking state (tracking state), the data will be wrong.

FIG. 2 is a functional block diagram of the synchronous signal protection circuit of the present invention. As shown in the figure, the synchronization signal detector 21 detects the synchronization signal according to the PLL output pulse PLCK and the EFM signal, that is, if (11T high+11T low+2T high) or (11T low+11T high+ 2T low), it means that the EFM signal contains the pattern of the synchronization signal (Frame Sync clock), so the detection synchronization signal (SYNC FOUND) is generated.

Frame Period Counter (Frame Period Counter) 22 uses the fixed pulse signal VCK as a reference pulse, and can calculate the interval period between two adjacent frames by detecting the frequency of occurrence of the synchronization signal, and then store the calculated result in the register device 23.

Since the data stored in the registration device 23 is not necessarily correct, it is necessary to use a valid frame period judgment device (Valid Frame Period Judgment) 24 to determine whether the current frame period is normal, and when the result of the judgment is normal , output an update instruction signal (UPDATE) to the register device 23 to update its record. The effective frame period determination device 24 is designed to track the transition state (transient state) under the change of data transition. If it is a constant angular velocity (CAV) mode, in the case of a slow change, the effective frame period determination device 24 can be used to update the changing interval period in the register device 23.

Since the frame interval will drift due to noise, the position of the next frame synchronization signal may not be correctly found at a fixed interval period. Therefore, a search device (WindowGenerator) 25 is used to expand the original fixed interval period to find the next frame synchronization signal. A synchronous signal to avoid misjudgment. The search device 25 transmits the searched range to a real sync signal judging device (Real Sync Judgment) 26 to judge whether the frame sync signal is a legal frame sync signal. If so, the actual synchronous signal is output to a synchronous signal generator (SYNC SIGNAL GENERATOR) 28. The synchronization signal generator 28 interpolates the correct frame synchronization signal according to the information of the actual synchronization signal and the frame period when the actual frame synchronization signal disappears or noise appears. Taking CD as an example, its frame period is 588T (T=1 PLCK pulse), while that of DVD is 1488T.

The synchronization signal latch judging device (Sync Lock Judgment) 27 judges whether the period of the frame synchronization signal is normal according to whether the frame synchronization signal can be found in the range of several consecutive times. If it can be found several times in a row, it means that the cycle of the frame synchronization signal is normal, so the synchronization indication signal (IN SYNC) is H and sent to the search device 25, otherwise it is L. Only when several consecutive synchronization indication signals are in a normal state, the actual synchronization signal uses the output of the search device 25 as the legal period of the frame synchronization signal.

FIG. 3 is a schematic diagram of the cycle of the present invention using the fixed-frequency pulse VCK as the reference pulse. As shown in Figure 3, taking the EFM pulse signal as an example, an EFM frame has 588T, and the fixed frequency pulse VCK is used to count the period of the frame synchronization signal to obtain m, that is, the 588 PLLK period is equal to the m VLK period. When noise occurs at N+5, since the frequency of the fixed-frequency pulse VCK is fixed, the period of the synchronous signal that uses the fixed-frequency pulse VCK as the reference pulse to lock the difference is also fixed, so the calculation of the frame is performed even when the noise occurs No error occurs either.

In summary, the present invention uses a fixed pulse signal as a basis for reference, so the number of frames can be correctly estimated, and the lost frame synchronization signal can be interpolated in real time, so that the processing of digital data is correct and the correct data can be solved . Moreover, the correct frame synchronization signal can be used to further control the rotational speed of the motor, and to decode data at constant linear and constant angular velocities. In addition, it can also be widely used in frame synchronization signal processing without identification code (non-ID frame sync), such as CD, and frame synchronization signal processing with identification code (ID frame sync), such as DVD.

The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the claims of the present invention shall fall within the scope of the patent of the present invention.

Claims (2)

1. synchronous signal protective circuit is applied to comprise in the optical record medium read/write device:

One synchronous signal supervisory instrument is used for the output pulse detection synchronizing signal according to 8 to 14 modulation signals and phase-locked loop apparatus, and output detects synchronizing signal;

One frame period counter, the umber of pulse of the reference burst signal of the fixed frequency that calculating was comprised in each cycle of aforementioned detection synchronizing signal, and output frame cycle;

One valid frame cycle decision maker is used to judge whether the aforementioned frame period is normal, and is being judged to be just often, the output update signal;

One LD device is used to store the aforementioned frame period, and according to aforementioned update signal, upgrades the frame period of being stored;

One searcher is looked for next frame synchronizing signal according to the frame period of upgrading in the aforementioned LD device, and the output hunting zone;

One synchronous signal determining device is used for judging according to aforementioned hunting zone whether aforementioned detection synchronizing signal is correct frame synchronizing signal, and the output decision signal;

One synchronous signal latch decision maker, be used for according to whether in several times aforementioned hunting zone continuously, looking for this correct frame synchronizing signal and judge whether the cycle of the frame synchronizing signal that this is correct is normal, and the output synchronous indicating signal, and provide this synchronous indicating signal to aforementioned searcher; And

One synchronous signal generator is used for frame period and aforementioned decision signal that the aforementioned LD device of foundation upgrades, produces synchronizing signal.

2. synchronous signal protective circuit as claimed in claim 1, wherein the frequency of above-mentioned reference pulse is the frequency of the output pulse of aforementioned phase-locked loop apparatus when phase-locked.

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