CN100407326C

CN100407326C - Synchronous signal protective circuit

Info

Publication number: CN100407326C
Application number: CN02127732XA
Authority: CN
Inventors: 蔡昭隆; 罗思善; 张垂弘
Original assignee: MediaTek Inc
Current assignee: MediaTek Inc
Priority date: 2002-08-07
Filing date: 2002-08-07
Publication date: 2008-07-30
Anticipated expiration: 2022-08-07
Also published as: CN1474401A

Abstract

The present invention relates to a synchronous signal protection circuit applied to an optical recording medium reading / writing device for correctly generating synchronous signals. The present invention obtains a count value of a frame period by using a pulse signal with fixed frequency as a reference pulse, and simultaneously counting periods of the synchronous signals so that correct synchronous signals are provided by using the reference pulse as the reference for calculating the frame period when synchronous signals are lost or noise is generated because disks are in defect. Thus, although the pulse output by a PLL device shifts because the synchronous signals are lost or the noise is generated when the disks are in defect, a differential compensation period of the synchronous signal can not be influenced.

Description

Synchronous signal protective circuit

Technical field

The present invention relates to a kind of synchronous signal protective circuit (Sync Protection Circuit) that is applied to the optical record medium read/write device; with when the disc generation flaw; utilize correct frame (frame) cycle of pulse estimation of fixed frequency, and the correct frame synchronizing signal of interpolation.

Background technology

Reading of existing optical record medium, as CD (Compact Disc), DVD is to be recorded in numerical data on the optical record medium with laser beam flying.With CD, the record of numerical data system according to a form of setting, is arranged in a frame (frame) with numerical data in the mode of EFM (eight-bit to fourteen-bit modulation), just can be recorded on the CD.Each frame all contains a frame synchronizing signal (frame sync signal) that is positioned at the frame starting position.Frame synchronizing signal is made of 24 (channel bits), and has the reference position that a special variation sample attitude (variation pattern) is come locating frame.

In disc-playing system, this synchronizing signal is used to produce control signal, so as to separating different frames.Therefore just has a synchronization signal detection circuit in the read/write device of existing optical record medium.This device also need comprise the synchronous signal protective circuit (Sync Signal Protecting Circuit) that combines with synchronization signal detection circuit (Sync signal detecting circuit) simultaneously; whereby when disc has flaw and cause synchronizing signal to lose; insert correct synchronizing signal, so that the decoding of data is unaffected.

Figure 4 shows that the structural drawing of existing synchronous signal protective circuit.As shown in the drawing, this synchronous signal protective circuit is to export pulse (PLCK) conduct with reference to signal, with the gap periods of estimated frames with PLL.Yet, when the surface of optical record medium is lost synchronizing signal because of flaw (defect) or scratch or noise (noise) occurred, will cause PLL output pulse to lock and frequency of occurrences drift, and then cause the miscount of frame synchronizing signal.

The PLL of being output pulse shown in Figure 5 is because the synoptic diagram of the downward drift of noise is lost or occurred to synchronizing signal.As shown in Figure 5, when disc generation flaw, promptly the defect signal is H, and PLL output pulse can't lock, and causes the cycle mistake of the synchronizing signal of institute's interpolation, and the processing of numerical data is made a mistake.With the EFM pulse signal is example, and the frame of an EFM has 588T, and when noise occurred at N+5 the time, mistake just appearred in PLCK, so the frame period that (window) found in fixing scope may be 560T, 540T, 520T etc.After data are correct, the cycle of just getting back to 588T.As if handling according to this cycle, the frame synchronizing signal of being calculated just can make a mistake.Only just the cycle occurs the frame synchronization indicator signal regularly under the normal situation of data.Actual synchronization signal (REAL SYNC) is used to then judge the frame synchronizing signal cycle of being looked for, whether the fixed cycle repeated.Synchronous indicating signal is after finding that the continuous several frames of actual synchronization signal disappear, and it is undesired with the cycle that reflects current frame synchronizing signal just to descend, and just rises after the actual synchronization signal finds again continuously.Relatively, frame synchronizing signal (FRAMESYNC) produces according to the actual synchronization signal, when the actual synchronization signal just often, frame synchronizing signal can produce with the actual synchronization signal Synchronization; But when the actual synchronization signal is undesired and can't occur the time, then frame synchronizing signal can be calculated the position of frame according to 588T.With Fig. 5 is example, and frame synchronizing signal can be offset gradually in defect areas, and when the actual synchronization signal picks up, frame synchronizing signal just again with the actual synchronization signal Synchronization, but the PLCK frequency drift because of defect areas causes the counting of frame error to occur, so make a mistake in the position of n+13.

Summary of the invention

Based on above-mentioned problem, the objective of the invention is to propose a kind of synchronous signal protective circuit, come the correct estimated frames cycle by utilizing fixing pulse signal as the reference signal, and the real-time interpolation synchronizing signal, so that the processing of numerical data recovers normal.

For reaching above-mentioned purpose, synchronous signal protective circuit of the present invention comprises: a synchronous signal supervisory instrument, be used for output pulse detection synchronizing signal according to EFM signal and PLL device, and the output synchronous indicating signal; One frame period counter, the umber of pulse of the reference burst signal of the fixed frequency that calculating was comprised in each cycle of synchronous indicating signal, and output frame cycle; One decision maker is used to judge whether the frame period is normal, and is being judged to be just often, the output update signal; One LD device is used for the storage frame cycle, and according to update signal, upgrades the frame period of being stored; One searcher is looked for legal frame synchronizing signal according to the frame period of LD device, and the output hunting zone; One synchronous signal determining device is used for judging according to the hunting zone whether synchronous indicating signal is correct synchronizing signal, and the output decision signal; One synchronous signal latch decision maker is used for judging according to decision signal whether the cycle of this frame is normal, and signal in the output synchronously, and provides this synchronously middle signal to searcher; And a synchronous signal generator, be used for according to frame period and decision signal, produce synchronizing signal.

Therefore, even because the PLL device causes synchronizing signal to lose because of disc generation flaw or when noise is arranged the output pulse produce drift, also can not influence the poor benefit cycle of synchronizing signal.

Description of drawings

Fig. 1 is the system architecture of optical record medium read/write device of the present invention.

Fig. 2 is the primary structure of synchronous signal protective circuit of the present invention.

Fig. 3 is the sequential chart of the various signals of synchronous signal protective circuit of the present invention.

Fig. 4 is the structural drawing of existing synchronous signal protective circuit.

Fig. 5 is the sequential chart of the various signals of the existing synchronous signal protective circuit of demonstration.

Embodiment

Describe the embodiment of synchronous signal protective circuit of the present invention in detail below with reference to accompanying drawing.

Figure 1 shows that the system architecture of optical record medium read/write device.The signal that this optical record medium 10 picks up via read head passes through after the processing of analogue signal processor 13, produces the RF signal.When the optical record medium surface damage, whether normally from the RF signal, just can judge.For example, normal RF signal has fixing magnitude of voltage (level), if wherein contain noise, just the reflection of laser can decay, therefore just can be judged by its magnitude of voltage and wherein contain noise.Therefore utilize signal noise detecting device 14 to produce flaw decision signal (Defect) according to the RF signal.This flaw decision signal just can offer signal cutter (Slicer) 15 and phaselocked loop (Phase Lock Loop, PLL) 16 prevent that stop signal cutter 15 is when noise or flaw generation, cut apart the drift (slicer level shift) of voltage, and avoid when noise or flaw generation, preventing the phenomenon of the output pulse generation drift of phaselocked loop.

Convert the digital signal of EFM form after the RF signal input signal cutter 15 to.This EFM signal inputs to phaselocked loop 16 to produce PLL output pulse (PLCK).Simultaneously, this EFM signal input sync signal holding circuit 17 is to export correct synchronizing signal (Frame Sync signal), for the usefulness of data decode and motor rotary speed control.

The fixed pulse signal VCK that synchronous signal protective circuit 17 is produced with fixed pulse generator 18 is as the reference pulse, the synchronizing signal of estimated frames cycle, and output thus.Detuner 19 supplies the usefulness of demodulation according to indicator signal contained in the synchronizing signal (indicator) with the data that grasp in the frame.Obtained data just can obtain desired data through the processing of CIRC demoder 110 and CD-ROM demoder 111.

In addition, fixed pulse signal VCK, synchronizing signal and PLL output pulse PLCK also offer motor rotary speed controller 11, control the rotating speed of Spindle Motor 12 thus according to CAV or CLV pattern.

According to this structure, data killer voltage (data slicer level) caused drift (shift) phenomenon when noise or flaw (defect) take place can be protected and avoid to signal noise detecting device 14 to the design of signal cutter 15.The drift of killer voltage will cause numerical data behind the section that leaves the noise generation, and not good initialization is arranged.Signal noise detecting device 14 to the design of phaselocked loop 16 then is to protect phaselocked loop 16, avoids PLL output pulse to produce significantly drift between the emergence period at noise or flaw, and makes phaselocked loop 16 spend the oversize time being returned to correct frequency.And under the state that seeks trajectory (tracking state), data will make a mistake.

Fig. 2 is the functional block diagram of synchronous signal protective circuit of the present invention.As shown in the drawing, synchronized signal detector 21 detects synchronizing signal according to PLL output pulse PLCK and EFM signal, that is, if read (11T high+11T low+2T high) or (11T low+11T high+2T low), just represent to contain in this EFM signal the sample attitude (pattern) of synchronizing signal (Frame Sync clock), detect synchronizing signal (SYNC FOUND) so produce.

Frame period counter (Frame Period Counter) 22 with fixing pulse signal VCK as the reference pulse, by the frequency of occurrences that detects synchronizing signal, just can calculate two gap periods between the adjacent frame, then result calculated is stored in the LD device 23.

Because the data of being stored in the LD device 23 are not necessarily correct, so need utilize a valid frame cycle decision maker (Valid Frame Pe riod Judgment) 24, judge whether the present frame period is normal, and in the result who judges for just often, output is upgraded indicator signal (UPDATE) to LD device 23, to upgrade its record.Valid frame cycle decision maker 24 is to design in order to be used for following the trail of transition status (transient state) under the variation of data-switching.If constant angular velocity (CAV) pattern, under situation about slowly changing, just can utilize the gap periods of valid frame cycle decision maker 24 in will changing to be updated in the LD device 23.

Because the interval of frame meeting drift to some extent because of noise, if possibly can't correctly find the position of next frame synchronizing signal with fixing gap periods, therefore utilize a searcher (WindowGenerator) 25 that script fixed intervals cycle expanded scope is looked for next synchronizing signal, the situation of avoiding judging by accident takes place.Whether searcher 25 sends the scope of search to actual synchronization signal determining device (Real Sync Judgment) 26, be legal frame synchronizing signal to judge this frame synchronizing signal.If just export the actual synchronization signal and give synchronous generator (SYNC SIGNAL GENERATOR) 28.When synchronous generator 28 disappears or noise occurs in the actual frame synchronizing signal, according to the information in actual synchronization signal and frame period, the frame synchronizing signal that interpolation is correct.With CD is example, and its frame period is 588T (T=1 PLCK pulse), then is 1488T among the DVD.

Synchronizing signal latchs decision maker (Sync Lock Judgment) 27 and can look for the situation of frame synchronizing signal according to whether judge whether the cycle of frame synchronizing signal is normal in several times scope continuously.If all can find several times continuously, be normal just represent the cycle of this frame synchronizing signal, so synchronous indicating signal (IN SYNC) is H, and sends searcher 25 to, otherwise be L.Have only and ought be all under the normal state by continuous synchronous indicating signal several times, the actual synchronization signal just can use the cycle of the output of searcher 25 as legal frame synchronizing signal.

Figure 3 shows that the present invention is with the cycle synoptic diagram of fixed frequency pulse VCK as the reference pulse.As shown in Figure 3, be example with the EFM pulse signal, the frame of an EFM has 588T, and the cycle of using fixed frequency pulse VCK to count frame synchronizing signal obtains m, that is 588 PLLK cycles equaled the m VLK cycle.When noise occurs at N+5 the time, because the fixed-frequency of fixed frequency pulse VCK, therefore also fixing with this fixed frequency pulse VCK as the cycle of the synchronizing signal of reference pulse lock difference benefit, so even the calculating of frame can not make a mistake when noise takes place yet.

In sum, the present invention utilizes fixing pulse signal foundation as a reference, then the number of estimated frames correctly, and the frame synchronizing signal that loses of interpolation in real time, so that the processing of numerical data is correct, solve errorless data.And, utilize correct frame synchronizing signal just can further control the rotating speed of motor, and the data decode under Constant Linear Velocity and the constant angular velocity.In addition, also can be widely used in not containing the frame synchronizing signal processing (non-ID frame sync) of identification code, as CD, and the frame synchronizing signal processing (ID frame sync) that contains identification code, as DVD.

The above only is the preferred embodiments of the present invention, and all equalizations of doing according to claim of the present invention change and modify, and all should belong to the covering scope of patent of the present invention.

Claims

1. synchronous signal protective circuit is applied to comprise in the optical record medium read/write device:

One synchronous signal supervisory instrument is used for the output pulse detection synchronizing signal according to 8 to 14 modulation signals and phase-locked loop apparatus, and output detects synchronizing signal;

One frame period counter, the umber of pulse of the reference burst signal of the fixed frequency that calculating was comprised in each cycle of aforementioned detection synchronizing signal, and output frame cycle;

One valid frame cycle decision maker is used to judge whether the aforementioned frame period is normal, and is being judged to be just often, the output update signal;

One LD device is used to store the aforementioned frame period, and according to aforementioned update signal, upgrades the frame period of being stored;

One searcher is looked for next frame synchronizing signal according to the frame period of upgrading in the aforementioned LD device, and the output hunting zone;

One synchronous signal determining device is used for judging according to aforementioned hunting zone whether aforementioned detection synchronizing signal is correct frame synchronizing signal, and the output decision signal;

One synchronous signal latch decision maker, be used for according to whether in several times aforementioned hunting zone continuously, looking for this correct frame synchronizing signal and judge whether the cycle of the frame synchronizing signal that this is correct is normal, and the output synchronous indicating signal, and provide this synchronous indicating signal to aforementioned searcher; And

One synchronous signal generator is used for frame period and aforementioned decision signal that the aforementioned LD device of foundation upgrades, produces synchronizing signal.

2. synchronous signal protective circuit as claimed in claim 1, wherein the frequency of above-mentioned reference pulse is the frequency of the output pulse of aforementioned phase-locked loop apparatus when phase-locked.