JP3795314B2 - Timing signal generator - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a timing signal generation device for detecting a link area which is a connection portion of information signals recorded on a recordable optical disc or the like and generating a timing signal indicating that a reproduction position is a link area. Is.
[0002]
[Prior art]
Recently, recordable disc media such as CD-R (Compact Disc-Recordable) that is a write once optical disc, CD-RW (Compact Disc-Rewriteable) that is a rewritable optical disc, and MD (MiniDisc) that is a magneto-optical disc are In addition to the use of editing and recording music data and enjoying music outdoors using a portable player, there is an increasing tendency to use it for storage purposes.
[0003]
This is because the manufacturing cost of the optical disk is very low, and it has a sufficient storage capacity for recording music and video, and it is considered that the number of audio-visual equipment using the optical disk will increase in the future.
[0004]
When new data is to be recorded on the recording area of such an optical disc, the data is not accidentally deleted as a result of writing data on the already recorded data. In addition, when an optical disc is played back, there is a relatively long unrecorded area between consecutive data. As a result, a tracking error signal cannot be generated and the tracking servo is removed, resulting in a failure in playback operation. In order to avoid such a problem that it becomes possible, a linking rule is defined by the standard document.
[0005]
According to the MD linking rule, in the FDh sector of each cluster, which is the minimum recording unit, EFM signal recording must be started and finished within a specified time of 49 ± 10 EFM frames from the detected ADIP signal synchronization pattern. It is prescribed. This area of the specified time is called “link area”. Each cluster is composed of a plurality of sectors, and each sector has an internal link area as a link area candidate for a specified time of 49 ± 10 EFM frames from the synchronization pattern of the ADIP signal. Of the plurality of internal link areas that are candidates for such a link area, the link area corresponds to a specific address corresponding to the FDh sector. A timing signal is output when such a link area is detected.
[0006]
In addition, “h” of FDh indicates that it is expressed in hexadecimal (hexadecimal number). ADIP is “Address In Pregroove”, and EFM is “Eighteen to Fourteen Modulation”.
[0007]
More specifically, the link area is a 20 EFM frame area from the 40th EFM frame to the 59th EFM frame after the detection of the synchronization pattern of the FDh sector, and it is allowed that data overwriting and unrecorded area over the longest 20 EFM frame are generated. Has been. As will be described later, the FDh sector on the optical disc corresponds to the FCh sector shifted by one sector in signal processing.
[0008]
Normally, when data is reproduced from an optical disk, an EFM signal reproduced from the optical disk is converted into a binary signal by a comparator, and the binarized EFM signal is input to a PLL (Phase Locked Loop) to generate an extraction clock.
[0009]
Then, the binarized EFM signal is punched out at the timing of the rising edge of the extracted clock, and the data string is EFM demodulated to restore information such as music.
[0010]
When an optical disc recorded in accordance with the above linking rules is reproduced, there is a case where no recorded signal is recorded in the link area, and it is not known how the signal reproduced from the optical disc behaves in such a situation. In the worst case, it is conceivable that the reproduced EFM signal oscillates in a high frequency band and the output signal of the comparator generates chattering. As a result, the phase lock of the PLL is lost.
[0011]
In addition, if the phase lock of the PLL is released, the playback position moves through the unrecorded link area to the area where the recording signal exists again, and even when a normal playback signal is input from the optical disk, the PLL is Since extra time is required until the phase is locked, considerable time is required to stably demodulate data.
[0012]
Therefore, conventionally, when a timing signal indicating that the reproduction position is in the link area is generated, and it is determined that the reproduction position is in the link area using the timing signal, the operation of the comparator that binarizes the reproduction signal is temporarily performed. By stopping and holding the output signal, chattering is prevented from occurring, and the phase lock of the PLL that extracts the clock of the binarized signal is protected.
[0013]
When the PLL determines that the reproduction position is in the link area using the timing signal, the operation is temporarily held, and a process of continuously outputting a signal having the output cycle immediately before the hold is performed. That is, double protection processing is performed against the phase out of the PLL.
[0014]
Next, a timing signal generation apparatus for an MD player according to the prior art will be described with reference to FIG. 10, FIG. 11, and FIG.
[0015]
FIG. 10 shows a block diagram of the timing signal generating apparatus, which is composed of an ADIP demodulating circuit 1001, a PLL 1002, and a link signal output circuit 1005 including a link signal output timing generating circuit 1003 and an output determining circuit 1004.
[0016]
FIG. 11 is a signal waveform diagram for explaining the operation of the timing signal generator. The bi-phase signal BPDT (a), which is a binary signal obtained by FM demodulation of the ADIP signal, and the PLL from the BPDT (a) BPCK (b) which is a clock extracted using the ADIP synchronization signal ADSY (c) indicating the position of the synchronization pattern of the ADIP signal, PCK (r) which is a clock extracted from the EFM signal using the PLL 1002, and each An internal LINK (h ′) indicating an area from the 39th EFM frame to the 59th EFM frame after the sector synchronization signal is shown.
[0017]
FIG. 12 is a signal waveform diagram for explaining the operation of the output determination circuit 1004. The address data (i) recorded on the disk, the ADIP signal synchronization signal ADSY (c), and the reproduction signal from the disk are demodulated. These are signal waveforms of the obtained address data (j), the internal LINK (h ′) output from the link signal output timing generation circuit 1003, and the timing signal LINK (h) output from the output determination circuit 1004.
[0018]
The ADIP demodulating circuit 1001 generates a binary BPDT (a) by FM-demodulating the ADIP signal reproduced from the MD, and extracts a clock BPCK (b) from the BPDT (a) using an internal PLL. .
[0019]
The frequency of the extracted clock BPCK (b) is about 6.3 kHz, and the data string is extracted by punching out BPDT (a) at the rising edge of BPCK (b).
[0020]
The synchronization pattern of the ADIP signal is defined such that the data sequence after FM demodulation is “11101000” (shown) or “00010111”. If the data sequence matches the synchronization pattern, the next BPCK (b ) During the period up to the rising edge, the synchronizing signal ADSY (c) is set to logic H and output. For other periods, the synchronization signal ADSY (c) outputs logic L.
[0021]
Further, the ADIP demodulating circuit 1001 obtains address data and an error detection code CRC (Cyclic Redundancy Check) by bi-phase demodulating the data sequence following the synchronization pattern, and uses the CRC to determine whether there is an error in the demodulated address data. Calculate.
[0022]
The address data obtained here is a total of 24 bits of data of cluster 16 bits and sectors 8 bits and CRC 8 bits.
[0023]
The PLL 1002 extracts the clock PCK (r) from the binarized EFM signal and outputs it to the link signal timing generation circuit 1003. The frequency of the clock PCK (r) extracted here is about 4.3218 MHz.
[0024]
One EFM frame is composed of 588 clock PCK (r) units, and the frame synchronization signal at the head of each EFM frame is repeated at a cycle of 4.3218 MHz / 588 = 7.35 kHz.
[0025]
In the link signal output timing generation circuit 1003, the internal signal corresponding to the internal link area as a link area candidate is determined based on the synchronization signal ADSY (c) input from the ADIP demodulation circuit 1001 and the clock PCK (r) input from the PLL 1002. LINK (h ′) is generated.
[0026]
Next, the process of generating the internal LINK (h ′) will be described using FIG.
[0027]
The link signal output timing generation circuit 1003 has a counter inside, and resets the counter to zero when the synchronization signal of the ADIP signal is detected, that is, when the synchronization signal ADSY (c) becomes logic H. Thereafter, the counter is incremented at every rising edge of the clock PCK (r).
[0028]
Therefore, when the counter value matches “588 × 39”, it can be determined that the disc playback position has entered the 40 EFM frame from detection of the sync signal, and when the counter value matches “588 × 59”, It can be determined that the playback position of the disc has entered the 60th EFM frame from the detection of the synchronization signal, that is, the 59th EFM frame has ended.
[0029]
The internal LINK (h ′) corresponding to the internal link area as a link area candidate output by the link signal output timing generation circuit 1003 is based on the counter value in accordance with the counter pattern detection from the 40th EFM frame to the 59th EFM frame. The area up to the eye is set to logic H, and the other areas are set to logic L.
[0030]
According to the linking rules, the link area is defined only in the FDh sector among a plurality of sectors in each cluster, but this indicates the position on the disk, and when the actual reproduction operation is performed, Is demodulated to determine the address, the internal address data is updated at the timing after all the data of the FDh sector has been read.
[0031]
That is, as shown in FIG. 12, the address data (i) on the disc and the address data (j) in the ADIP demodulator circuit 1001 are shifted by one sector, and the playback position of the disc is defined by the linking rule. The link area is the case where the address data (j) is a sector that is FCh of a specific address.
[0032]
The output determination circuit 1004 inputs the internal LINK (h ′) and the address data (j), and when the address data (j) is the specific address FCh, the internal LINK (h ′) is output as it is as the timing signal LINK (h). When the address data (j) is other than the specific address FCh, the timing signal LINK (h) corresponding to the link area defined by the linking rule is generated by outputting the timing signal LINK (h) as logic L. Can do.
[0033]
[Problems to be solved by the invention]
In the timing signal generation device according to the above-described prior art, a clock is extracted from the EFM signal using a PLL, and the position of the link area is obtained by utilizing a fixed ratio between the period of the extracted clock and the period of the EFM frame. Is.
[0034]
The PLL 1002 is designed to have a wide tracking band in order to make it difficult to remove the phase lock. The PLL 1002 also follows the disturbance of the EFM signal due to defects such as dust and fingerprints on the disk surface. The period of the extracted clock is disturbed in the period, and the disturbance of the period is accumulated in the counter in the link signal timing generation circuit 1003 so that the position of the link area is shifted or longer than the specified time (20 EFM frame) of the link area. There has been a problem of becoming an area or a short area.
[0035]
Also, as a recent effort to save power, the optical disk playback device increases the transfer speed by rotating the optical disk at a higher speed than the normal speed, stores a large amount of reproduced data in the buffer, and stores the remaining data in the buffer. In the case where there is sufficient power, a technique has been introduced in which the reproduction operation from the optical disk is stopped and the power consumed by mechanical elements such as a spindle motor and an actuator is reduced.
[0036]
Furthermore, from the viewpoint of cost reduction, an effort has been made to use a CAV (Constant Angular Velocity) control for the rotation control of the optical disc, which can be simplified as compared with a complex CLV (Constant Linear Velocity) control circuit.
[0037]
For the above-mentioned approach, development of a signal processing circuit corresponding to a variable linear velocity is one solution.
[0038]
However, in a normal PLL, the period of the input signal needs to be within a range of about ± 10% of the design target value in order to lock the phase. In the configuration according to the conventional technique, the linear velocity changes due to the CAV control. There was a problem that it could not be handled.
[0039]
As a countermeasure, a configuration with multiple PLLs to accommodate various linear velocities is possible. However, the circuit scale increases significantly, so an increase in cost cannot be avoided and the circuit design is complicated. You will face the problem of becoming.
[0040]
[Means for Solving the Problems]
The present invention for the timing signal generator solves the above-mentioned problems by taking the following measures.
[0041]
The present invention assumes the following configuration. In an apparatus for reproducing an information signal from a disc in which an information signal is recorded in a predetermined recording unit and having a predetermined link area at a connection portion of the recording unit, the playback position on the disc is the link area The timing signal generating apparatus for generating the timing signal shown in FIG. 1 further includes information demodulating means for demodulating the synchronization signal and address information from the reproduction signal of the disk, as in the prior art.
[0042]
Here, the predetermined recording unit can be exemplified by a cluster which is a group of a plurality of sectors. Typical examples of the information signal include an audio signal, a video signal, a video / audio mixed signal, and a data signal. The connection part is an area for connecting from one recording unit (cluster) to the next predetermined recording unit (cluster). However, these are merely examples, and the present invention is not necessarily limited to such.
[0043]
The timing signal generation device of the present invention is characterized by further including the following elements in addition to the above assumptions. That is, as an alternative to the PLL in the conventional technique, an average period detecting means for detecting the average period value of the reproduction signal is provided. Then, the timing signal output means obtains an internal link area as a link area candidate based on the synchronization signal from the information demodulation means and the average period value from the average period detection means, and from the information demodulation means When the address becomes a specific address, the internal link area is specified as a link area and the timing signal is output.
[0044]
Here, for ease of understanding, as a reference, the correspondence relationship with the constituent elements in the embodiments described later is described. The information demodulating means corresponds to an ADIP demodulating circuit as an example, and the average period The detection means corresponds to an average period detection circuit, and the timing signal output means corresponds to a link signal output circuit. The specific address corresponds to FCh as an example. However, these are merely examples, and the present invention is not necessarily limited to such.
[0045]
The effect | action by the said structure of this invention is as follows. In each sector in the cluster as a typical example of the recording unit, the information demodulating means demodulates the synchronization signal and address information from the reproduction signal. The average period detecting means detects an average period value for the reproduction signal from the disc. For example, an average period value can be obtained by reproducing an address signal for tracking servo recorded in advance on the disk and counting between rising edges or falling edges with a clock. In the case of an address signal in which a high-frequency component and a low-frequency component are mixed, the average period value can be obtained by using a low-pass filter. Since the average period value is equivalent to a low-frequency component, even if a defect such as dust or fingerprint exists on the disk, the influence hardly affects.
[0046]
There is a certain correlation (proportional relationship) between the recording frequency of the information signal recorded on the disc and the recording frequency of the address signal. This correlation does not change even if the linear velocity of the disk changes. That is, if the average period value of the reproduced address signal is obtained regardless of the linear velocity of the disk, the frame length of the information signal can be easily obtained.
[0047]
The timing signal output means obtains the position of the internal link area as a link area candidate in each sector based on the synchronization signal from the information demodulation means and the average period value from the average period detection means. For example, the number of frames corresponding to the reproduction signal from the disc is counted. For the measurement of one frame of the reproduction signal, the starting point of the measurement is determined by the synchronization signal. When the clock count value becomes a predetermined constant multiple of the average period value, it is set as one frame. In each sector, the number of frames to the number of frames from the synchronization signal in the internal link area is determined in advance by the disc standard. The timing signal output means counts the number of frames of the information signal and obtains an internal link area for each sector. A plurality of such internal link areas are candidates for the link area. In all sectors constituting the cluster, such an internal link area as a link area candidate is obtained. At least until the regular link area is obtained, the internal link area is obtained.
[0048]
Further, the timing signal output means determines whether or not the address is a specific address based on the address information from the information demodulation means, and sets the specific address among the plurality of internal link areas that are link area candidates. A corresponding internal link area is specified as a link area, and a timing signal is generated and output in the link area.
[0049]
As described above, by using the average period value of the playback signal, even if the playback signal has deteriorated due to dust or fingerprint defects on the disk surface, the link area is accurately obtained and the timing is accurately determined. In addition, since the average period value has a certain correlation with the linear velocity, it is possible to cope with changes in linear velocity during playback without any significant increase or change in circuit. it can.
[0050]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be generally described below.
[0051]
The timing signal generating device according to the first aspect of the present invention is an apparatus for reproducing the information signal from a disc in which an information signal is recorded in a predetermined recording unit and a predetermined link area is provided at a connection portion of the recording unit. A timing signal generating device for generating a timing signal indicating that the upper reproduction position is the link area, information demodulating means for demodulating synchronization signal and address information from the reproduction signal of the disc; Mean period detecting means for detecting an average period value, and obtaining an internal link area as a link area candidate based on the synchronization signal and the average period value, and linking the internal link area when the address becomes a specific address Timing signal output means for specifying the region and outputting the timing signal is provided.
[0052]
The configuration of the first invention corresponds to the configuration of the above-mentioned section [Means for Solving the Problems] described in another form of expression. It is substantially the same as that described in the section of [Means for Doing]. In other words, by using the average period value of the playback signal, even if the playback signal is deteriorated due to dust or fingerprint defects on the disk surface, the link area is accurately determined and the timing signal is generated with high accuracy. Further, since the average period value has a certain correlation with the linear velocity, it is possible to cope with a change in linear velocity during reproduction without accompanying a significant increase or change in circuit.
[0053]
In a timing signal generating apparatus according to a second aspect of the present invention as a preferred embodiment, in the first aspect, the information demodulating means generates and outputs a status signal based on an internal signal, and the timing signal output means The output of the timing signal is prohibited based on the status signal.
[0054]
According to a third aspect of the present invention, there is provided the timing signal generating device according to the second aspect of the invention, wherein the information demodulating means outputs the status of a detection window for detecting a synchronization signal as the status signal. Features.
[0055]
The operation of the second and third inventions is as follows. If the information demodulator cannot stably demodulate the address information due to defects such as dust or fingerprints on the disk, it is not a specific address in practice, but it is erroneously determined to be a specific address. There is a possibility. In such a case, a false timing signal is unexpectedly output, and a protection operation such as a hold may erroneously occur in the comparator that binarizes the reproduction signal and the PLL that extracts the clock of the binarized signal. . As described above, when the information demodulating means cannot stably demodulate the address information, the information demodulating means outputs a status signal to the timing signal output means, thereby prohibiting the timing signal output means from outputting the timing signal. As a result, a false timing signal is not unexpectedly output, and an inconvenient situation in which a protective operation such as a comparator or PLL hold is erroneously performed can be avoided.
[0056]
According to a fourth aspect of the present invention, there is provided a timing signal generating apparatus according to the second and third aspects of the invention, wherein the information demodulating means outputs the calculation result of the error detection code as the status signal. Features.
[0057]
This uses the calculation result of the error detection code as the status signal instead of using the status of the detection window for detecting the synchronization signal as the status signal, and exhibits the same effect as described above. In other words, if the information demodulating means cannot stably demodulate the address information due to defects such as dust and fingerprints, a status signal that is the result of the error detection code is output and a false timing signal is unexpectedly output. It is possible to avoid an inconvenient situation in which a protective operation such as a comparator or PLL hold is erroneously performed.
[0058]
According to a fifth aspect of the present invention, in the first to fourth aspects of the invention, the information demodulating means outputs an error detection code calculation result, and the timing signal output means includes an internal address register. And the internal address register corrects an address output from the information demodulating means in accordance with a calculation result of the error detection code.
[0059]
The operation of the fifth invention is as follows. If the above-mentioned protection operation prohibition process is performed when the information demodulating means continuously demodulates the address information due to defects such as dust or fingerprints on the disk, it is actually a specific address. Nevertheless, there is a possibility that it is erroneously determined that it is not a specific address. In this case, the normal timing signal is not output to the normal link area, and if the link area is in an unrecorded state, the comparator for binarizing the reproduction signal and the clock of the binarized signal are extracted. There is a possibility that the PLL is out of phase lock due to an abnormal signal in the PLL. In this way, as a countermeasure when the information demodulating means continuously makes an error in address demodulation, the information demodulating means outputs the calculation result of the error detection code to the timing signal output means. The timing signal output means is provided with an internal address register for correcting the address from the information demodulating means based on the calculation result of the error detection code. This internal address register uses the address from the information demodulating means as it is when the error detection code calculation result is normal. In the case of an abnormality, the previous address is updated and corrected by incrementing etc., and a correct address is always secured. As a result, the link area can always be accurately detected even when address demodulation is continuously erroneous.
[0060]
(Specific embodiment)
Hereinafter, specific embodiments of a timing signal generating apparatus according to the present invention will be described in detail with reference to the drawings.
[0061]
(Embodiment 1)
FIG. 1 is a block diagram showing a configuration of a timing signal generation apparatus according to Embodiment 1 of the present invention.
[0062]
As shown in the figure, the timing signal generation device includes an ADIP demodulation circuit 101, an average period detection circuit 102, and a link signal output circuit 105 including a link signal output timing generation circuit 103 and an output determination circuit 104. That is, in the first embodiment, the average period detection circuit 102 is used instead of the PLL 1002 of the conventional timing signal generation device (FIG. 10).
[0063]
FIG. 2 is a signal waveform diagram for explaining the operations of the ADIP demodulating circuit 101, the average period detecting circuit 102, and the link signal output timing generating circuit 103. The biphase data BPDT (a) obtained by binarizing the ADIP signal by FM demodulation. The clock BPCK (b) extracted from the bi-phase data BPDT (a), the synchronization signal ADSY (c) that is the synchronization signal of the ADIP signal, and the average period that is a value obtained by triple the average period data of the ADIP signal Value data (d), signal waveforms and data of an EFM frame measurement counter (e), a LINK EFM frame detection signal (f), and an internal LINK counter (g) in the link signal output timing generation circuit 103.
[0064]
FIG. 3 is a signal waveform diagram for explaining the operation of the link signal output timing generation circuit 103. The signal waveforms of the LINK EFM frame detection signal (f), the internal LINK counter (g), and the internal LINK signal (h ′) It is data.
[0065]
The ADIP demodulating circuit 101 and the output determining circuit 104 perform the same operations as those of the timing signal generating apparatus described with reference to FIG. 10 in the prior art, and description thereof is omitted here.
[0066]
Therefore, the operations of the average period detection circuit 102 and the link signal output timing generation circuit 103 will be described here.
[0067]
The average period detection circuit 102 is a circuit for calculating an average period of the ADIP signal reproduced from the disk, binarizes the input ADIP signal, and counts between rising edges or falling edges of the signal by a clock, The period data of the ADIP signal as the count value is updated as needed.
[0068]
The ADIP signal has a high frequency component, which is a periodic deviation due to FM modulation, and a low frequency component, which is a fluctuation of the FM carrier frequency, as main frequency components. By passing the periodic data of the ADIP signal through a low pass filter, Only the frequency component sufficiently lower than the high frequency component due to the deviation is extracted, and data having only the low frequency component due to the fluctuation of the FM carrier frequency is output. This output data indicates the average period of the ADIP signal, and is data corresponding to the FM carrier frequency of about 22.05 kHz.
[0069]
Also, even if there are defects such as dust and fingerprints on the disk surface, the effect only affects the relatively high frequency components of the ADIP signal and is removed by the low-pass filter. It is thought that there will be almost no influence on.
[0070]
Next, the link signal output timing generation circuit 103 will be described.
[0071]
The link signal output timing generation circuit 103 receives the synchronization signal ADSY (c) and the average period value data (d), and stores the link signal output timing generation circuit 103 in the internal link area as a candidate link area indicating the 39th to 59th EFM frame areas of each sector. A corresponding internal LINK (h ′) is generated.
[0072]
Usually, the synchronization signal of the EFM frame has a period corresponding to 7.35 kHz, and the average period of the ADIP signal is equivalent to 22.05 kHz. The ratio of 7.35 kHz: 22.05 kHz = 1: 3 is constant, and is always kept constant even if the linear velocity of the disk changes.
[0073]
In other words, if the average period of the ADIP signal is obtained regardless of the linear velocity at which the disc is reproduced, the length of one EFM frame can be easily obtained. A certain internal link area can also be easily obtained.
[0074]
The operation for obtaining the length of one EFM frame from the average period of the ADIP signal will be described with reference to FIG.
[0075]
The link signal output timing generation circuit 103 includes a frame counter (e), and when the rising edge of the synchronization signal ADSY (c) is detected, the counter (e) is reset to zero.
[0076]
The counter (e) is incremented by a clock having the same frequency as that measured for the period data of the ADIP signal. When the counter (e) matches the average period value data (d) obtained by multiplying the average period data of the ADIP signal, the counter is reset to zero. To do.
[0077]
The LINK frame detection signal (f) is set to logic H at the moment when the counter (e) coincides with the average period value data (d) obtained by multiplying the average period data of the ADIP signal by three, and is set to logic L again after a certain time. As a result, the polarity of the LINK frame detection signal (f) changes from logic L to logic H every 1 EFM frame.
[0078]
Further, the link signal output timing generation circuit 103 includes an internal LINK counter (g). When the rising edge of the synchronization signal ADSY (c) is detected, the counter (g) is reset to the initial value “1”, and the LINK counter When the rising edge of the frame detection signal (f) is detected, the counter (g) is incremented.
[0079]
This count value indicates the number of EFM frames in the current disc reproduction position from the synchronization pattern of the ADIP signal. As shown in FIG. 3, the internal LINK counter (g) is 40d (“ If d ″ is a decimal number (decimal number) to 59d, and the internal LINK (h ′) is set to logic H, the position of the internal link area as a link area candidate can be obtained. it can.
[0080]
After determining the internal LINK (h ′) corresponding to the internal link area in the link signal output timing generation circuit 103 as described above, the output determination circuit 104 in the link signal output circuit 105 is the same as in the conventional technique. , Based on the internal LINK (h ′) from the link signal output timing generation circuit 103 and the address from the ADIP demodulation circuit 101, a plurality of internal outputs sequentially output for each sector in the same manner as in FIG. A timing signal LINK (h) is output at a timing corresponding to the specific address FCh in LINK (h ′). That is, the position of the link area as defined in the linking rule can be obtained.
[0081]
As described above, according to the timing signal generation device of the first embodiment, by providing the average period detection circuit 102 and the link signal output timing generation circuit 103, it is possible to deal with defects such as dust and fingerprints on the disk surface. Since the timing signal is generated using the average period of the ADIP signal having a certain correlation with the linear velocity, the circuit configuration can be changed. It is possible to generate a timing signal corresponding to a change in linear velocity.
[0082]
(Embodiment 2)
A timing signal generation apparatus according to Embodiment 2 of the present invention will be described with reference to FIGS. 4, 5, and 6.
[0083]
FIG. 4 is a block diagram showing the configuration of the timing signal generation device according to Embodiment 2 of the present invention.
[0084]
As shown in the figure, the timing signal generation device includes an ADIP demodulation circuit 401, an average period detection circuit 402, and a link signal output circuit 405 including a link signal output timing generation circuit 403 and an output determination circuit 404. In the second embodiment, a status signal indicating an internal state is output from the ADIP demodulating circuit 401 and input to the output determining circuit 404.
[0085]
FIG. 5 is a signal waveform diagram illustrating the detection window status which is a status signal. From the ADIP signal, a synchronization signal (k) (hereinafter referred to as a detection synchronization signal) indicating that a synchronization pattern has been detected from the ADIP signal. A synchronization signal (m) to be interpolated when no synchronization pattern is detected (hereinafter referred to as an interpolation synchronization signal), an ADIP signal synchronization signal ADSY (c) output from the ADIP demodulation circuit 401, and a detection window It is a signal waveform of the detection window status (n) indicating the state of.
[0086]
FIG. 6 is a signal waveform diagram for explaining the operation of the timing signal generating apparatus according to the second embodiment of the present invention. The address (i) on the disk, the ADIP signal synchronization signal ADSY (c), and demodulated address data ( j), the detection window status (n), and the signal waveform and data of the timing signal LINK (h).
[0087]
The average period detection circuit 402 and the link signal output timing generation circuit 403 perform the same operations as those of the timing signal generation apparatus of FIG. 1 according to the first embodiment of the present invention, and description thereof is omitted here.
[0088]
Therefore, here, the ADIP demodulation circuit 401 and the output determination circuit 404 will be described.
[0089]
The ADIP demodulation circuit 401 detects the synchronization pattern of the ADIP signal and outputs the synchronization signal ADSY (c). However, a protection processing circuit is provided as a countermeasure when the synchronization detection cannot be performed.
[0090]
The ADIP sector is composed of data corresponding to 84 clocks BPCK, and the synchronization pattern exists at the head of the ADIP sector and is recorded with a data length corresponding to 8 clocks BPCK (see FIG. 11). That is, when a normal ADIP signal is demodulated, a synchronization pattern is always detected with a period of 84 BPCK.
[0091]
If this rule is followed, even if the ADIP signal synchronization cannot be detected due to defects such as dust or fingerprints on the disk surface, if the clock BPCK can be generated normally, it is synchronized with the position of the synchronization signal that should exist originally. A signal can be inserted. This signal is the interpolation synchronization signal (m).
[0092]
Therefore, there are two types of synchronization signals in the ADIP demodulation circuit 401. One of the two types of synchronization signals must be selected and the synchronization signal ADSY (c) must be output. The method used is to use a detection window.
[0093]
The detection window indicates an allowable range of time axis fluctuation of the detection synchronization signal (k) with respect to the interpolation synchronization signal (m). When the detection window is set, the detection synchronization signal (k) is located inside the detection window. If it is detected in step (b), it is determined that it matches the interpolation synchronization signal (m), and the detection synchronization signal (k) is output as it is as the synchronization signal ADSY (c) without using the interpolation synchronization signal (m). If the detection synchronization signal (k) is detected outside the detection window, it is determined that the detection synchronization signal (k) does not match the interpolation synchronization signal (m), and the detected detection synchronization signal (k) is ignored. When no detection window is set, all detection synchronization signals (k) are output to the synchronization signal ADSY (c).
[0094]
The interpolation synchronization signal (m) is output 84BPCK after the output of the synchronization signal ADSY (c), and when the synchronization signal ADSY (c) is further output before counting the 84 clocks BPCK, at that time To reset the counter and count the clock BPCK. The interpolation synchronization signal (m) is output unconditionally to the synchronization signal ADSY (c).
[0095]
Under the above conditions, the synchronization signal ADSY (c) is generated from the detection synchronization signal (k) or the interpolation synchronization signal (m).
[0096]
Next, how to determine whether or not to set a detection window will be described with reference to FIG.
[0097]
When the detection window is set, an object is to exclude a false synchronization signal that is generated at a position other than the original position due to a defect in the ADIP signal when the detection synchronization signal (k) is stably output. For example, it is set when the detection synchronization signal (k) and the interpolation synchronization signal (m) coincide with each other twice. That is, in the detection synchronization signal (k) in FIG. 5, since the third and fourth waveforms from the left coincide with the interpolation synchronization signal (m), the detection is the status signal at the fourth timing. Window status (n) is being launched.
[0098]
On the other hand, when the detection window is not set, the purpose is to match the phases when the detection synchronization signal (k) and the interpolation synchronization signal (m) do not coincide at all. For example, the setting is canceled when the detection synchronization signal (k) and the interpolation synchronization signal (m) do not match. That is, since there is no detection synchronization signal (k) at the fifth waveform from the left of the interpolation synchronization signal (m) in FIG. 5, the detection window status (n) is lowered at that timing. In the case of the second waveform from the left of the detection synchronization signal (k) in FIG. 5, the detection window status (n) is logic H at this stage, but this detection is used as the synchronization signal ADSY (c). The synchronization signal (k) is ignored.
[0099]
Due to such state transition, the ADIP demodulation circuit 401 controls the detection window so that the detection synchronization signal (k) and the interpolation synchronization signal (m) coincide as much as possible, and operates so that data demodulation can be performed stably.
[0100]
That is, conversely, when the detection window is set, the ADIP demodulating circuit 401 stably demodulates the address data (j). When the detection window is not set, the ADIP demodulation circuit 401 is stable. The possibility that the address data (j) is demodulated is low.
[0101]
Since the detailed contents of the interpolation are not directly related to the present invention, further explanation is omitted, but in any case, it was determined that the address demodulation was normal and stable in the ADIP demodulation circuit 401. Sometimes the status signal is set to logic H, and when it is determined that the address demodulation is unstable, the status signal is set to logic L. FIG. 5 shows this.
[0102]
Next, the output determination circuit 404 will be described.
[0103]
In addition to the operation of the timing signal generator described in the first embodiment, the output determination circuit 404 has a detection window status (n) that is a status signal input from the ADIP demodulation circuit 401 set to logic H (a detection window is set). ), The timing signal LINK (h) is output. However, when the detection window status (n) is logic L (detection window setting is canceled), the timing signal LINK (h) is fixed to logic L. Output.
[0104]
By the way, in the case of the timing signal generating apparatus in the first embodiment, the synchronization signal ADSY (c) and the address are set even when the setting of the detection window is released, that is, when the possibility of stably demodulating data is low. A link area is obtained using data (j) and average period data of the ADIP signal, and a timing signal LINK (h) is output. Such inconvenience will be described with reference to FIG.
[0105]
As shown in FIG. 6, in the case of the first embodiment, even if a sector that is not a specific address FCh is demodulated as a specific address FCh as a result of address demodulation, a false timing signal indicated by a broken line is shown in that sector. LINK (h) is output, and as a result, the comparator that binarizes the reproduction signal from the disc is held, and normal demodulation operation cannot be temporarily performed.
[0106]
However, in the case of the timing signal generation device according to the second embodiment of the present invention, it is determined from the detection window status (n) that stable data demodulation has not been performed, and the detection window status (n) becomes logic L and is stable. If there is a possibility that the data is not demodulated properly, the timing signal LINK (h) is forcibly fixed to the logic L and output, and the above-mentioned problems can be avoided.
[0107]
As described above, according to the timing signal generation device of the second embodiment, the detection window status is output from the ADIP demodulator circuit and is input to the output determination circuit, thereby eliminating defects such as dust and fingerprints on the disk surface. In addition to being able to generate a timing signal that is not affected and corresponds to a change in linear velocity, it can be avoided that a false timing signal LINK is output during data demodulation when the ADIP demodulation circuit is unstable.
[0108]
In the timing signal generator according to the second embodiment of the present invention, the status signal output from the ADIP demodulator circuit is the detection window status. Instead, for example, as shown in FIG. If it is determined that there is no error in the CRC address data check, the CRC operation result is set to logic H, and if it is determined to be error, the CRC operation result is output to the output determination circuit as logic L. Operation is obtained.
[0109]
(Embodiment 3)
A timing signal generation apparatus according to Embodiment 3 of the present invention will be described with reference to FIGS.
[0110]
FIG. 8 is a block diagram showing the configuration of the timing signal generation device according to Embodiment 3 of the present invention.
[0111]
As shown in the figure, the timing signal generation device includes an ADIP demodulation circuit 801, an average period detection circuit 802, and a link signal output circuit 806 including a link signal output timing generation circuit 803, an output determination circuit 804, and an address interpolation circuit 805. ing. In the third embodiment, the address interpolation circuit 805 is provided in the link signal output circuit 806. The address interpolation circuit 805 is provided with an internal address register for correcting the address from the ADIP demodulation circuit 801.
[0112]
FIG. 9 is a signal waveform diagram for explaining the operation of the timing signal generating apparatus according to the third embodiment of the present invention. The address (i) on the disk, the ADIP signal synchronization signal ADSY (c), and demodulated address data ( j), CRC calculation result (p), interpolation address data (q), and signal waveform and data of timing signal LINK (h).
[0113]
ADIP demodulation circuit 801, average period detection circuit 802, link signal output timing generation circuit 803, and output determination circuit 804 perform the same operations as the timing signal generation apparatus of FIG. 1 according to the first embodiment of the present invention. The description here is omitted.
[0114]
Therefore, the address interpolation circuit 805 will be described here.
[0115]
The address interpolation circuit 805 has an 8-bit internal address register (q) for address data, and the CRC calculation result (p) is logic H at the timing of the rising edge of the input synchronization signal ADSY (c). In this case, the input address data (j) is substituted into the internal address register (q), and when the CRC operation result (p) is logic L, the data stored in the internal address register (q) is incremented. The contents of the internal address register (q) will be referred to as interpolation address data.
[0116]
However, since the address data is sector information, when the interpolation address data (q) is incremented, it is incremented by 1 continuously from 00h to 1Fh, but after 1Fh, it is incremented to FCh, FDh, FEh, and FFh. The interpolation address data (q) returns to 00h in the next increment.
[0117]
Then, the address interpolation circuit 805 outputs the interpolation address data (q) data to the output determination circuit 804.
[0118]
Next, a detailed operation will be described with reference to FIG.
[0119]
Initially, the ADIP demodulation circuit 801 normally demodulates the address data (j) in order from 1Dh and 1Eh from the ADIP signal, and as a result, the CRC calculation result (p) also outputs logic H.
[0120]
Therefore, the interpolation address data (q) of the address interpolation circuit 805 matches the address data (j).
[0121]
Subsequently, the ADIP signal is disturbed by a defect such as dust or fingerprint on the disk surface, and the address data (j) to be demodulated is 1Fh, but it is erroneously demodulated as 00h, and the CRC calculation result (p) Becomes logic L, indicating that the address data (j) is an error.
[0122]
However, since the CRC calculation result (p) is logic L, the address interpolation circuit 805 does not substitute 00h, which is the address data (j), into the interpolation address data (q), but instead of the interpolation address data (q 1Fh that is a value obtained by incrementing 1Eh that is 1).
[0123]
Subsequently, the demodulated address data (j) is erroneously demodulated as 1 Ah different from the original sector data FCh (specific address), and the CRC calculation result (p) also becomes logic L, but the address interpolation circuit 805 performs interpolation. FCh (specific address) which is a value obtained by incrementing 1Fh held immediately before is assigned to address data (q).
[0124]
By the way, in the case of the timing signal generating apparatus according to the second embodiment, the output determination circuit determines whether the address demodulation is normally performed based on the internal status of the ADIP demodulation circuit, and if it is determined that the address demodulation is not normally performed. For example, the protection processing is performed so that the timing signal LINK is forcibly set to the logic L regardless of the address value of the sector and the false timing signal LINK is not output.
[0125]
However, even if the playback position of the disk is a regular link area, the timing signal LINK may be forced to be logically L due to the internal status of the ADIP demodulator circuit. Therefore, there is a problem that an abnormal signal is input to the comparator that binarizes the signal reproduced from the above and the PLL that extracts the clock of the binarized signal and the phase lock of the PLL is released.
[0126]
However, in the case of the timing signal generation apparatus according to the third embodiment of the present invention, address demodulation is performed by estimating address data together with address data demodulated by the ADIP demodulation circuit using the CRC calculation result, and generating interpolated address data. The timing signal LINK can be output as a logical H to the original link area even when the signal is unstable, and the above-described problems can be avoided.
[0127]
As described above, by providing the address interpolation circuit in the link signal output circuit, not only is it possible to generate a timing signal that is not affected by defects such as dust and fingerprints on the disk surface and also corresponds to a change in linear velocity, but also ADIP A reliable timing signal can be output even when the demodulating circuit demodulates unstable data.
[0128]
【The invention's effect】
According to the present invention for the timing signal generation device, an internal link area as a link area candidate is obtained based on the synchronization signal from the information demodulating means and the average period value from the average period detecting means, and the information demodulating means When the address becomes a specific address, the internal link area is identified as the link area and the timing signal is output, so the playback signal deteriorates due to dust or fingerprint defects on the disk surface. Even in this case, it is possible to accurately determine the link area and generate the timing signal with high accuracy, and furthermore, since the average period value has a constant correlation with the linear velocity, it is possible to significantly increase or change the circuit. Without change, it is possible to cope with a change in linear velocity during reproduction.
[0129]
Also, the reliability of the address demodulation is judged using the status signal that grasps the internal state of the information demodulating means and the calculation result of the error detection code. If it is judged that the demodulating state is not normal, the timing signal indicating the link area By prohibiting the output of the signal, a false timing signal is not unexpectedly output, and a protective operation such as a comparator that binarizes the reproduction signal and a PLL hold that extracts the clock of the binarized signal is performed. You can avoid the inconvenient situation that happens by mistake.
[0130]
Furthermore, in the internal address register of the timing signal output means, by correcting the address according to the calculation result of the error detection code from the information demodulation means, and always ensuring the correct address, even when address demodulation is continuously erroneous, The link area can always be accurately detected.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a timing signal generation device according to a first embodiment of the present invention.
FIG. 2 is a signal waveform diagram for explaining the operation of the ADIP demodulation circuit and the link signal output timing generation circuit according to the first embodiment of the present invention
FIG. 3 is a signal waveform diagram for explaining the operation of the link signal output timing generation circuit according to the first embodiment of the present invention;
FIG. 4 is a block diagram showing a configuration of a timing signal generation device according to Embodiment 2 of the present invention.
FIG. 5 is a signal waveform diagram for explaining a detection window status which is a status signal in Embodiment 2 of the present invention;
FIG. 6 is a signal waveform diagram for explaining the operation of the timing signal generation device according to the second embodiment of the present invention;
FIG. 7 is a signal waveform diagram illustrating an operation when a CRC calculation result is used as a status in Embodiment 2 of the present invention.
FIG. 8 is a block diagram showing a configuration of a timing signal generation device according to a third embodiment of the present invention.
FIG. 9 is a signal waveform diagram illustrating the operation of the timing signal generation device according to the third embodiment of the present invention.
FIG. 10 is a block diagram showing a configuration of a conventional timing signal generator
FIG. 11 is a signal waveform diagram for explaining operations of an ADIP demodulating circuit and a link signal output timing generating circuit in a conventional timing signal generating apparatus;
FIG. 12 is a signal waveform diagram for explaining an output determination circuit in a conventional timing signal generator;
[Explanation of symbols]
101, 401, 801, 1001 ADIP demodulation circuit
102, 402, 802 Average period detection circuit
103, 403, 803, 1003 Link signal output timing generation circuit
104, 404, 804, 1004 Output judgment circuit
105, 405, 806, 1005 Link signal output circuit
805 Address interpolation circuit
1002 PLL

Claims (5)

In an apparatus for reproducing an information signal from a disc in which an information signal is recorded in a predetermined recording unit and having a predetermined link area at a connection portion of the recording unit, the playback position on the disc is the link area A timing signal generating device for generating a timing signal, an information demodulating means for demodulating synchronization signal and address information from the reproduction signal of the disc, an average period detecting means for detecting an average period value of the reproduction signal, Timing for obtaining an internal link area as a link area candidate based on the synchronization signal and the average period value and specifying the internal link area as a link area and outputting the timing signal when the address becomes a specific address A timing signal generation device comprising a signal output means. 2. The information demodulating unit generates and outputs a status signal based on an internal signal, and the timing signal output unit prohibits the output of the timing signal based on the status signal. The timing signal generation device described. 3. The timing signal generating apparatus according to claim 2, wherein the information demodulating means outputs a status of a detection window for detecting a synchronization signal as the status signal. 4. The timing signal generating apparatus according to claim 2, wherein the information demodulating unit outputs an operation result of an error detection code as the status signal. The information demodulating means outputs an operation result of an error detection code, the timing signal output means has an internal address register, and the internal address register follows the operation result of the error detection code, and the information demodulating means 5. The timing signal generating apparatus according to claim 1, wherein an address output from the timing signal is corrected.

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