JP2002109750A - Device for generating timing signal - Google Patents

Abstract

PROBLEM TO BE SOLVED: To precisely presume a link area by a linking rule from a reproduction signal of an optical disc even if the reproduction signal gets disordered by defects such as dust or fingerprints on the surface of the optical disc and linear velocity at a time of reproducing changes in a wide range. SOLUTION: In a device that reproduces an information signal from the disc having a specific link area in a cluster and generates a timing signal showing that a reproduction position is a link area, an ADIP demodulated circuit 101 demodulates a synchronized signal and address information from the reproduction signal of the disc. An average cycle detecting circuit 102 detects an average cycle value of the reproduction signal. A link signal output timing generating circuit 103 searches an internal link area as a candidate of the link area based on the synchronized signal and the average cycle value. An output judging circuit 104 regards the internal link area as the link area and outputs the timing signal when an address becomes a specific address.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention detects a link area which is a connection portion of an information signal recorded on a recordable optical disk or the like, and generates a timing signal indicating that a reproduction position is a link area. And a timing signal generation device for the same.

[0002]

2. Description of the Related Art Recently, a write-once optical disc, CD-R
(Compact Disc-Recordable
e), a rewritable optical disk CD-RW (Com
Recordable disc media such as MD (MiniDisc), which is a disc-rewritable disc (MD), and a magneto-optical disc, are used to edit and record music data and enjoy music outdoors using a portable player, as well as storage applications. There is also an increasing tendency to use it.

[0003] This is because the manufacturing cost of the optical disk is very low, and there is a sufficient storage capacity for recording music and video, and it is considered that the number of audiovisual devices using the optical disk will increase in the future.

When trying to record new data in such a recording area of an optical disk, the data may be accidentally deleted as a result of writing the data on the already recorded data. To ensure that there is no
In order to avoid the problem that the unrecorded area exists between consecutive data for a relatively long time, and as a result, a tracking error signal cannot be generated, the tracking servo is disengaged and the playback operation becomes impossible. A linking rule is defined by the document.

According to the MD linking rule, in the FDh sector of each cluster, which is the minimum unit of recording, 49 ± 10 EFM is obtained from the detected ADIP signal synchronization pattern.
It is stipulated that recording of the EFM signal must be started and ended within a specified time of a frame. The area for the specified time is called a “link area”. Each cluster is composed of a plurality of sectors, and in each sector, a specified time of 49 ± 10 EFM frames is an internal link area as a link area candidate from the synchronization pattern of the ADIP signal. Of the plurality of internal link areas that are candidates for such a link area, the link area corresponds to the specific address corresponding to the FDh sector. When such a link area is detected, a timing signal is output.

The "h" of FDh is a hexadecimal number (hex)
(Adecimal number) expression. ADIP is “Address In Pregr”
oove "and EFM is" Eightteent
o Fourteen Modulation.

[0007] More specifically, the link area is set to 5 from the 40th EFM frame after detecting the synchronization pattern of the FDh sector.
This is a 20 EFM frame area up to the ninth EFM frame, and overwriting of data up to a maximum of 20 EFM frames and occurrence of an unrecorded area are allowed. As described later, the FDh sector on the optical disk is equivalent to the FCh sector shifted by one sector in signal processing.

Normally, when data is reproduced from an optical disk, the EFM signal reproduced from the optical disk is converted into a binary signal by a comparator, and the binarized EFM signal is input to a PLL (Phase Locked Loop) to extract an extraction clock. Generate.

Then, the binarized EFM signal is punched out at the timing of the rising edge of the extracted clock, and the data string is subjected to EFM demodulation to restore information such as music.

When reproducing an optical disk recorded according to the above-described linking rule, no recording signal may be recorded in the link area, and in such a situation, how the signal reproduced from the optical disk behaves will be described. I do not understand. In the worst case, it is conceivable that the reproduced EFM signal oscillates in a high frequency band and the output signal of the comparator generates chattering, and as a result, the phase lock of the PLL is released.

Further, if the phase lock of the PLL is lost, the reproduction position moves again through the unrecorded link area to the area where the recording signal exists, and even if a normal reproduction signal is input from the optical disk. , Extra time is required until the PLL locks the phase, and it takes a considerable amount of time to stably demodulate data.

Therefore, conventionally, a timing signal indicating that the reproduction position is in the link area is generated, and if it is determined that the reproduction position is in the link area using the timing signal, a comparator for binarizing the reproduction signal is used. By suspending the operation and holding the output signal, chattering is prevented from occurring, and the phase lock of the PLL for extracting the clock of the binarized signal is protected.

When the PLL determines that the reproduction position is in the link area by using the timing signal, the PLL temporarily performs its operation, and performs a process of continuously outputting a signal maintaining the output cycle immediately before the hold. ing. That is, double protection processing is performed for the out-of-phase of the PLL.

Next, a conventional timing signal generating apparatus for an MD player will be described with reference to FIGS. 10, 11 and 12. FIG.

FIG. 10 is a block diagram of a timing signal generating device, which includes an ADIP demodulation circuit 1001 and a PLL.
1002 and link signal output timing generation circuit 10
3 and a link signal output circuit 1005 comprising an output determination circuit 1004.

FIG. 11 is a signal waveform diagram for explaining the operation of the timing signal generation device.
Bi-phase signal BPD which is a demodulated and binarized signal
T (a), BPCK (b) which is a clock extracted from BPDT (a) using PLL, and ADIP synchronization signal ADS indicating the position of the synchronization pattern of the ADIP signal.
Y (c), PCK (r) which is a clock extracted from the EFM signal using the PLL 1002, and 59EFM from the 39th EFM frame after the synchronization signal of each sector.
It shows an internal LINK (h ') indicating the area of the frame.

FIG. 12 is a signal waveform diagram for explaining the operation of the output determination circuit 1004. The address data (i) recorded on the disk and the synchronization signal ADS of the ADIP signal are shown.
Y (c), address data (j) obtained by demodulating a reproduction signal from the disc, an internal LINK (h ′) output from the link signal output timing generation circuit 1003, and a timing signal LIN output from the output determination circuit 1004
It is a signal waveform of K (h).

An ADIP demodulation circuit 1001 is a BPDT obtained by subjecting an ADIP signal reproduced from an MD to FM demodulation and binarizing the signal.
(A) is generated, and the BP is generated using the PLL provided therein.
The clock BPCK (b) is extracted from DT (a).

The frequency of the extracted clock BPCK (b) is about 6.3 kHz. At the rising edge of BPCK (b), BPDT (a) is punched out to extract a data string.

The synchronization pattern of the ADIP signal is such that the data string after FM demodulation is defined as "11101000" (shown) or "00010111". BPC
During the period up to the rising edge of K (b), the synchronization signal AD
SY (c) is set to logic H and output. For other periods, the synchronizing signal ADSY (c) outputs logic L.

Further, the ADIP demodulation circuit 1001 performs bi-phase demodulation of a data sequence following the synchronization pattern, thereby obtaining address data and an error detection code CRC (Cycle).
cRedundancy Check) is obtained, and whether there is an error in the demodulated address data is calculated using the CRC.

The address data obtained here is 16-bit cluster data, 8-bit sector data, a total of 24-bit data, and CRC 8-bit data.

The PLL 1002 extracts the clock PCK (r) from the binarized EFM signal and outputs the clock PCK (r) to the link signal timing generation circuit 1003. The frequency of the clock PCK (r) extracted here is about 4.3218 MHz.

One EFM frame is composed of 588 clocks P
CK (r) unit, and the frame synchronization signal at the head of each EFM frame is 4.3218 MHz / 5
It is repeated at a period of 88 = 7.35 kHz.

Link signal output timing generation circuit 100
At 3, the internal LINK (h ′) corresponding to the internal link area as a link area candidate is obtained from the ADSY (c) of the synchronization signal input from the ADIP demodulation circuit 1001 and the clock PCK (r) input from the PLL 1002. Generate.

Next, referring to FIG.
The process of generating (h ′) will be described.

Link signal output timing generation circuit 100
Numeral 3 has a counter therein, and when a synchronizing signal of the ADIP signal is detected, that is, the synchronizing signal ADSY (c)
Resets the counter to zero when goes to logic H. Thereafter, the counter is incremented at each rising edge of the clock PCK (r).

Therefore, if the value of the counter is “588 × 3”
9 ", it can be determined that the playback position of the disk has entered the 40th EFM frame from the detection of the synchronization signal, and when the value of the counter matches" 588 × 59 ", the playback position of the disk has been detected since the detection of the synchronization signal. It can be determined that the 60th EFM frame has entered, that is, the 59th EFM frame has ended.

Link signal output timing generation circuit 100
The internal LINK (h ′) corresponding to the internal link area as a link area candidate output by the E.3 is 40 EFM after detecting the synchronization pattern of each sector according to the value of the counter.
A logic H is set in a region from the frame to the 59 EFM frame, and a logic L is set in other regions.

According to the linking rule, the link area is defined only in the FDh sector among a plurality of sectors in each cluster, but this indicates the position on the disk, and indicates that the link area is actually being reproduced. When the reproduction signal is demodulated and the address is determined, the internal address data is updated at a timing after reading all the data of the FDh sector.

That is, as shown in FIG. 12, the address data (i) on the disk and the address data (j) in the ADIP demodulation circuit 1001 are shifted by one sector, and the reproduction position of the disk is linked. The link area defined by the rule is a sector where the address data (j) is the FCh of a specific address.

The output determination circuit 1004 has an internal LINK
(H ') and address data (j) are input. If the address data (j) is the specific address FCh, the internal LINK is used.
(H ′) is output as it is as the timing signal LINK (h), and the address data (j) is changed to the specific address FCh.
In other cases, the timing signal LINK (h) corresponding to the link area defined by the linking rule is output by outputting the timing signal LINK (h) as logic L.
Can be generated.

[0033]

In the above-mentioned timing signal generating apparatus according to the prior art, a clock is extracted from the EFM signal using a PLL, and the period of the extracted clock and E
The position of the link area is obtained by using the fact that the period ratio of the FM frame is fixed.

The PLL 1002 is designed to have a wide tracking band in order to make it difficult to lose the phase lock. The PLL 1002 also follows the disturbance of the EFM signal due to a defect such as dust or fingerprint on the disk surface, so that the phase lock is not released. However, during the period, the period of the extracted clock is disturbed, and the disturbance of the period is accumulated in the counter inside the link signal timing generation circuit 1003, and the position of the link area is shifted, or the specified time of the link area (20 EFM)
Frame), there is a problem that the area becomes longer or shorter.

As a power saving measure, recent optical disk reproducing apparatuses increase the transfer speed by rotating the optical disk at a speed higher than the normal speed, store a large amount of reproduced data in a buffer, and store the data in the buffer. When the remaining amount of data is sufficient, a technique has been introduced in which a reproduction operation from an optical disc is stopped to reduce power consumed by mechanical elements such as a spindle motor and an actuator.

Further, from the viewpoint of cost reduction,
CAV (Constant A)
With the use of an ordinary velocity (CL) (Constant Linear),
(Velocity) control circuit is being simplified.

One solution to the above-mentioned problem is to develop a signal processing circuit that supports a variable linear velocity.

However, in order to lock the phase in the ordinary PLL, the period of the input signal needs to be within a range of about ± 10% of the design target value. There was a problem that it could not cope with the change of.

As a countermeasure, a configuration having a plurality of PLLs to cope with various linear velocities is also possible.
Since the circuit scale is remarkably increased, an increase in cost cannot be avoided, and furthermore, there is a problem that the circuit design becomes complicated.

[0040]

The present invention for a timing signal generating device solves the above-mentioned problems by taking the following means.

The present invention is based on the following configuration. An information signal is recorded in a predetermined recording unit, and an apparatus for reproducing the information signal from a disk having a predetermined link area at a connection portion of the recording unit, wherein a reproduction position on the disk is the link area. A timing signal generating device for generating a timing signal shown in the figure, and further comprising an information demodulating means for demodulating a synchronization signal and address information from a reproduction signal of the disk as in the conventional technique.

Here, the predetermined recording unit may be, as a typical example, a cluster which is a group of a plurality of sectors. Typical examples of the information signal include an audio signal, a video signal, a mixed video / audio signal, and a data signal. The connection portion is an area for connecting one recording unit (cluster) to the next predetermined recording unit (cluster). However, these are merely examples, and the present invention does not need to be limited to such.

The timing signal generator of the present invention is characterized by further comprising the following elements in addition to the above-mentioned premise. That is, PL in the case of the prior art
As an alternative to L, an average period detecting means for detecting an average period value of the reproduction signal is provided. In the timing signal output means, based on the synchronization signal from the information demodulation means and the average period value from the average period detection means, determine an internal link area as a link area candidate,
When the address from the information demodulating means becomes a specific address, the internal link area is specified as a link area and the timing signal is output.

Here, in order to facilitate understanding, the correspondence relationship with the components in the embodiment described later is described for reference. The information demodulating means is an ADIP as an example.
The average period detection means corresponds to the average period detection circuit, and the timing signal output means corresponds to the link signal output circuit. The specific address corresponds to FCh as an example. However, these are merely examples, and the present invention does not need to be limited to such.

The operation of the above configuration of the present invention is as follows. In each sector in a cluster as a representative example of the recording unit, the information demodulating means demodulates a synchronization signal and address information from a reproduced signal. The average period detecting means detects an average period value of the reproduction signal from the disk. For example, an average period value can be obtained by reproducing an address signal for a tracking servo recorded in advance on a disk and counting a period between rising edges or falling edges thereof by a clock. In the case of an address signal in which a high-frequency component and a low-frequency component are mixed, an average period value can be obtained by using a low-pass filter. Since the average period value is equivalent to a low-frequency component, even if a defect such as dust or fingerprint is present on the disc, the influence thereof hardly spreads.

There is a certain correlation (proportional relation) between the recording frequency of the information signal recorded on the disk and the recording frequency of the address signal. This correlation does not change even when the linear velocity of the disk changes. That is, the frame length of the information signal can be easily obtained if the average period value of the reproduced address signal is obtained regardless of the linear velocity of the disk.

The timing signal output means obtains the position of the internal link area as a link area candidate in each sector based on the synchronization signal from the information demodulation means and the average cycle value from the average cycle detection means. For example, the number of frames corresponding to the reproduction signal from the disk is counted. For the measurement of one frame of the reproduction signal, the start point of the measurement is determined by the synchronization signal. One frame is counted when the clock count value becomes a predetermined constant multiple of the average period value. In each sector, from what frame to what frame the internal link area is from the synchronization signal is determined in advance by the disc standard. The timing signal output means counts the number of frames of the information signal to determine an internal link area for each sector. Such a plurality of internal link areas are link area candidates. In all the sectors constituting the cluster, an internal link area as such a link area candidate is obtained. The internal link area is determined at least until the regular link area is determined.

Further, the timing signal output means determines whether or not the address is a specific address on the basis of the address information from the information demodulation means. An internal link area corresponding to a specific address is specified as a link area, and a timing signal is generated and output in the link area.

As described above, by utilizing the average period value of the reproduction signal, even if the reproduction signal is degraded due to a defect such as dust or a fingerprint on the disk surface, a high link area can be obtained accurately. The timing signal can be generated with high accuracy, and the average period value has a constant correlation with the linear velocity, so it can respond to changes in linear velocity during playback without a significant increase or change in circuits. can do.

[0050]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be generally described.

According to a first aspect of the present invention, there is provided a timing signal generating apparatus for reproducing an information signal from a disk on which an information signal is recorded in a predetermined recording unit and which has a predetermined link area at a connection portion of the recording unit. A timing signal generation device that generates a timing signal indicating that a reproduction position on the disk is the link area,
Information demodulation means for demodulating a synchronization signal and address information from the reproduction signal of the disc; average period detection means for detecting an average period value of the reproduction signal; and a link area based on the synchronization signal and the average period value. Timing signal output means for obtaining an internal link area as a candidate and, when the address becomes a specific address, specifying the internal link area as a link area and outputting the timing signal.

The structure of the first invention corresponds to the structure of the above-mentioned [Means for Solving the Problems] section described in another form of expression. Means for Solving the Problems] is substantially the same as that described in the section. In other words, by using the average period value of the reproduction signal, even if the reproduction signal is deteriorated due to a defect such as dust or a fingerprint on the disk surface, the link area is accurately obtained and the timing signal is generated with high accuracy. Further, since the average period value has a constant correlation with the linear velocity, it is possible to cope with a change in the linear velocity at the time of reproduction without significantly increasing or changing the circuit.

According to a second aspect of the present invention, there is provided a timing signal generating apparatus according to the first aspect, wherein
The information demodulation means generates and outputs a status signal based on an internal signal, and the timing signal output means inhibits the output of the timing signal based on the status signal.

According to a third aspect of the present invention, there is provided a timing signal generating device according to the second aspect, wherein the information demodulating means outputs a status of a detection window for detecting a synchronization signal as the status signal. It is characterized by doing.

The operation according to the second and third aspects of the invention is as follows. If the information demodulation means cannot stably demodulate the address information due to defects such as dust and fingerprints on the disc, it is erroneously determined that the address is a specific address although it is not actually a specific address. May be lost. In such a case, a false timing signal is unexpectedly output, and a protection operation such as a hold may be erroneously performed in a comparator for binarizing the reproduced signal or a PLL for extracting a clock of the binarized signal. . As described above, when the information demodulation means cannot stably demodulate the address information, the information demodulation means outputs a status signal to the timing signal output means to prohibit the timing signal output means from outputting the timing signal. As a result, a false timing signal is prevented from being output unexpectedly, and an inconvenient situation in which a protection operation such as a hold of a comparator or a PLL occurs by mistake can be avoided.

According to a fourth aspect of the present invention, there is provided a timing signal generating device according to the second or third aspect, wherein the information demodulating means outputs an operation result of an error detection code as the status signal. It is characterized by doing.

This uses the operation result of the error detection code as the status signal instead of using the state of the detection window for detecting the synchronization signal as the status signal, and has the same effect as described above. That is, when the information demodulating means cannot stably demodulate the address information due to a defect such as dust or a fingerprint, a status signal which is an operation result of the error detection code is output and a false timing signal is unexpectedly output. It is possible to avoid the inconvenience that the protection operation such as the hold of the comparator or the PLL is erroneously performed.

According to a fifth aspect of the present invention, in the timing signal generating apparatus according to the first to fourth aspects, the information demodulation means outputs an operation result of an error detection code, and the timing signal output means has an internal An address register is provided, and the internal address register corrects an address output by the information demodulation means according to a result of the operation of the error detection code.

The operation of the fifth invention is as follows. If the above-described protection operation prohibition process is performed when the demodulation of the address information by the information demodulation means is continuously incorrect due to a defect such as dust or fingerprint on the disc, it is actually a specific address. in spite of,
There is a possibility that an erroneous determination is made that the address is not a specific address. In this case, a normal timing signal is not output to the normal link area, and if the link area is in an unrecorded state, a comparator for binarizing the reproduced signal or a clock of the binarized signal is extracted. PL
There is a possibility that an abnormal signal is sent to L and the PLL loses phase lock. As a countermeasure when the information demodulating means continuously erroneously demodulates the address, the information demodulating means is configured to output the operation result of the error detection code to the timing signal output means. The timing signal output means is provided with an internal address register for correcting the address from the information demodulation means based on the result of the operation of the error detection code. This internal address register uses the address from the information demodulation means as it is when the operation result of the error detection code is normal. In the case of abnormality, the previous address is updated and corrected by incrementing or the like, and a correct address is always secured. As a result, even if the address demodulation is continuously incorrect, the link area can always be detected accurately.

(Specific Embodiment) Hereinafter, a specific embodiment of the timing signal generator according to the present invention will be described in detail with reference to the drawings.

(Embodiment 1) FIG. 1 is a block diagram showing a configuration of a timing signal generator according to Embodiment 1 of the present invention.

As shown, the timing signal generator comprises an ADIP demodulation circuit 101, an average period detection circuit 10
2, a link signal output circuit 10 including a link signal output timing generation circuit 103 and an output determination circuit 104
5 is provided. That is, in the first embodiment, the average period detection circuit 102 is used instead of the PLL 1002 of the conventional timing signal generation device (FIG. 10).

FIG. 2 is a signal waveform diagram for explaining the operation of ADIP demodulation circuit 101, average period detection circuit 102, and link signal output timing generation circuit 103.
Bi-phase data BP obtained by binarizing a signal by FM demodulation
DT (a) and bi-phase data BPDT (a)
Clock BPCK (b) extracted from the above, a synchronization signal ADSY (c) which is a synchronization signal of the ADIP signal, and A
Average period value data (d), which is a value obtained by doubling the average period data of the DIP signal, an EFM frame measurement counter (e) inside the link signal output timing generation circuit 103, and an EFM frame detection signal (f) for LINK. , A signal waveform and data of an internal LINK counter (g).

FIG. 3 is a signal waveform diagram for explaining the operation of the link signal output timing generation circuit 103. The EFM frame detection signal for LINK (f), the counter for internal LINK (g), and the internal LINK signal (h ') are shown. It is a signal waveform and data.

ADIP demodulation circuit 101, output judgment circuit 1
04 performs the same operation as the timing signal generation device described in FIG. 10 in the prior art, and a description thereof will be omitted.

Therefore, here, the average period detecting circuit 1
02 and the link signal output timing generation circuit 103 will be described.

The average period detection circuit 102 is a circuit for calculating the average period of the ADIP signal reproduced from the disk, binarizes the input ADIP signal, and uses a clock between the rising edge or the falling edge of the signal. Count and the count value ADIP
The signal cycle data is updated as needed.

The ADIP signal has, as main frequency components, a high-frequency component that is a period deviation due to FM modulation and a low-frequency component that is a fluctuation of the FM carrier frequency. The period data of the ADIP signal is passed through a low-pass filter. By
Only the frequency component sufficiently lower than the high frequency component due to the period deviation is extracted, and data having only the low frequency component due to the fluctuation of the FM carrier frequency is output. This output data indicates the average period of the ADIP signal.
The data is equivalent to about 22.05 kHz which is the M carrier frequency.

Also, even if defects such as dust and fingerprints are present on the disk surface, the influence mainly affects the relatively high frequency components of the ADIP signal, and is removed by the low-pass filter. It is considered that there is almost no influence on the average period data.

Next, the link signal output timing generation circuit 103 will be described.

Link signal output timing generation circuit 103
Receives the synchronizing signal ADSY (c) and the average period value data (d) as inputs and outputs 59E from the 39 EFM frame of each sector.
An internal LINK (h ′) corresponding to an internal link area as a link area candidate indicating the area of the FM frame is generated.

Normally, the synchronization signal of the EFM frame is 7.3.
It has a period equivalent to 5 kHz, and the average period of the ADIP signal is equivalent to 22.05 kHz. 7.35 kHz
The ratio of z: 22.05 kHz = 1: 3 is constant, and is always kept constant even if the linear velocity of the disk changes.

In other words, the length of one EFM frame can be easily obtained if the average period of the ADIP signal is obtained regardless of the linear speed at which the disk is reproduced. The internal link area, which is a candidate for, can be easily obtained.

The operation for obtaining the length of one EFM frame from the average period of the ADIP signal will be described with reference to FIG.

Link signal output timing generation circuit 103
Has a frame counter (e), and resets the counter (e) to zero when a rising edge of the synchronization signal ADSY (c) is detected.

The counter (e) is incremented by a clock having the same frequency as that obtained by measuring the period data of the ADIP signal, and decrements the average period data of the ADIP signal by three.
The counter is reset to zero when it matches the multiplied average period value data (d).

At the moment when the counter (e) coincides with the average period value data (d) which is three times the average period data of the ADIP signal, the LINK frame detection signal (f) is set to logic H, and after a certain period of time, the logic is reset again. By setting to L, LIN
The polarity of the K frame detection signal (f) changes from logic L to logic H every EFM frame.

Further, the link signal output timing generation circuit 103 includes an internal LINK counter (g), and resets the counter (g) to an initial value “1” when detecting a rising edge of the synchronization signal ADSY (c). , L
When the rising edge of the INK frame detection signal (f) is detected, the counter (g) is incremented.

This count value indicates the number of the EFM from the synchronization pattern of the ADIP signal at the current playback position of the disk.
As shown in FIG. 3, the internal LINK counter (g) indicates that the frame is a frame from 40 d (“d” indicates a decimal number) to 59 d. LINK (h ')
Is set to logic H, the position of the internal link area as a link area candidate can be obtained.

After the link signal output timing generation circuit 103 obtains the internal LINK (h ') corresponding to the internal link area in this manner, the output of the link signal output circuit 105 is output in the same manner as in the prior art. The determination circuit 104 is a link signal output timing generation circuit 1
LINK (h ') from AD03 and ADIP demodulation circuit 1
12, a plurality of internal Ls sequentially output for each sector in the same manner as in FIG.
A timing signal LINK (h) is output at a timing corresponding to the specific address FCh among INK (h ').
That is, the position of the link area specified in the linking rule can be obtained.

As described above, according to the timing signal generating apparatus of the first embodiment, the average period detecting circuit 102 and the link signal output timing generating circuit 103 are provided, so that defects such as dust and fingerprints on the disk surface can be obtained. Can generate a timing signal that has almost no effect on the linear velocity, and generates a timing signal using the average period of the ADIP signal having a constant correlation with the linear velocity. A timing signal corresponding to a change in the linear velocity can be generated without any change.

(Embodiment 2) A timing signal generator according to Embodiment 2 of the present invention will be described with reference to FIGS.

FIG. 4 is a block diagram showing a configuration of a timing signal generator according to the second embodiment of the present invention.

As shown, the timing signal generator comprises an ADIP demodulation circuit 401 and an average period detection circuit 40.
2, a link signal output circuit 40 including a link signal output timing generation circuit 403 and an output determination circuit 404
5 is provided. In Embodiment 2, ADIP
The demodulation circuit 401 outputs a status signal indicating an internal state, and inputs the status signal to the output determination circuit 404.

FIG. 5 is a signal waveform diagram for explaining a detection window status which is a status signal, and includes a synchronizing signal (k) (hereinafter referred to as a detected synchronizing signal) indicating that a synchronizing pattern has been detected from the ADIP signal. A synchronization signal (m) to be interpolated when a synchronization pattern is not detected from the ADIP signal (hereinafter referred to as an interpolation synchronization signal), and a synchronization signal AD of the ADIP signal output from the ADIP demodulation circuit 401.
It is a signal waveform of SY (c) and the detection window status (n) which shows the state of the detection window.

FIG. 6 is a signal waveform diagram for explaining the operation of the timing signal generating device according to the second embodiment of the present invention. The address (i) on the disk, the synchronizing signal ADSY (c) of the ADIP signal, and the demodulated signal are demodulated. These are signal waveforms and data of address data (j), detection window status (n), and timing signal LINK (h).

The average period detection circuit 402 and the link signal output timing generation circuit 403 perform the same operations as those of the timing signal generation device of FIG. 1 according to the first embodiment of the present invention, and description thereof will be omitted. I do.

Therefore, here, the ADIP demodulation circuit 4
01, the output determination circuit 404 will be described.

The ADIP demodulation circuit 401 detects the synchronization pattern of the ADIP signal and outputs the synchronization signal ADSY
Although (c) is output, a circuit for protection processing is provided as a countermeasure when synchronization cannot be detected.

The ADIP sector has 84 clocks BPC.
K, and the synchronization pattern exists at the head of the ADIP sector, and includes eight clocks BPC.
It is recorded with a data length corresponding to K (see FIG. 11). That is, when a normal ADIP signal is demodulated, a synchronization pattern is always detected at a period of 84 BPCK.

According to this rule, even if the synchronization of the ADIP signal cannot be detected due to a defect such as dust or fingerprint on the disk surface, if the clock BPCK can be generated normally, the synchronization signal of the originally existing synchronization signal can be obtained. A synchronization signal can be inserted at the position. This signal is the interpolation synchronization signal (m).

Therefore, there are two types of synchronization signals inside the ADIP demodulation circuit 401. One of these two types of synchronization signals is selected and the synchronization signal ADSY (c) is selected.
Must be output, and the method used is to use a detection window.

The detection window indicates an allowable range of the time axis fluctuation of the detection synchronization signal (k) with respect to the interpolation synchronization signal (m). When the detection window is set, the detection synchronization signal (k)
Is detected inside the detection window, it is determined that the signal coincides with the interpolation synchronization signal (m), and the detection synchronization signal (k) is used as the synchronization signal ADSY (c) without using the interpolation synchronization signal (m). However, if the detection synchronization signal (k) is detected outside the detection window, it is determined that it does not match the interpolation synchronization signal (m), and the detected detection synchronization signal (k) is ignored. . If no detection window is set, all detection synchronization signals (k) are output as synchronization signals ADSY (c).

The interpolation synchronization signal (m) is a synchronization signal ADSY
(C) is output 84 BPCK after being output, and 8
If the synchronization signal ADSY (c) is further output before counting the four clocks BPCK, the counter is reset at that time and the clock BPCK is counted. The interpolation synchronization signal (m) is unconditionally the synchronization signal ADSY.
Output to (c).

Under the above conditions, the detected synchronizing signal (k) or the interpolated synchronizing signal (m) is used for synchronizing the synchronizing signal ADSY (c).
Generate

Next, how the detection window is set or not will be described with reference to FIG.

When the detection window is set, the purpose is to exclude a false synchronization signal generated at a position other than the original position due to a defect in the ADIP signal when the detection synchronization signal (k) is output stably. And For example, this is set when the detection synchronization signal (k) and the interpolation synchronization signal (m) match twice consecutively. That is, in the detection synchronization signal (k) of FIG. 5, since the third and fourth waveforms from the left coincide with the interpolation synchronization signal (m), the status signal is detected at the fourth timing. Window status (n) has been started.

On the other hand, when the detection window is not set, the purpose is to match the phases when the detection synchronization signal (k) and the interpolation synchronization signal (m) do not match at all. For example, when the detection synchronization signal (k) and the interpolation synchronization signal (m) do not match, the setting is released. That is, since there is no detection synchronization signal (k) at the fifth waveform from the left of the interpolation synchronization signal (m) in FIG. 5, the detection window status (n) falls at that timing. Note that, at the time of the second waveform from the left of the detection synchronization signal (k) in FIG. 5, the detection window status (n) is logic H at this stage. Synchronizing signal (k) is ignored.

Due to such a state transition, the ADIP demodulation circuit 401 causes the detection synchronization signal (k) and the interpolation synchronization signal (m)
The detection window is controlled so as to match as much as possible, and an operation is performed to stably perform data demodulation.

In other words, conversely, when the detection window is set, it means that the ADIP demodulation circuit 401 is stably demodulating the address data (j), and when the detection window is not set. , Stably address data (j)
Therefore, it is unlikely that the signal has been demodulated.

Since the details of the interpolation are not directly related to the present invention, further description is omitted.
In any case, when the ADIP demodulation circuit 401 determines that the address demodulation is normal and stable, the status signal is set to logic H, and when it is determined that the address demodulation is unstable, the status signal is set to logic H. L
Set to. FIG. 5 illustrates this.

Next, the output determination circuit 404 will be described.

The output decision circuit 404 operates in addition to the operation of the timing signal generator described in the first embodiment, and furthermore, the detection window status (n), which is a status signal input from the ADIP demodulation circuit 401, is set to logic H (the detection window is set). Is output), the timing signal LINK (h) is output. However, when the detection window status (n) is logic L (the setting of the detection window is released), the timing signal LINK (h) is output.
(H) is fixed to logic L and output.

By the way, in the case of the timing signal generation device according to the first embodiment, even when the setting of the detection window is released, that is, even when the possibility of stably demodulating data is low, the synchronization signal ADSY (c ), An address data (j), and a link area using the average cycle data of the ADIP signal, and outputs a timing signal LINK (h). Such an inconvenience will be described with reference to FIG.

As shown in FIG. 6, in the case of the first embodiment, even if the address demodulation is incorrectly performed with the specific address FCh as a result of the address demodulation in the sector that is not the specific address FCh, the sector indicated by the broken line in the sector does not. As a result, the comparator which binarizes the reproduction signal from the disk is held, and the normal demodulation operation cannot be temporarily performed.

However, in the case of the timing signal generation device according to the second embodiment of the present invention, it is determined from the detection window status (n) that stable data demodulation has not been performed, and the detection window status (n) is set to logic L. If there is a possibility that stable data demodulation may not be performed, the timing signal LINK (h) is forcibly fixed to the logic L and output, thereby avoiding the above-described problem.

As described above, according to the timing signal generation device of the second embodiment, the detection window status is output from the ADIP demodulation circuit and input to the output determination circuit, so that dust, fingerprints, etc. on the disk surface can be obtained. In addition to generating a timing signal that is not affected by the defect and that corresponds to a change in the linear velocity, it is possible to prevent the ADIP demodulation circuit from outputting a false timing signal LINK when demodulating data that is unstable. it can.

In the timing signal generator according to the second embodiment of the present invention, the status signal output from the ADIP demodulation circuit is used as the detection window status. Instead, for example, as shown in FIG. The result is output as a status, and if it is determined that there is no error in the address data check by the CRC, the CRC operation result is set to logic H. If it is determined that the error is an error, the CRC operation result is output to logic L and output to the output determination circuit. A similar operation can be obtained.

(Embodiment 3) A timing signal generator according to Embodiment 3 of the present invention will be described with reference to FIGS.

FIG. 8 is a block diagram showing a configuration of a timing signal generating device according to the third embodiment of the present invention.

As shown, the timing signal generator comprises an ADIP demodulation circuit 801 and an average period detection circuit 80.
2, and a link signal output circuit 806 including a link signal output timing generation circuit 803, an output determination circuit 804, and an address interpolation circuit 805. In the third embodiment, an address interpolation circuit 805 is provided in a link signal output circuit 806. The address interpolation circuit 805 is provided with an internal address register for correcting an address from the ADIP demodulation circuit 801.

FIG. 9 is a signal waveform diagram for explaining the operation of the timing signal generation device according to the third embodiment of the present invention. The address (i) on the disk, the synchronizing signal ADSY (c) of the ADIP signal, and the demodulated signal are shown. The signal waveform and data of the address data (j), the CRC calculation result (p), the interpolation address data (q), and the timing signal LINK (h).

ADIP demodulation circuit 801, average period detection circuit 802, link signal output timing generation circuit 803, and output determination circuit 804 perform the same operations as in the timing signal generation device of FIG. 1 according to the first embodiment of the present invention. Therefore, the description is omitted here.

Therefore, here, the address interpolation circuit 805
Will be described.

The address interpolation circuit 805 has an internal 8-bit address register (q) for address data. The CRC operation result (p) is generated at the timing of the rising edge of the input synchronization signal ADSY (c). In the case of logic H, the input address data (j) is substituted into the internal address register (q), and when the CRC operation result (p) is logic L, the data stored in the internal address register (q) is incremented. I do. The contents of the internal address register (q) will be referred to as interpolation address data.

However, since the address data is sector information, when the interpolation address data (q) is incremented, it is incremented by one continuously from 00h to 1Fh, but after 1Fh, FCh, FDh, and FE are added.
h and FFh, and the interpolation address data (q) returns to 00h in the next increment.

The address interpolation circuit 805 outputs the data of the interpolation address data (q) to the output judgment circuit 804.

Next, a detailed operation will be described with reference to FIG.

At first, the ADIP demodulation circuit 801
Address data (j) is normally transmitted from the signal to 1Dh, 1Eh
, And as a result, the CRC operation result (p) also outputs logic H.

Therefore, the interpolation address data (q) of the address interpolation circuit 805 matches the address data (j).

Subsequently, the ADIP signal is disturbed by defects such as dust and fingerprints on the disk surface, and the address data (j) to be demodulated is 1Fh, but is erroneously demodulated to 00h. (P) also becomes logic L, indicating that the address data (j) is erroneous.

However, since the CRC operation result (p) is logic L, the address interpolation circuit 805 does not substitute the address data (j) of 00h into the interpolation address data (q), but substitutes the immediately preceding interpolation address. 1Fh, which is a value obtained by incrementing 1Eh as data (q), is substituted.

The demodulated address data (j) is also different from the original sector data FCh (specific address) by 1
Ah is erroneously demodulated as Ah, and the CRC operation result (p) also becomes logic L. However, the address interpolation circuit 805 increments 1Fh held immediately before in the interpolation address data (q) by FCh (specific value). Address).

By the way, in the case of the timing signal generating device according to the second embodiment, the output judging circuit judges whether or not the address demodulation is normally performed based on the internal status of the ADIP demodulating circuit. If determined, the timing signal LINK is forcibly set to logic L irrespective of the address value of the sector, and protection processing is performed so as not to output the false timing signal LINK.

However, even when the reproduction position of the disc is in the normal link area, the timing signal LINK may be forcibly set to logic L due to the internal status of the ADIP demodulation circuit. If there is, there is a problem that an abnormal signal is input to a comparator for binarizing a signal reproduced from a disk or a PLL for extracting a clock of the binarized signal, and the PLL loses phase lock.

However, in the case of the timing signal generation device according to the third embodiment of the present invention, the address data is estimated together with the address data demodulated by the ADIP demodulation circuit using the result of the CRC operation, and interpolation address data is generated. Even when the address demodulation is unstable, the timing signal LINK can be output as a logical H to the original link area, and the above-described problem can be avoided.

As described above, by providing the link signal output circuit with the address interpolation circuit, it is possible to generate a timing signal corresponding to a change in linear velocity without being affected by defects such as dust and fingerprints on the disk surface. No, A
The DIP demodulation circuit can output a reliable timing signal even at the time of unstable data demodulation.

[0128]

According to the present invention for a timing signal generator, an internal link area as a link area candidate is determined based on a synchronization signal from an information demodulator and an average period value from an average period detector. When the address from the information demodulating means becomes a specific address, the internal link area is specified as a link area and a timing signal is output, so that there is a defect such as dust or fingerprint on the disk surface. Even if the reproduced signal is degraded, it is possible to accurately determine the link area and generate a timing signal with high accuracy, and since the average period value has a constant correlation with the linear velocity, a large circuit It is possible to cope with a change in the linear velocity at the time of reproduction without accompanying an increase or change in.

The reliability of the address demodulation is determined by using the status signal for grasping the internal state of the information demodulating means and the operation result of the error detection code. If it is determined that the demodulation is not performed normally, the link area is changed. Inhibiting the output of the timing signal shown in FIG. 2 prevents a false timing signal from being output unexpectedly, such as a comparator for binarizing the reproduced signal or a PLL hold for extracting a clock of the binarized signal. It is possible to avoid an inconvenient situation in which the protection operation is erroneously performed.

Further, in the internal address register of the timing signal output means, the address is corrected according to the result of the operation of the error detection code from the information demodulation means, and the correct address is always secured, so that the address demodulation is continuously erroneous. Even in this case, the link area can always be detected accurately.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a timing signal generation device according to a first embodiment of the present invention.

FIG. 2 is a signal waveform diagram illustrating operations of an ADIP demodulation circuit and a link signal output timing generation circuit according to the first embodiment of the present invention.

FIG. 3 is a signal waveform diagram illustrating an operation of the link signal output timing generation circuit according to the first embodiment of the present invention.

FIG. 4 is a block diagram illustrating a configuration of a timing signal generation device according to a second embodiment of the present invention.

FIG. 5 is a signal waveform diagram illustrating a detection window status which is a status signal according to the second embodiment of the present invention.

FIG. 6 is a signal waveform diagram illustrating an operation of the timing signal generation device according to the second embodiment of the present invention.

FIG. 7 is a signal waveform diagram illustrating an operation when a CRC operation result is used as a status according to the second embodiment of the present invention.

FIG. 8 is a block diagram illustrating a configuration of a timing signal generation device according to a third embodiment of the present invention.

FIG. 9 is a signal waveform diagram illustrating an operation of the timing signal generation device according to the third embodiment of the present invention.

FIG. 10 is a block diagram showing a configuration of a conventional timing signal generation device.

FIG. 11 shows a timing signal A in a conventional timing signal generation device.
Signal waveform diagram for explaining the operation of the DIP demodulation circuit and the link signal output timing generation circuit

FIG. 12 is a signal waveform diagram illustrating an output determination circuit in a conventional timing signal generation device.

[Explanation of symbols]

101, 401, 801, 1001 ADIP demodulation circuit 102, 402, 802 Average period detection circuit 103, 403, 803, 1003 Link signal output timing generation circuit 104, 404, 804, 1004 Output judgment circuit 105, 405, 806, 1005 Link Signal output circuit 805 Address interpolation circuit 1002 PLL

Claims (5)

[Claims] 1. An information signal is recorded in a predetermined recording unit,
And an apparatus for reproducing the information signal from a disk having a predetermined link area at a connection portion of the recording unit, wherein a timing signal generating apparatus generates a timing signal indicating that a reproduction position on the disk is the link area. Information demodulating means for demodulating a synchronization signal and address information from the reproduction signal of the disc; average period detection means for detecting an average period value of the reproduction signal; and, based on the synchronization signal and the average period value. Timing signal output means for determining an internal link area as a link area candidate and outputting the timing signal by specifying the internal link area as a link area when the address becomes a specific address. A timing signal generation device. 2. The information demodulation means generates and outputs a status signal based on an internal signal, and the timing signal output means inhibits output of the timing signal based on the status signal. The timing signal generator according to claim 1. 3. The timing signal generator according to claim 2, wherein the information demodulator outputs a state of a detection window for detecting a synchronization signal as the status signal. 4. The timing signal generating device according to claim 2, wherein said information demodulating means outputs an operation result of an error detection code as said status signal. 5. The information demodulation means outputs an operation result of an error detection code, the timing signal output means has an internal address register, and the internal address register operates according to the operation result of the error detection code. 5. The timing signal generating device according to claim 1, wherein an address output by said information demodulating means is corrected.