JPH0628774A - Device and method for controlling phase - Google Patents

Abstract

PURPOSE:To properly reproduce recording data by controlling a delay amt. in a sampling clock based on difference data in reproduced data sampled at the timing of before and behind of a preamble W signal. CONSTITUTION:When a clock mark is detected by a synchronous signal extracting part 12, a clock mark signal CM is outputted to a PLL circuit 14 at the timing, and the operation is repeated and the drawing of the phase synchronism of the sampling clock SP to the CM is ended. The clock SP phase- synchronized with the clock mark is phase fine adjusted by a variable delay line 16 further and the sampling clock SPa perfectly phase-synchronized with the clock SP at a data recording time is formed and the sampling operation of an analog/digital converter 11 is executed by the clock SPa. Further, a control amt. phase fine adjusting is calculated based on the difference in the digital reproduced data obtained by sampling with the clock SPa generated at the timing of before and behind of the regenerative signal of a recording pit in the preamble signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention controls the phase of a sampling clock of reproduced data by a sampling servo system in which servo patterns including clock marks are recorded on a storage medium at regular intervals, and sampling is performed by the sampling clock. The present invention relates to a phase control device that controls the delay time of a sampling clock based on the level of a reproduction signal.

[0002]

2. Description of the Related Art Conventionally, for example, in a magneto-optical disk device or the like, a sampling servo method is used to control the phase of a sampling clock of reproduced data, and at the time of data recording, a sample signal for measuring a phase delay amount is provided in a predetermined area. A "phase control circuit" disclosed in Japanese Patent Laid-Open No. 63-244448 has been proposed as a phase control device for recording and controlling the delay time of the sampling clock based on the reproduction level of the sample signal.

[0003]

However, in this conventional device, if there is a signal loss due to a defect in the medium or the like in the area where the sample signal is written, the sample signal cannot be obtained, so that data reading is performed. It becomes impossible to control the phase of the clock, and as a result, there arises a problem that errors occur frequently in read data.

The present invention has been made in order to eliminate the inconvenience of such a conventional apparatus, and a phase control apparatus capable of suppressing the effect of signal loss caused by a defect of a medium and reproducing recorded data appropriately. It is intended to be provided.

[0005]

According to the present invention, the phase of a sampling clock of reproduced data is controlled by a sampling servo system in which servo patterns including clock marks are recorded on a storage medium at regular intervals. In a phase control device for controlling the delay time of a sampling clock based on the level of a reproduced signal sampled, a preamble recording means for recording a preamble signal having a predetermined bit pattern in which recording pits do not appear around at least one clock before recording data. And a delay data generating means for outputting the set value of the delay time of the sampling clock, and a signal level difference of the reproduced data obtained at the timing of the sampling clock before and after the recording pit of the preamble signal is detected. When the differential data detecting means and the preamble signal are detected, the delay time setting value output from the delay data generating means is periodically switched to a predetermined plurality of steps to periodically switch the delay time of the sampling clock to set the delay time. When the values are the same, the average value of the plurality of difference data detected by the difference data detecting means is calculated, and the optimum delay amount of the sampling clock is calculated based on the average value of the difference data to detect the preamble signal. After that, a control means for setting the delay amount of the sampling clock to the calculated optimum delay amount is provided.

Further, the phase of the sampling clock of the reproduction data is controlled by the sampling servo system in which the servo patterns including the clock marks are recorded in the storage medium at regular intervals, and based on the level of the reproduction signal sampled by the sampling clock. In a phase control device for controlling the delay time of a sampling clock by means of preamble recording means for recording a preamble signal consisting of a predetermined bit pattern in which recording pits do not appear at least around one clock before recording data,
Delay data generating means for outputting the set value of the delay time of the sampling clock and difference data detecting means for detecting the difference in signal level of the reproduction data obtained at the timing of the sampling clock before and after the recording pit of the preamble signal. And when the preamble signal is detected, the delay time setting value output from the delay data generating means is periodically switched to a predetermined plurality of steps and in a unit of a predetermined number of sampling clocks to switch the delay time of the sampling clocks periodically. When the delay time setting value is the same value, the average value of the plurality of difference data detected by the difference data detecting means is calculated, and the optimum delay amount of the sampling clock is calculated based on the average value of the difference data, After detecting the preamble signal, the delay of the sampling clock Those having a control means for setting the amount of optimum delay amount calculated that.

Further, the phase of the sampling clock of the reproduced data is controlled by the sampling servo system in which the servo patterns including the clock marks are recorded in the storage medium at regular intervals, and the level of the reproduced signal sampled by the sampling clock is controlled. In a phase control device for controlling the delay time of a sampling clock by means of preamble recording means for recording a preamble signal consisting of a predetermined bit pattern in which recording pits do not appear at least around one clock before recording data,
Delay data generating means for outputting the set value of the delay time of the sampling clock and difference data detecting means for detecting the difference in signal level of the reproduction data obtained at the timing of the sampling clock before and after the recording pit of the preamble signal. A differential data discriminating means for discriminating that the size of the differential data outputted from the differential data detecting means is within a predetermined range, and a delay time setting value outputted from the delay data generating means at the time of detecting the preamble signal. And the delay time of the sampling clock is periodically switched, and the difference data detected by the difference data detection means is input when the difference data determination means outputs a judgment output. Then, the delay time setting value is the same based on the input difference data. Calculates the average value of the difference data of value,
An optimum delay amount of the sampling clock is calculated based on the average value of the difference data, and after the preamble signal is detected, the delay amount of the sampling clock is set to the calculated optimum delay amount. .

Further, the phase of the sampling clock of the reproduced data is controlled by the sampling servo system in which the servo patterns including the clock marks are recorded in the storage medium at regular intervals, and based on the level of the reproduced signal sampled by the sampling clock. In a phase control device for controlling the delay time of a sampling clock by means of preamble recording means for recording a preamble signal consisting of a predetermined bit pattern in which recording pits do not appear at least around one clock before recording data,
Delay data generating means for outputting the set value of the delay time of the sampling clock and difference data detecting means for detecting the difference in signal level of the reproduction data obtained at the timing of the sampling clock before and after the recording pit of the preamble signal. A differential data discriminating means for discriminating that the size of the differential data outputted from the differential data detecting means is within a predetermined range, and a delay time setting value outputted from the delay data generating means at the time of detecting the preamble signal. Is periodically switched in a predetermined plurality of steps and in a unit of a predetermined number of sampling clocks to cyclically switch the delay time of the sampling clock, and when the differential data determining means outputs a determination output, the differential data detecting means Enter the detected difference data and enter the difference Calculate the average value of the difference data when the delay time setting value is the same value based on the data, calculate the optimum delay amount of the sampling clock based on the average value of the difference data, after the preamble signal detection, the The control means is provided for setting the delay amount of the sampling clock to the calculated optimum delay amount.

Further, the phase of the sampling clock of the reproduced data is controlled by the sampling servo system in which the servo patterns including the clock marks are recorded on the storage medium at regular intervals, and based on the level of the reproduced signal sampled by the sampling clock. In a phase control device for controlling the delay time of a sampling clock by means of preamble recording means for recording a preamble signal consisting of a predetermined bit pattern in which recording pits do not appear at least around one clock before recording data,
Delay data generating means for outputting the set value of the delay time of the sampling clock and difference data detecting means for detecting the difference in signal level of the reproduction data obtained at the timing of the sampling clock before and after the recording pit of the preamble signal. When the preamble signal is detected, the delay time setting value output from the delay data generating means is cyclically switched to a plurality of predetermined steps to periodically switch the delay time of the sampling clock, and the delay time setting value is the same value. At the time of calculating the average value of the plurality of difference data detected by the difference data detecting means, calculating the optimum delay amount of the sampling clock based on the average value of the difference data, after the preamble signal detection, Set the delay amount of the sampling clock to the calculated optimum delay amount. Operation mode and the delay time setting value output from the delay data generating means at the time of detecting the preamble signal are sequentially switched to a predetermined plurality of steps and in a unit of a predetermined sampling clock, and the delay time of the sampling clock is periodically changed. While switching to, the average value of the plurality of difference data detected by the difference data detection means when the delay time setting value is the same value,
A second operation mode is provided in which an optimum delay amount of the sampling clock is calculated based on the average value of the difference data, and after the preamble signal is detected, the delay amount of the sampling clock is set to the calculated optimum delay amount. A timing control means and a mode setting means for selectively setting the operation mode of the timing control means to either the first operation mode or the second operation mode.

Further, the phase of the sampling clock of the reproduced data is controlled by the sampling servo system in which the servo patterns including the clock marks are recorded in the storage medium at regular intervals, and based on the level of the reproduced signal sampled by the sampling clock. In a phase control device for controlling the delay time of a sampling clock by means of preamble recording means for recording a preamble signal consisting of a predetermined bit pattern in which recording pits do not appear at least around one clock before recording data,
Delay data generating means for outputting the set value of the delay time of the sampling clock and difference data detecting means for detecting the difference in signal level of the reproduction data obtained at the timing of the sampling clock before and after the recording pit of the preamble signal. A differential data discriminating means for discriminating that the size of the differential data outputted from the differential data detecting means is within a predetermined range, and a delay time setting value outputted from the delay data generating means at the time of detecting the preamble signal. And the delay time of the sampling clock is periodically switched, and the difference data detected by the difference data detection means is input when the difference data determination means outputs a judgment output. Then, the delay time setting value is the same based on the input difference data. Calculates the average value of the difference data of value,
An optimum delay amount of the sampling clock is calculated based on the average value of the difference data, and after the preamble signal is detected, a first operation mode in which the delay amount of the sampling clock is set to the calculated optimum delay amount, and a preamble When a signal is detected, the delay time setting value output from the delay data generating means is cyclically switched in a predetermined plurality of steps and in a unit of a predetermined number of sampling clocks to cyclically switch the delay time of the sampling clocks, and the difference When there is a discrimination output from the data discrimination means, the difference data detected by the difference data detection means is input, and the average value of the difference data when the delay time set value is the same value is calculated based on the input difference data. The optimum delay of the sampling clock based on the average value of the difference data. After calculating the amount and detecting the preamble signal, the timing control means having a second operation mode for setting the delay amount of the sampling clock to the calculated optimum delay amount, and the operation mode of the timing control means are set to the above-mentioned A mode setting means for selectively setting either the first operation mode or the second operation mode is provided.

Further, the phase of the sampling clock of the reproduced data is controlled by the sampling servo system in which the servo patterns including the clock marks are recorded at a constant interval on the storage medium, and based on the level of the reproduced signal sampled by the sampling clock. In a phase control device for controlling the delay time of a sampling clock by means of preamble recording means for recording a preamble signal consisting of a predetermined bit pattern in which recording pits do not appear at least around one clock before recording data,
Delay data generating means for outputting the set value of the delay time of the sampling clock and difference data detecting means for detecting the difference in signal level of the reproduction data obtained at the timing of the sampling clock before and after the recording pit of the preamble signal. When the preamble signal is detected, the delay time setting value output from the delay data generating means is cyclically switched to a plurality of predetermined steps to periodically switch the delay time of the sampling clock, and the delay time setting value is the same value. At the time of calculating the average value of the plurality of difference data detected by the difference data detecting means, calculating the optimum delay amount of the sampling clock based on the average value of the difference data, after the preamble signal detection, Set the delay amount of the sampling clock to the calculated optimum delay amount. Operation mode and the delay time setting value output from the delay data generating means at the time of detecting the preamble signal are sequentially switched to a predetermined plurality of steps and in a unit of a predetermined sampling clock, and the delay time of the sampling clock is periodically changed. While switching to, the average value of the plurality of difference data detected by the difference data detection means when the delay time setting value is the same value,
A second operation mode is provided in which an optimum delay amount of the sampling clock is calculated based on the average value of the difference data, and after the preamble signal is detected, the delay amount of the sampling clock is set to the calculated optimum delay amount. Timing control means, error detection means for detecting a data error included in the reproduction data, and error detection when the data reproduction operation is executed with the timing control means set to the first operation mode. When the number of data errors detected by the means exceeds the predetermined range,
A mode control means for setting the timing control means to the second operation mode is provided.

Further, the phase of the sampling clock of the reproduction data is controlled by the sampling servo system in which the servo patterns including the clock marks are recorded on the storage medium at regular intervals, and the level of the reproduction signal sampled by the sampling clock is controlled. In a phase control device for controlling the delay time of a sampling clock by means of preamble recording means for recording a preamble signal consisting of a predetermined bit pattern in which recording pits do not appear at least around one clock before recording data,
Delay data generating means for outputting the set value of the delay time of the sampling clock and difference data detecting means for detecting the difference in signal level of the reproduction data obtained at the timing of the sampling clock before and after the recording pit of the preamble signal. A differential data discriminating means for discriminating that the size of the differential data outputted from the differential data detecting means is within a predetermined range, and a delay time setting value outputted from the delay data generating means at the time of detecting the preamble signal. And the delay time of the sampling clock is periodically switched, and the difference data detected by the difference data detection means is input when the difference data determination means outputs a judgment output. Then, the delay time setting value is the same based on the input difference data. Calculates the average value of the difference data of value,
An optimum delay amount of the sampling clock is calculated based on the average value of the difference data, and after the preamble signal is detected, a first operation mode in which the delay amount of the sampling clock is set to the calculated optimum delay amount, and a preamble When a signal is detected, the delay time setting value output from the delay data generating means is cyclically switched in a predetermined plurality of steps and in a unit of a predetermined number of sampling clocks to cyclically switch the delay time of the sampling clocks, and the difference When there is a discrimination output from the data discrimination means, the difference data detected by the difference data detection means is input, and the average value of the difference data when the delay time set value is the same value is calculated based on the input difference data. The optimum delay of the sampling clock based on the average value of the difference data. After the preamble signal is detected, the timing control means having a second operation mode for setting the delay amount of the sampling clock to the calculated optimum delay amount, and a data error included in the reproduction data. And the number of data errors detected by the error detecting means when the data reproducing operation is executed with the timing control means and the timing control means set to the first operation mode exceed the predetermined range. In some cases, a mode control means for setting the timing control means to the second operation mode is provided.

Further, the phase of the sampling clock of the reproduction data is controlled in sector units by a sampling servo system in which servo patterns including clock marks are recorded on the storage medium at regular intervals, and the reproduction signal sampled by the sampling clock is controlled. In a control method of a phase control device for controlling a delay time of a sampling clock based on a level, preamble recording means for recording a preamble signal consisting of a predetermined bit pattern in which a recording pit does not appear around at least one clock before recording data, Delay data generating means for outputting the set value of the delay time of the sampling clock, and detection of the difference in signal level of the reproduction data obtained at the timing of the sampling clock before and after the recording pit of the preamble signal And the differential data detecting means for detecting the preamble signal, the delay time setting value output from the delay data generating means is cyclically switched to a predetermined plurality of steps, and the delay time of the sampling clock is cyclically switched. When the set values are the same value, the average value of the plurality of difference data detected by the difference data detecting means is calculated, and the optimum delay amount of the sampling clock is calculated based on the average value of the difference data, and the preamble signal is calculated. After the detection, the first operation mode in which the delay amount of the sampling clock is set to the calculated optimum delay amount, and the delay time setting value output from the delay data generating means at the time of detecting the preamble signal are set in predetermined plural steps. In addition, the sampling clock is switched periodically in units of a predetermined number of sampling clocks. Of the plurality of difference data detected by the difference data detecting means when the delay time set value is the same value, and the sampling is performed based on the average value of the difference data. After the optimum delay amount of the clock is calculated and the preamble signal is detected, timing control means having a second operation mode for setting the delay amount of the sampling clock to the calculated optimum delay amount is included in the reproduction data. Error detection means for detecting a data error that is present, a predetermined data pattern is recorded in each sector of the recording medium when the recording medium is initialized, and the first operation mode is set in the timing control means for each sector. The number of data errors detected by the error detection means when setting When the operation mode 2 is set, the number of data errors detected by the error detection means is compared, the operation mode having the smaller number of data errors is discriminated for each sector, and the management information indicating the discrimination result is displayed. After recording on the recording medium and after initialization of the recording medium, the management information recorded on the recording medium is read out, and based on the content of the management information,
The operation mode set in the timing control means is selected for each sector.

Further, the phase of the sampling clock of the reproduction data is controlled by the sampling servo system in which the servo patterns including the clock marks are recorded in the storage medium at a constant interval, and based on the level of the reproduction signal sampled by the sampling clock. In a method of controlling a phase control device for controlling a delay time of a sampling clock by means of preamble recording means for recording a preamble signal consisting of a predetermined bit pattern in which recording pits do not appear around at least one clock before recording data, and the sampling clock. Delay data generating means for outputting the set value of the delay time of the preamble signal, and differential data for detecting the difference in the signal level of the reproduced data obtained at the timing of the sampling clock before and after the recording pit of the preamble signal. Outputting means, difference data determining means for determining whether the size of the difference data output from the difference data detecting means is within a predetermined range, and delay time output from the delay data generating means when the preamble signal is detected. The set value is cyclically switched to a predetermined plurality of steps to cyclically switch the delay time of the sampling clock, and the differential data detected by the differential data detecting means when there is a discriminative output from the differential data discriminating means. The average value of the difference data having the same delay time setting value is calculated based on the input difference data, and the optimum delay amount of the sampling clock is calculated based on the average value of the difference data. After the signal is detected, the delay amount of the sampling clock is set to the calculated optimum delay amount. When the operation mode and the preamble signal are detected, the delay time setting value output from the delay data generating means is periodically switched to a predetermined plurality of steps and in a unit of a predetermined sampling clock, and the delay time of the sampling clock is cyclically changed. At the same time as switching, the difference data detected by the difference data detecting means is inputted when there is a discrimination output from the difference data discriminating means, and the difference data when the delay time setting value is the same value based on the inputted difference data. Of the sampling clock is calculated based on the average value of the difference data, and after the preamble signal is detected, the delay amount of the sampling clock is set to the calculated optimum delay amount. Timing control means having two operation modes and included in the reproduction data. An error detecting means for detecting a data error which is present, a predetermined data pattern is recorded in each sector of the recording medium at the time of initialization of the recording medium, and the first operation mode is set to the timing control means for each sector. The number of data errors detected by the error detection means when set and the number of data errors detected by the error detection means when the second operation mode is set in the timing control means are compared, and For sectors,
The operation mode with the smaller number of data errors is discriminated, the management information indicating the discrimination result is recorded on the recording medium, and after the recording medium is initialized, the management information recorded on the recording medium is read out and the contents of the management information are read. Based on the above, the operation mode set in the timing control means is selected for each sector.

Further, the recording medium is divided into sectors having a predetermined data length, and each sector records an address area in which address data for identifying each sector is recorded in advance and arbitrary data. And a preamble area provided between the address area and the user data area for setting the preamble signal, the interval being set to be longer than the interval of the servo pattern. It is a thing.

[0016]

Therefore, since the delay amount of the sampling clock is controlled based on the difference data of the reproduction data sampled at the timing before and after the recording pit of the preamble signal, even if the recording pit cannot be obtained, the sampling clock The amount of delay can be controlled appropriately. Further, when a recording defect is generated in the recording area of the preamble signal and difference data with a large error is obtained, the difference data is not used, so that the delay amount of the sampling clock should be controlled more accurately. You can Further, since two operation modes for setting the delay amount of the sampling clock are provided and the operation mode in which the data error is less likely to occur is selected, the error occurrence at the time of data reproduction can be suppressed. Also,
By setting the length of the recording area of the preamble signal to be large, the operation at the time of adjusting the delay amount of the sampling clock can be executed more reliably.

[0017]

Embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

FIG. 1 shows a magneto-optical disk to which the embodiment of the present invention is applied.

Recording tracks TK are concentrically formed at a predetermined pitch on the magneto-optical disk 1 and are rotationally driven at a constant angular velocity.
As shown in, a 2-byte length servo area SBA for sampling servo and a 16-byte length data area DTA are alternately arranged.

In this servo area SBA, as shown in FIG.
, The pits P are arranged in a zigzag pattern so as to be in contact with the center LC of the recording track TK and line up on opposite sides.
A, PB, and a pit PC arranged so that its center coincides with the center LC of the recording track TK is recorded.

Then, the reproduction signal RF (see (b) in the figure)
Among them, a tracking error of a laser beam (not shown) of an optical pickup (not shown) is detected based on the reproduction level at the timing of the pits PA and PB, and the laser beam is recorded on the recording track TK based on the tracking error.
Tracking servo control is performed to match the center LC of the.

Further, the phase control of a sampling clock (described later) for sampling the reproduction signal RF is performed based on the reproduction level at the timing of the pit PC.

Further, a focusing error of the laser beam of the optical pickup is detected at an intermediate timing between the pits PA, PB and the pit PC, and based on the focusing error, the focusing of the laser beam is made to coincide with the recording track TK. Servo control is performed.

On the other hand, the data area DTA is divided into a predetermined number (for example, 32) of sectors of a predetermined length, and each sector is for identifying each sector as shown in FIG. 4 (a). Address area SSA (for example, 16 bytes) and a predetermined data length (for example, 6 bytes)
72 bytes) of user data area UDT.

Further, in the address area SSA, as shown in FIG. 2B, a sector mark SM (1 byte length) consisting of a predetermined bit pattern representing the beginning of a sector,
The sector address SA (1 byte length) in which the address for identifying the sector is set, the track address upper digit information TAH (1 byte length) indicating the upper digit of the track address for identifying the recording track TK, the track address Track address lower digit information TAL (1 byte length) representing the lower digit, data obtained by inverting the bit pattern of the track address lower digit information TAL (1's complement)
Track address lower order digit inversion information CTA to be set
L (1 byte length), track address upper digit information TAH
Track address upper digit inversion information CTAH (1 byte length) in which the data obtained by inverting the bit pattern of
Sector address inversion information CSA (1 byte length) in which data in which the bit pattern of the sector address SA is inverted is set, and a gap GAP of 1 byte length, and a preamble signal of 8 bytes length consisting of a predetermined bit pattern.

Here, the track address lower digit inversion information CTAL, the track address upper digit inversion information CTAH,
The sector address inversion information CSA is used to inspect the contents of the track address lower digit information TAL, the track address upper digit information TAH, and the sector address SA, respectively.

The bit pattern of the preamble signal is a data pattern in which the recording pits do not appear in the space of at least one clock before and after the recording pit. For example, as shown in FIG.
0100100100 ... ”. Also in this case,
As shown in FIG. 2B, the recording modulation rule in which pits are formed in data 1 is used. Further, the reproduction signal RF obtained by reproducing the recording pit of the preamble signal is
It changes as shown in FIG. In this case, 1
Five clocks correspond to one byte length.

Of the data recorded in the address area SSA, the sector mark SM and the sector address S
A, track address upper digit information TAH, track address lower digit information TAL, track address lower digit inversion information CTAL, track address upper digit inversion information CTA
H and the sector address inversion information CSA are recorded in the magneto-optical disk 1 in advance, and the preamble signal is recorded at the time of data recording, immediately before the recording data is written.
It is recorded using an optical pickup device used for recording data.

Since the preamble signal is continuously recorded in the same system as the data recording in this way, the sampling clock of the preamble signal and the sampling clock of the recording data have the same phase. The phase of the sampling clock is the pit P of the servo area SBA.
Phase control is performed with reference to the rising edge of the binarized signal (clock mark) obtained by binarizing the reproduction signal RF of C.

On the other hand, during data reproduction, basically, a sampling clock whose phase is controlled with reference to the rising edge of a binarized signal (clock mark) obtained by binarizing the reproduced signal RF of the pit PC in the servo area SBA is used. make use of,
The reproduction signal RF is sampled to form reproduction data.

Further, due to the state of the data recording system at the time of data recording, or the peak shift included in the generated clock mark, there is a phase error between the sampling clock at the time of data reproduction and the sampling clock at the time of data recording. Since it has occurred, further detecting the preamble signal and finely adjusting the phase of the sampling clock,
The sampling clock is set to the next user data area U
It is used when reproducing the DT data.

The fine adjustment of the phase of the sampling clock according to the present invention will be described with reference to FIGS. 6 and 7.

For example, a reproduction signal RF (FIG. 6) of a recording pit (see FIG. 6A) recorded on the recording track TK.
As shown in FIG. 6 (d), the sampling clock is delayed with respect to the timing of (b)).
The sample values FL1, FL2, ... Obtained by sampling the reproduction signal RF with the sampling clock generated immediately before the recording pit are obtained by sampling the reproduction signal RF with the sampling clock generated immediately after the recording pit. The values are larger than the sample values FR1, FR2, ...

Further, as shown in FIG. 6F, the sampling clock is advanced with respect to the timing of the reproduction signal RF (see FIG. 6E) of the recording pit recorded on the recording track TK. , Sample values FL1, FL2, obtained by sampling the reproduction signal RF with the sampling clock generated immediately before the recording pit.
Are smaller than the sample values FR1, FR2, ... Obtained by sampling the reproduction signal RF with the sampling clock generated at the timing immediately after the recording pit.

Further, as shown in FIG. 7 (d), the sampling clock coincides with the timing of the reproduction signal RF (see FIG. 7 (c)) of the recording pit recorded on the recording track TK. Then, with the sampling clock generated at the timing immediately before the recording pit, the reproduction signal RF
Sample values FL1, FL2, ...
And the sampled values FR1, FR2, ... Obtained by sampling the reproduction signal RF with the sampling clock generated immediately after the recording pit are equal.

Therefore, sample values FL1, FL2, ..., F obtained by sampling with the sampling clock generated before and after the timing of the reproduction signal RF of the recording pits.
By calculating the difference between the levels of R1, FR2, ..., It is possible to determine the phase error between the sampling clock during data recording and the sampling clock during data reproduction.

Therefore, in this embodiment, first, as shown in FIG.
As shown in (e) and FIG. 9, the sampling clock delay time is D1, D2, D3, D4 every 3 clock cycles in the odd byte of the preamble signal in the period in which the preamble signal is detected. It changes sequentially to D5, and changes to D5, D4, D3, D2, D1 in every three clock cycles at the even byte of the preamble signal.
Here, D1 <D2 <D3 <D4 <D5.

Then, for each sampling clock, the above-mentioned sample values FL1, FL2, ..., F
The level difference of R1, FR2, ... Is calculated, and the average value of the level differences at the same delay time is calculated.

Here, for example, as shown in FIG.
Consider a graph in which the horizontal axis is the delay time and the vertical axis is the difference data average value δ, and the relationship between the delay time actually detected and the difference data average value δ is plotted on this graph, and these plot points are passed. An approximate straight line LL is formed.

Considering the point where this approximate straight line LL intersects the horizontal axis, the value on the horizontal axis at this point is the delay time at which the difference data average value δ becomes 0, that is, the sampling clock at the time of data reproduction. It is equal to the delay time for setting the phase difference of the sampling clock during data recording to zero.

As described above, the delay time of the sampling clock is sequentially changed in the period in which the preamble signal is detected, and the sampling clock is obtained by sampling with the sampling clock generated before and after the timing of the reproduction signal RF of the recording pit. Sample values FL1, FL2, ..., FR1, F
The difference between the levels of R2, ... Is formed, the average value of the differences obtained at the same delay time is calculated, and the linear approximation operation is executed based on the delay time and the average value of the difference data. The phase fine adjustment value of the sampling clock can be obtained by calculating the delay time when the average value of the difference data matches 0 based on the result.

FIG. 11 shows a phase controller according to an embodiment of the present invention.

In the figure, a reproduction signal RF obtained from an optical pickup device (not shown) is applied to a binarization circuit 10 and an analog / digital converter 11.

The binarization circuit 10 binarizes the reproduction signal RF and converts it into a reproduction pulse signal DP, and the reproduction pulse signal DP is added to the synchronization signal extracting section 12.

The sync detection / extraction unit 12 outputs the reproduction pulse signal D
It is for detecting a synchronization signal such as a sector mark SM or a clock mark based on P. The detection mode is set by the timing generation unit 13, and the detection result is notified to the timing generation unit 13 and the clock mark is detected. When the clock is detected, the signal CM of the clock mark
Is added to a PLL (Phase Locked Loop) circuit 14.

The PLL circuit 14 generates a sampling clock SP having a predetermined frequency and synchronizes the phase of the sampling clock SP with the input signal CM. The sampling clock SP is supplied to the write controller 15. The sampling clock SP is added while being delayed by a predetermined amount via the variable delay line 16.
It is added to the analog / digital converter 11 as a.

The analog / digital converter 11 samples the reproduction signal RF input at the timing when the sampling clock SPa is added, and converts the value into predetermined digital reproduction data DF. Is added to the demodulator 17 and is also added to the difference detector 18.

The difference detecting section 18 includes a timing generating section 13
The reproduction signal R of the recording pit at the specified timing
Digital reproduction data DF obtained by sampling with the sampling clock SPa generated before and after the timing of F
The difference data Dd obtained thereby is added to the average value calculation unit 19.

The average value calculation unit 19 includes the timing generation unit 1
The difference detection unit 18 corresponding to the delay time designated by 3
The calculated difference data Dd is classified and stored, and the average value of the stored plurality of difference data Dd is calculated for each delay time. The calculation result is the difference average value data AV. It is added to the linear approximation calculation unit 20.

The linear approximation calculation unit 20 calculates the above-described approximate straight line LL based on the difference average value data AV, and the calculation result is added to the zero phase delay amount calculation unit 21.

The zero phase delay amount calculation unit 21 calculates the delay amount at which the value of the difference data Dd becomes 0 based on the calculation result of the linear approximation calculation unit 20, and the calculation result is the zero phase delay amount. The quantity command value Dz is added to one input end of the switch 22.

The delay amount generator 23 generates a delay amount command value Dx for designating the delay amount of the variable delay line 16, and
A delay amount command value Dx is generated by a command from the timing generation unit 13.
The value of the delay amount command value D
x is applied to the other input terminal of the switch 22.

The switch 22 selects either the zero phase delay amount command value Dz or the delay amount command value Dx according to a command from the timing generator 13, and the selected zero phase delay amount command value. Dz or delay amount command value D
x is added to the delay amount command value input terminal of the variable delay line 16.

The write controller 15 drives the semiconductor laser element 24, which is the light source of the optical pickup device, in synchronization with the sampling clock SP, based on the contents of the recording data WD. The read data RD is formed based on the digital reproduction data DF.

With the above configuration, when the reading of the sector data is started, the timing generator 13 sets the sync signal extractor 12 in the detection state of the sector mark SM.

As a result, when the optical pickup device reads the sector mark SM, the data pattern of the sector mark SM appears in the reproduction pulse signal DP output from the binarization circuit 10, whereby the sync signal extraction unit 12 is activated. The sector mark SM is detected, and a detection signal indicating that the sector mark SM has been detected is output from the synchronization signal extraction unit 12 to the timing generation unit 13.

As a result, the timing generation section 13 assumes the detection timing of the pit PC in the next servo area SBA from the detection timing of the sector mark SM, and outputs the detection window to the synchronization signal extraction section 12 at the estimated timing. Then, the operation of detecting the clock mark (pit PC) is performed. If the synchronization signal extraction unit 12 cannot detect the clock mark, the process returns to the detection of the sector mark SM again,
The sync signal extraction unit 12 is made to detect the clock mark again.

When the synchronizing signal extracting section 12 can detect the clock mark, the synchronizing signal extracting section 12 is instructed to output the clock mark signal CM.

As a result, after that, when the synchronization signal extraction unit 12 detects the clock mark, the clock mark signal CM is output to the PLL circuit 14 at that timing, and this operation is repeated, and the sampling clock S
The pulling of the phase synchronization with respect to the P clock mark signal CM is completed.

In this way, the sampling clock S
With P being phase-synchronized with the clock mark, the timing generator 13 switches from the preamble signal detection start timing to the preamble signal reading period T1 (a time corresponding to a length of 8 bytes), as shown in FIG. Bowl 2
The delay amount command value Dx is selected by 2 and the delay amount command value Dx generated from the delay amount generating section 23 is set to the time D1, D2, D3, D4, D5 at every three clock cycles in the odd byte of the preamble signal. The value sequentially changes to the corresponding value, and at the even-numbered byte of the preamble signal, the value sequentially changes to the value corresponding to the time D5, D4, D3, D2, D1 every three clock cycles. At the same time, the timing generator 1
3 starts the operation of the difference detection unit 18, and also notifies the average value calculation unit 19 of the set value of the delay time that changes sequentially.

Thereby, the sampling clock SP
Of the digital reproduction data DF obtained by sampling with the sampling clock SPa generated before and after the timing of the reproduction signal RF of the recording pit, with respect to each delay time. And the difference data Dd is sequentially output to the average value calculation unit 19.

In this way, the difference data Dd obtained during the preamble signal reading period T1 is input to the average value calculation unit 19, and the average value calculation unit 19 delays each of the delay times D1, D2 and D3. , D4, D5, the difference average value data AV is calculated, and the linear approximation calculation unit 2 is calculated.
It is output to 0. Then, as described above, the straight line approximation calculation unit 20 calculates the approximation straight line LL, and the zero phase delay amount calculation unit 21 calculates the zero phase delay amount using the calculation result. These average value calculation unit 19 and linear approximation calculation unit 20
And the calculation of the zero phase delay amount calculation unit 21 is at least the period T required to read the next servo area SBA.
It ends in 2.

After this period T2 has passed, the timing generation section 13 causes the switch 22 to select the zero phase delay amount command value Dz output from the zero phase delay amount calculation section 21, and the next data area DTA and thereafter. In the period T3 until the end of the sector, the state is maintained.

As a result, the zero phase delay amount command value Dz corresponding to the zero phase delay amount calculated by the zero phase delay amount calculating section 21 is added to the variable delay line 16, and is output from the variable delay line 16. Sampling clock SPa
Is the sampling clock SP delayed by a zero phase delay amount.

As a result, the reproduction signal RF for reading the user data area UDT is sampled at the sampling clock SPa having the same timing as the sampling clock for recording data, and the digital reproduction data DF is obtained.
Since it is added to the demodulator 17, the demodulator 17 can appropriately perform data demodulation, and the reproduced digital data RD is appropriately formed.

As described above, in this embodiment, the sampling clock SP phase-synchronized with the clock mark is
Further, the phase is finely adjusted by the variable delay line 16 to form the sampling clock SPa which is completely in phase with the sampling clock at the time of data recording, and the sampling operation of the analog / digital converter 11 is performed by the sampling clock SPa. Therefore, the reproduced digital data RD can be properly obtained.

Further, a control amount for finely adjusting the phase is calculated based on the difference between a plurality of digital reproduction data DF obtained by sampling with the sampling clock SPa generated before and after the timing of the reproduction signal RF of the recording pit of the preamble signal. Therefore, even if the recording pit of the preamble signal is missing due to a defect of the magneto-optical disk 1 or the like, the control amount can be appropriately calculated.

Further, in this case, when the control amount for finely adjusting the phase is calculated, the delay time of the sampling clock SPa is set to the time D1, D2, D3, D4 for every three clock periods in the odd byte of the preamble signal. In addition to the change in the order of D5, in the even bytes of the preamble signal, the time changes in the order of D5, D4, D3, D2, and D1, so that the recording pits of the preamble signal are cyclic due to a medium defect or the like. Difference data can be obtained even in a missing state, and a highly reliable control amount can be obtained.

Now, for example, as shown in FIGS. 13A to 13E, the medium defect M is recorded in the recording area of the preamble signal.
When M occurs and an error occurs in the sample value FL5 of the reproduction signal RF of the fifth recording pit of the preamble signal, the difference data between the sample value FL5 of the fifth recording pit and the sample value FR5 is different. The value becomes significantly larger than the difference data, and as a result, as shown in FIG. 14, the value of the difference data average value δ5 ′ corresponding to the delay time D5 becomes the other delay times D1, D2, D3, D4. It is higher than the corresponding difference data average value.

For this reason, in this case, the approximate straight line formed by the method of the embodiment of FIG. 10 described above becomes the straight line LL1 'shown in FIG. 14, and this approximate straight line LL1'.
The zero phase delay amount calculated using
The error ED is included in comparison with the zero phase delay amount calculated based on the approximate straight line LL1 formed using the difference data average value δ5 obtained when there is no difference.

As described above, in the case where the medium defect MM is generated in the recording area of the preamble signal and the sample value of the reproduction signal RF of the recording pit of the preamble signal has an error, the method of the above-described embodiment is effective. An error may occur in the obtained zero phase delay amount.

In order to avoid such a situation, for example, an appropriate range of the difference data of the sample values is defined (± δt), and when calculating the approximate straight line, the difference data that exceeds the appropriate range should not be used. do it.

FIG. 15 shows a phase control device according to another embodiment of the present invention. In addition, in FIG.
The same parts and corresponding parts are designated by the same reference numerals.

In the figure, the difference detecting section 18 obtains digital reproduction data DF obtained by sampling with the sampling clock SPa generated before and after the timing of the reproduction signal RF of the recording pit at the timing designated by the timing generation section 13. Of the difference data Dd obtained by the calculation of the difference data Dd.
And the difference discriminator 25.

The difference discriminating section 25 discriminates whether or not the difference data Dd is within a predetermined proper range. When it is discriminated that the difference data Dd is within a predetermined proper range, the discrimination signal SS is outputted. It outputs to the average value calculation unit 19.

The average value calculation unit 19 executes the above-described average value calculation operation based on the difference data Dd input while the determination signal SS is being output from the difference determination unit 25 to obtain the difference average value data AV. The calculation result is added to the linear approximation calculation unit 20.

With the above configuration, when starting the reading of the sector data, the timing generation section 13 first causes the synchronization signal extraction section 12 to detect the sector mark SM and then the clock mark (pit) as in the above-described embodiment. (PC) to perform a pull-in operation of phase synchronization with the clock mark signal CM of the sampling clock SP.

In this way, the sampling clock S
With P being phase-synchronized with the clock mark, the timing generator 13 causes the switch 22 to select the delay amount command value Dx during the preamble signal reading period T1 from the detection start timing of the preamble signal, and also generates the delay amount. The delay amount command value Dx generated from the unit 23 is sequentially changed to a value corresponding to the time D1, D2, D3, D4, D5 every three clock cycles in the odd byte of the preamble signal, and in the even byte of the preamble signal. The value sequentially changes to a value corresponding to the time D5, D4, D3, D2, D1 every three clock cycles. At the same time, the timing generation unit 13 starts the operation of the difference detection unit 18 and also notifies the average value calculation unit 19 of the set value of the delay time that changes sequentially.

Thereby, the sampling clock SP
Of the digital reproduction data DF obtained by sampling with the sampling clock SPa generated before and after the timing of the reproduction signal RF of the recording pit, with respect to each delay time. And the difference data Dd is sequentially output to the average value calculation unit 19. Further, the difference determination unit 25
Among the difference data Dd, for the data determined to be within the appropriate range, the determination signal SS is set to the average value calculation unit 1
Output to 9.

Of the difference data Dd obtained during the preamble signal reading period T1 in this manner, only the difference data Dd determined by the difference discriminating unit 25 to be within the appropriate range is sent to the average value calculating unit 19. This average value calculation unit 1
According to 9, each delay time D1, D2, D3, D
The difference average value data AV regarding 4 and D5 is calculated and output to the linear approximation calculation unit 20. Then, as described above, the straight line approximation calculation unit 20 calculates the approximation straight line LL, and the zero phase delay amount calculation unit 21 calculates the zero phase delay amount using the calculation result. The calculations of the average value calculation unit 19, the linear approximation calculation unit 20, and the zero phase delay amount calculation unit 21 are completed at least during the period T2 required to read the next servo area SBA.

After this period T2 has passed, the timing generator 13 causes the switch 22 to select the zero phase delay amount command value Dz output from the zero phase delay amount calculator 21, and after the next data area DTA, In the period T3 until the end of the sector, the state is maintained.

As a result, the zero phase delay amount command value Dz corresponding to the zero phase delay amount calculated by the zero phase delay amount calculation unit 21 is added to the variable delay line 16 and is output from the variable delay line 16. Sampling clock SPa
Is the sampling clock SP delayed by a zero phase delay amount.

As a result, the reproduction signal RF for reading the user data area UDT is sampled at the sampling clock SPa having the same timing as the sampling clock for recording data, and the digital reproduction data DF is sampled.
Since it is added to the demodulator 17, the demodulator 17 can appropriately perform data demodulation, and the reproduced digital data RD is appropriately formed.

In this way, in this embodiment, the sampling clock SP phase-synchronized with the clock mark is
Further, the phase is finely adjusted by the variable delay line 16 to form the sampling clock SPa which is completely in phase with the sampling clock at the time of data recording, and the sampling operation of the analog / digital converter 11 is performed by the sampling clock SPa. Therefore, it is possible to obtain appropriate reproduction digital data RD.

Further, the difference discriminating unit 25 limits the difference data Dd used by the average value calculating unit 19 to calculate the difference average value data AV to a value within a predetermined proper range. Even if the recording area of the preamble signal has a defect and the sample value of the reproduction data DF includes an error (noise), the zero phase delay amount is accurately calculated without being affected by the noise. be able to.

In the above-described embodiment, the delay time of the sampling clock is sequentially changed for each sampling clock in the period in which the preamble signal is detected. However, the sampling clock delay time is changed for each predetermined sampling clock (for example, 1 byte ( = 15 clocks)), the delay time of the sampling clock can be changed so that the average value of the difference data obtained when the sampling clocks having the same delay time are generated is used.

That is, as shown in FIGS. 16, 17 and 18, the delay time of the sampling clock is set to D1 during the first byte of the period in which the preamble signal is detected, and the second byte is set. Of the sampling clock, the delay time of the sampling clock is set to D2, the delay time of the sampling clock is set to D3 during the third byte, and the delay time of the sampling clock is set to D4 during the fourth byte. The sampling clock delay time is set to D4 during the fifth byte period, the sampling clock delay time is set to D3 during the sixth byte period, and the sampling clock delay time is set during the seventh byte period. The sampling clock delay time is set to D1 during the eighth byte.

Then, sample values FL11, FL12, ..., F obtained by sampling with the sampling clock generated before and after the timing of the reproduction signal RF of the recording pits.
L21, FL22, ..., FL31, FL32, ..., FL
41, FL42, ... And sample values FR11, F
R12, ..., FR21, FR22, ..., FR31, FR
32, ..., FR41, FR42, ..., while forming a level difference, calculate an average value of the differences obtained at the same delay time, and perform a linear approximation operation based on the delay time and the difference data average value. The phase fine adjustment value of the sampling clock can be obtained by executing the calculation and further calculating the delay time when the difference data average value matches 0 based on the calculation result.

FIG. 19 shows a phase controller according to still another embodiment of the present invention. In FIG.
The same parts and corresponding parts are designated by the same reference numerals.

In the figure, the average value calculating unit 26 is arranged so that the difference detecting unit 1 operates during a period corresponding to 1 byte of the preamble signal.
8 calculates the average value of the plurality of difference data Dd, stores the average value as the byte period average value corresponding to the delay time designated by the timing generation unit 13, and ends the detection of the preamble signal. Then, for each delay time, the average value of the stored byte period average values is calculated, and the calculation result is added to the linear approximation calculation unit 20 as difference average value data AV.

With the above configuration, when starting the reading of the sector data, the timing generation section 13 sets the synchronization signal extraction section 12 in the detection state of the sector mark SM.

As a result, when the optical pickup device reads the sector mark SM, the data pattern of the sector mark SM appears in the reproduction pulse signal DP output from the binarization circuit 10, whereby the sync signal extraction unit 12 is activated. The sector mark SM is detected, and a detection signal indicating that the sector mark SM has been detected is output from the synchronization signal extraction unit 12 to the timing generation unit 13.

As a result, the timing generation section 13 assumes the detection timing of the pit PC in the next servo area SBA from the detection timing of the sector mark SM, and outputs the detection window to the synchronization signal extraction section 12 at the estimated timing. Then, the operation of detecting the clock mark (pit PC) is performed. If the synchronization signal extraction unit 12 cannot detect the clock mark, the process returns to the detection of the sector mark SM again,
Similarly, the sync signal extraction unit 12 is caused to detect the clock mark.

When the synchronizing signal extracting section 12 can detect the clock mark, the synchronizing signal extracting section 12 is instructed to output the clock mark signal CM.

As a result, after that, when the synchronization signal extraction unit 12 detects a clock mark, the clock mark signal CM is output to the PLL circuit 14 at that timing, and this operation is repeated, and the sampling clock S
The pulling of the phase synchronization with respect to the P clock mark signal CM is completed.

In this way, the sampling clock S
With P being phase-synchronized with the clock mark, the timing generator 13 causes the switch 22 to select the delay amount command value Dx during the preamble signal reading period T1 (see FIG. 12) from the preamble signal detection start timing. At the same time, the delay amount command value Dx generated from the delay amount generating unit 23 is set to the delay time D1, D2, D at the timing when a period corresponding to 1 byte of the preamble signal elapses.
The values are sequentially changed to values corresponding to 3, D4, D4, D3, D2, D1.

At the same time, the timing generator 13
The operation of the difference detection unit 18 is started, and at the timing of changing the delay amount command value Dx, the calculation cycle of the average value calculation unit 26 is started in a state of notifying the delay time at that time.

Thereby, the sampling clock SP
Of the sampling clock SP generated before and after the timing of the reproduction signal RF of the recording pit, which sequentially and periodically changes for each period corresponding to 1 byte of the preamble signal.
The difference of the digital reproduction data DF obtained by sampling at a is calculated by the difference detection unit 18, and the average value calculation unit 26 calculates the byte period average value of the difference data Dd at each delay time for each 1-byte period. To be done.

In this way, during the preamble signal reading period T1, the average value calculating section 26 calculates the byte period average value, finishes reading the preamble signal, and
When two sets of byte period average values for the respective delay times are obtained, the average value calculation unit 26 calculates the average value of the byte period average values of the delay times, respectively, and the difference average value data AV thus obtained is As described above, it is used for the calculation of the approximate straight line LL in the linear approximation calculation unit 20, and the zero phase delay amount calculation unit 21 calculates the zero phase delay amount using the calculation result. The calculations of the linear approximation calculation unit 20 and the zero phase delay amount calculation unit 21 are completed at least during the period T2 required to read the next servo area SBA.

After this period T2 has passed, the timing generation section 13 causes the switch 22 to select the zero phase delay amount command value Dz output from the zero phase delay amount calculation section 21, and the next data area DTA and thereafter. In the period T3 until the end of the sector, the state is maintained.

As a result, similarly to the above-described embodiment, the zero phase delay amount command value Dz corresponding to the zero phase delay amount calculated by the zero phase delay amount calculating section 21 becomes the variable delay line 16
Therefore, the sampling clock SPa output from the variable delay line 16 is
Is delayed by zero phase delay amount, resulting in
The demodulator 17 can appropriately perform data demodulation,
The reproduced digital data RD is appropriately formed.

In this way, in the present embodiment, the delay amount of the sampling clock is sequentially and cyclically changed for each period corresponding to 1 byte of the preamble signal to form the difference data. It is possible to obtain a large number of samples of the difference data, and as a result, it is possible to further reduce the influence of the medium defect or the like included in the difference average value data AV output from the average value calculation unit 26.

FIG. 20 shows a phase controller according to still another embodiment of the present invention. In the figure, the same parts as those in FIG. 15 and corresponding parts are designated by the same reference numerals.

In the figure, the average value calculation unit 27 is provided with the difference data D output from the difference detection unit 18 on condition that the determination signal SS is output from the difference determination unit 25.
d is input, and an average value of a plurality of difference data Dd input in a period corresponding to 1 byte of the preamble signal is calculated, and the average value is converted into bytes in accordance with the delay time designated by the timing generation unit 13. When the preamble signal is detected, the average value of the stored byte period average values is calculated for each delay time. The calculation result is the difference average value data AV. Is added to the linear approximation calculation unit 20.

With the above configuration, when the reading of the sector data is started, the timing generation section 13 sets the synchronization signal extraction section 12 in the detection state of the sector mark SM.

As a result, when the optical pickup device reads the sector mark SM, the data pattern of the sector mark SM appears in the reproduction pulse signal DP output from the binarization circuit 10, whereby the sync signal extraction unit 12 is activated. The sector mark SM is detected, and a detection signal indicating that the sector mark SM has been detected is output from the synchronization signal extraction unit 12 to the timing generation unit 13.

As a result, the timing generation unit 13 assumes the detection timing of the pit PC of the next servo area SBA from the detection timing of the sector mark SM, and outputs the detection window to the synchronization signal extraction unit 12 at the estimated timing. Then, the operation of detecting the clock mark (pit PC) is performed. If the synchronization signal extraction unit 12 cannot detect the clock mark, the process returns to the detection of the sector mark SM again,
Similarly, the sync signal extraction unit 12 is caused to detect the clock mark.

When the synchronizing signal extracting section 12 can detect the clock mark, the synchronizing signal extracting section 12 is instructed to output the clock mark signal CM.

As a result, after that, when the synchronization signal extraction unit 12 detects the clock mark, the clock mark signal CM is output to the PLL circuit 14 at that timing, and this operation is repeated, and the sampling clock S
The pulling of the phase synchronization with respect to the P clock mark signal CM is completed.

In this way, the sampling clock S
With P being phase-synchronized with the clock mark, the timing generator 13 causes the switch 22 to select the delay amount command value Dx during the preamble signal reading period T1 (see FIG. 12) from the preamble signal detection start timing. At the same time, the delay amount command value Dx generated from the delay amount generating unit 23 is set to the delay time D1, D2, D at the timing when a period corresponding to 1 byte of the preamble signal elapses.
The values are sequentially changed to values corresponding to 3, D4, D4, D3, D2, D1.

At the same time, the timing generator 13
The operation of the difference detection unit 18 is started, and at the timing of changing the delay amount command value Dx, the calculation cycle of the average value calculation unit 27 is started in a state of notifying the delay time at that time.

Thereby, the sampling clock SP
The amount of delay of the recording pits changes cyclically at intervals corresponding to one byte of the preamble signal, and the reproduction signal RF
Sampling clock S generated before and after the timing
The difference of the digital reproduction data DF obtained by sampling at Pa is calculated by the difference detection unit 18, and the difference data D
It is output as d to the difference determination unit 25 and the average value calculation unit 27. Further, the difference discriminating unit 25 determines the difference data Dd.
Among them, the determination signal SS is output to the average value calculation unit 27 for those determined to be within the appropriate range.

Of the difference data Dd obtained during the preamble signal reading period T1 in this way, only the difference data Dd that the difference discriminating unit 25 has determined to be within a proper range is sent to the average value calculating unit 27. The average value calculator 27 calculates the byte period average value of the difference data Dd at each delay time for each input 1-byte period.

In this way, in the preamble signal reading period T1, the average value calculating section 27 calculates the byte period average value, finishes reading the preamble signal, and
When two sets of byte period average values relating to the respective delay times are obtained, the average value calculating unit 27 calculates the average value of the byte period average values of the respective delay times, and the difference average value data AV thus obtained is As described above, it is used for the calculation of the approximate straight line LL in the linear approximation calculation unit 20, and the zero phase delay amount calculation unit 21 calculates the zero phase delay amount using the calculation result. The calculations of the linear approximation calculation unit 20 and the zero phase delay amount calculation unit 21 are completed at least during the period T2 required to read the next servo area SBA.

After this period T2 has passed, the timing generator 13 causes the switch 22 to select the zero phase delay amount command value Dz output from the zero phase delay amount calculator 21, and after the next data area DTA, In the period T3 until the end of the sector, the state is maintained.

As a result, as in the above-described embodiment, the zero phase delay amount command value Dz corresponding to the zero phase delay amount calculated by the zero phase delay amount calculating section 21 becomes the variable delay line 16
Therefore, the sampling clock SPa output from the variable delay line 16 is
Is delayed by zero phase delay amount, resulting in
The demodulator 17 can appropriately perform data demodulation,
The reproduced digital data RD is appropriately formed.

In this way, in this embodiment, the delay amount of the sampling clock is sequentially and cyclically changed for each period corresponding to 1 byte of the preamble signal to form the difference data. It is possible to obtain a large number of samples of the difference data of, and as a result, it is possible to further reduce the influence of a medium defect or the like included in the difference average value data AV output from the average value calculation unit 27.

Further, the difference discriminating unit 25 limits the difference data Dd used by the average value calculating unit 27 to calculate the difference average value data AV to a value within a predetermined proper range. Even if the recording area of the preamble signal has a defect and the sample value of the reproduction data DF includes an error (noise), the zero phase delay amount is accurately calculated without being affected by the noise. be able to.

By the way, in the above-mentioned embodiment, the length of the preamble signal is set to 8 bytes, but if this preamble signal is made longer, the number of samples at the time of adjustment for setting the delay amount of the sampling clock is changed. Since it can be increased, the influence of the medium defect can be further reduced, and as a result, the zero phase delay amount can be calculated more accurately.

In that case, as shown in FIG. 21, a 16-byte data area DTA is arranged between the address area SSA and the user data area UDT, and a 16-byte preamble signal is recorded in this data area DTA. It is recommended to set the preamble area PAA. In this case, a 24-byte preamble signal can be used together with the 8-bit preamble signal recorded in the address area SSA.

FIG. 22 shows a phase controller according to still another embodiment of the present invention. In the figure,
The same parts as those in FIG. 11 and the corresponding parts are designated by the same reference numerals.

In the figure, the average value calculation unit 30 calculates the difference data Dd output from the difference detection unit 18 by 2
An average value calculation process of various kinds of operation modes is executed, and the operation mode is set by the timing generation unit 13. The first operation mode executed by the average value calculation unit 30 is the difference data D calculated by the difference detection unit 18 corresponding to the delay time designated by the timing generation unit 13.
This is an operation mode in which d is classified and stored, and an average value of a plurality of stored difference data Dd is calculated for each delay time. In the second operation mode, the difference detection unit 1 operates during the period corresponding to 1 byte of the preamble signal.
8 calculates the average value of the plurality of difference data Dd, stores the average value as the byte period average value corresponding to the delay time designated by the timing generation unit 13, and ends the detection of the preamble signal. Then, for each delay time, it is an operation mode for calculating the average value of the stored byte period average values. Further, the calculation result of the average value calculation unit 30 is added to the linear approximation calculation unit 20 as difference average value data AV.

The error detection / correction circuit 31 refers to the error correction code included in the reproduced digital data RD output from the demodulation unit 17, detects the reproduced digital data RD in which an error has occurred, and detects the error. Predetermined error correction processing is applied to the reproduced digital data RD, and the processing result is output to the next-stage device as corrected reproduced digital data RDc. Also, 1
When the processing for the sector is completed, an error signal ED representing the number of data errors (the number of error bits) included in the sector is formed and output.

The error detection / correction circuit 31 outputs the input reproduction digital data RD as it is to the corrected reproduction digital data RDc for the portion in which no data error is detected, and includes it in the reproduction digital data RD. When the number of data errors exceeding the capability of the error correction code is detected, the data errors are notified to the outside.

The mode decision section 32 decides the operation mode of this phase control device based on the error signal ED output from the error correction circuit 31, and the mode signal MOD representing the decision result is the timing generation signal. Part 13
Has been added to.

With the above configuration, the mode determining section 32 selects the first operation mode as the initial state and outputs the mode signal MOD representing the first operation mode to the timing generating section 13.
Output to.

In this state, the following first operation mode is executed. That is, when the reading of the sector data is started, the timing generation unit 13 sets the synchronization signal extraction unit 12 in the detection state of the sector mark SM.

As a result, when the optical pickup device reads the sector mark SM, the data pattern of the sector mark SM appears in the reproduction pulse signal DP output from the binarization circuit 10, whereby the sync signal extraction section 12 is caused. The sector mark SM is detected, and a detection signal indicating that the sector mark SM has been detected is output from the synchronization signal extraction unit 12 to the timing generation unit 13.

As a result, the timing generation section 13 assumes the detection timing of the pit PC of the next servo area SBA from the detection timing of the sector mark SM, and outputs the detection window to the synchronization signal extraction section 12 at the estimated timing. Then, the operation of detecting the clock mark (pit PC) is performed. If the synchronization signal extraction unit 12 cannot detect the clock mark, the process returns to the detection of the sector mark SM again,
The sync signal extraction unit 12 is made to detect the clock mark again.

When the synchronizing signal extracting section 12 can detect the clock mark, the synchronizing signal extracting section 12 is instructed to output the clock mark signal CM.

As a result, after that, when the synchronization signal extraction unit 12 detects a clock mark, the clock mark signal CM is output to the PLL circuit 14 at that timing, and this operation is repeated, and the sampling clock S
The pulling of the phase synchronization with respect to the P clock mark signal CM is completed.

In this way, the sampling clock S
With P being phase-synchronized with the clock mark, the timing generator 13 causes the switch 22 to set the delay amount command value Dx during the preamble signal reading period T1 from the preamble signal detection start timing, as shown in FIG. The delay amount command value Dx generated by the delay amount generation unit 23 is set to the time D1, D2, D3, D4, D for every three clock cycles in the odd byte of the preamble signal.
The value sequentially changes to a value corresponding to 5, and at the even bytes of the preamble signal, the time D5, D4, D
The value sequentially changes to a value corresponding to 3, D2, D1. At the same time, the timing generation unit 13 starts the operation of the difference detection unit 18, and also notifies the average value calculation unit 30 of the set value of the delay time that sequentially changes in the state in which the first operation mode is designated. .

As a result, the sampling clock SP
Of the digital reproduction data DF obtained by sampling with the sampling clock SPa generated before and after the timing of the reproduction signal RF of the recording pit, with respect to each delay time. And the difference data Dd is sequentially output to the average value calculation unit 30.

In this way, the difference data Dd obtained during the preamble signal reading period T1 is input to the average value calculating section 30, and the average value calculating section 30 causes the respective delay times D1, D2 and D3. , D4, D5, the difference average value data AV is calculated, and the linear approximation calculation unit 2 is calculated.
It is output to 0. Then, as described above, the straight line approximation calculation unit 20 calculates the approximation straight line LL, and the zero phase delay amount calculation unit 21 calculates the zero phase delay amount using the calculation result. These average value calculation unit 19 and linear approximation calculation unit 20
And the calculation of the zero phase delay amount calculation unit 21 is at least the period T required to read the next servo area SBA.
It ends in 2.

After this period T2 has passed, the timing generator 13 causes the switch 22 to select the zero phase delay amount command value Dz output from the zero phase delay amount calculator 21, and after the next data area DTA, In the period T3 until the end of the sector, the state is maintained.

As a result, the zero phase delay amount command value Dz corresponding to the zero phase delay amount calculated by the zero phase delay amount calculating section 21 is added to the variable delay line 16 and is output from the variable delay line 16. Sampling clock SPa
Is the sampling clock SP delayed by a zero phase delay amount.

As a result, the reproduction signal RF for reading the user data area UDT is sampled at the sampling clock SPa having the same timing as the sampling clock for recording data, and the digital reproduction data DF is obtained.
Since it is added to the demodulator 17, the demodulator 17 can appropriately perform data demodulation, and the reproduced digital data RD is appropriately formed.

Further, when the reproduced digital data RD is input, the error detection / correction circuit 31 executes a predetermined error correction process, and the corrected reproduced digital data RD of the processing result.
c is sequentially output. When the processing for one sector at that time ends, the error detection / correction circuit 31 outputs an error signal ED representing the data error detected at that time to the mode determination unit 32.

As a result, the mode determination section 32 checks, based on the error signal ED, whether the data error at that time is less than or equal to a predetermined value, and if it is determined that the data error is less than or equal to the predetermined value, , Holds the contents of the mode signal MOD at that time. On the other hand, when it is determined that the data error exceeds the predetermined value, the mode determination unit 32
Changes the value of the mode signal MOD to a value corresponding to the other operation mode (in this case, the second operation mode).

As a result, the timing generator 13 executes the following second operation mode for the next sector. However, when it is detected that the value of the mode signal MOD has been changed in the middle of the next sector, the timing generation unit 13 executes the above-described first operation mode for the next sector and then The second operating mode is started from the sector.

In the second operation mode, when the sector data reading is started, the timing generator 13
The sync signal extraction unit 12 is set to the detection state of the sector mark SM.

As a result, when the optical pickup device reads the sector mark SM, the data pattern of the sector mark SM appears in the reproduction pulse signal DP output from the binarization circuit 10, whereby the sync signal extraction section 12 is caused. The sector mark SM is detected, and a detection signal indicating that the sector mark SM has been detected is output from the synchronization signal extraction unit 12 to the timing generation unit 13.

As a result, the timing generation section 13 assumes the detection timing of the pit PC in the next servo area SBA from the detection timing of the sector mark SM, and outputs the detection window to the synchronization signal extraction section 12 at the estimated timing. Then, the operation of detecting the clock mark (pit PC) is performed. If the synchronization signal extraction unit 12 cannot detect the clock mark, the process returns to the detection of the sector mark SM again,
Similarly, the sync signal extraction unit 12 is caused to detect the clock mark.

When the synchronizing signal extracting section 12 can detect the clock mark, the synchronizing signal extracting section 12 is instructed to output the clock mark signal CM.

As a result, after that, when the synchronization signal extraction unit 12 detects the clock mark, the clock mark signal CM is output to the PLL circuit 14 at that timing, and this operation is repeated, and the sampling clock S
The pulling of the phase synchronization with respect to the P clock mark signal CM is completed.

In this way, the sampling clock S
With P being phase-synchronized with the clock mark, the timing generator 13 causes the switch 22 to select the delay amount command value Dx during the preamble signal reading period T1 (see FIG. 12) from the preamble signal detection start timing. At the same time, the delay amount command value Dx generated from the delay amount generating unit 23 is set to the delay time D1, D2, D at the timing when a period corresponding to 1 byte of the preamble signal elapses.
The values are sequentially changed to values corresponding to 3, D4, D4, D3, D2, D1.

At the same time, the timing generator 13
When the operation of the difference detection unit 18 is started and the delay amount command value Dx is changed, the second operation mode is designated as the operation mode, and the delay time at that time is notified and the average value is calculated. The calculation cycle of the unit 30 is started.

Accordingly, the sampling clock SP
Of the sampling clock SP generated before and after the timing of the reproduction signal RF of the recording pit, which sequentially and periodically changes for each period corresponding to 1 byte of the preamble signal.
The difference of the digital reproduction data DF obtained by sampling in a is calculated by the difference detection unit 18, and the average value calculation unit 30 calculates the average byte period of the difference data Dd at each delay time for each 1-byte period. To be done.

In this way, in the preamble signal reading period T1, the average value calculating section 30 calculates the byte period average value, finishes reading the preamble signal, and
When two sets of byte period average values relating to the respective delay times are obtained, the average value calculating unit 30 calculates the average value of the byte period average values of the respective delay times, and the difference average value data AV thus obtained is As described above, it is used for the calculation of the approximate straight line LL in the linear approximation calculation unit 20, and the zero phase delay amount calculation unit 21 calculates the zero phase delay amount using the calculation result. The calculations of the linear approximation calculation unit 20 and the zero phase delay amount calculation unit 21 are completed at least during the period T2 required to read the next servo area SBA.

After this period T2 has passed, the timing generation section 13 causes the switch 22 to select the zero phase delay amount command value Dz output from the zero phase delay amount calculation section 21, and after the next data area DTA, In the period T3 until the end of the sector, the state is maintained.

As a result, similarly to the above, the zero phase delay amount command value Dz corresponding to the zero phase delay amount calculated by the zero phase delay amount calculating section 21 is added to the variable delay line 16, so that the variable delay line The sampling clock SPa output from 16 is obtained by delaying the sampling clock SP by a zero phase delay amount, and as a result, the demodulator 17
Can appropriately perform data demodulation, and the reproduced digital data RD is appropriately formed.

Further, when the reproduced digital data RD is input, the error detection / correction circuit 31 executes a predetermined error correction process, and the corrected reproduced digital data RD of the processing result.
c is sequentially output. When the processing for one sector at that time ends, the error detection / correction circuit 31 outputs an error signal ED representing the data error detected at that time to the mode determination unit 32.

As a result, the mode determination section 32 checks, based on the error signal ED, whether the data error at that time is less than or equal to a predetermined value, and if it is determined that the data error is less than or equal to the predetermined value, , Holds the contents of the mode signal MOD at that time. On the other hand, when it is determined that the data error exceeds the predetermined value, the mode determination unit 32
Changes the value of the mode signal MOD to a value corresponding to the other operation mode (in this case, the first operation mode).

As a result, the timing generator 13 executes the above-mentioned first operation mode for the next sector. However, when it is detected that the value of the mode signal MOD has been changed in the middle of the next sector, the timing generation unit 13 executes the above-described second operation mode for the next sector and then The first operating mode is started from the sector.

As described above, in this embodiment, at the start of the operation, the phase adjustment operation is executed in the first operation mode, and many data errors are included in the reproduced digital data RD obtained after the phase adjustment of the sampling clock SPa. In this case, since the second operation mode is selected at the time of reproducing the next sector, the sampling clock SP is selected according to the state of the magneto-optical disk 1 used at that time.
The phase adjustment operation of a can be performed, and the zero phase delay amount can be set more appropriately.

FIG. 23 shows a phase controller according to still another embodiment of the present invention. In the figure,
The same parts as those in FIG. 22 and the corresponding parts are designated by the same reference numerals.

In the figure, the average value calculation unit 33 calculates the difference data Dd output from the difference detection unit 18 by 2
An average value calculation process of various kinds of operation modes is executed, and the operation mode is set by the timing generation unit 13. Further, the first operation mode executed by the average value calculation unit 33 corresponds to the delay time designated by the timing generation unit 13 and corresponds to the difference input when the difference determination unit 25 outputs the determination signal SS. This is an operation mode in which the data Dd is classified and stored, and the average value of the stored plurality of difference data Dd is calculated for each delay time. In addition, the second operation mode executed by the average value calculation unit 33 inputs the difference data Dd output from the difference detection unit 18 on condition that the determination signal SS is output from the difference determination unit 25, The average value of the plurality of difference data Dd input during the period corresponding to 1 byte of the preamble signal is calculated, and the average value is stored as the byte period average value corresponding to the delay time designated by the timing generation unit 13. Then, when the detection of the preamble signal is completed, it is an operation mode in which the average value of the stored byte period average values is calculated for each delay time.
Further, the calculation result of the average value calculation unit 33 is added to the linear approximation calculation unit 20 as the difference average value data AV.

With the above configuration, the mode determining section 32 selects the first operation mode as the initial state and outputs the mode signal MOD representing the first operation mode to the timing generating section 13.
Output to.

In this state, the following first operation mode is executed. That is, when the reading of the sector data is started, the timing generation section 13 first causes the synchronization signal extraction section 12 to detect the sector mark SM, and performs the clock mark (pit PC) detection operation, as in the above-described embodiment. Then, the pull-in operation of the phase synchronization with the clock mark signal CM of the sampling clock SP is performed.

In this way, the sampling clock S
With P being phase-synchronized with the clock mark, the timing generator 13 causes the switch 22 to select the delay amount command value Dx during the preamble signal reading period T1 from the detection start timing of the preamble signal, and also generates the delay amount. The delay amount command value Dx generated from the unit 23 is sequentially changed to a value corresponding to the time D1, D2, D3, D4, D5 every three clock cycles in the odd byte of the preamble signal, and in the even byte of the preamble signal. The value sequentially changes to a value corresponding to the time D5, D4, D3, D2, D1 every three clock cycles. At the same time, the timing generation unit 13 starts the operation of the difference detection unit 18 and, in the state where the first operation mode is designated to the average value calculation unit 33,
Notify the set value of the delay time that changes sequentially.

Accordingly, the sampling clock SP
Of the digital reproduction data DF obtained by sampling with the sampling clock SPa generated before and after the timing of the reproduction signal RF of the recording pit, with respect to each delay time. And the difference data Dd is sequentially output to the average value calculator 33. Further, the difference determination unit 25
For the difference data Dd that is determined to be a value within the appropriate range, the determination signal SS is set to the average value calculation unit 3
Output 3

Of the difference data Dd obtained during the preamble signal reading period T1 in this way, only the difference data Dd determined by the difference discriminating unit 25 to be within the proper range is sent to the average value calculating unit 33. The average value calculation unit 3
3, the delay time D1, D2, D3, D
The difference average value data AV regarding 4 and D5 is calculated and output to the linear approximation calculation unit 20. Then, as described above, the straight line approximation calculation unit 20 calculates the approximation straight line LL, and the zero phase delay amount calculation unit 21 calculates the zero phase delay amount using the calculation result. The calculations of the average value calculation unit 33, the linear approximation calculation unit 20, and the zero phase delay amount calculation unit 21 are completed at least during the period T2 required to read the next servo area SBA.

After this period T2 has passed, the timing generator 13 causes the switch 22 to select the zero phase delay amount command value Dz output from the zero phase delay amount calculator 21. In the period T3 until the end of the sector, the state is maintained.

As a result, the zero phase delay amount command value Dz corresponding to the zero phase delay amount calculated by the zero phase delay amount calculating section 21 is added to the variable delay line 16, and is output from the variable delay line 16. Sampling clock SPa
Is the sampling clock SP delayed by a zero phase delay amount.

As a result, the reproduction signal RF for reading the user data area UDT is sampled at the sampling clock SPa at the same timing as the sampling clock for recording data, and the digital reproduction data DF is obtained.
Since it is added to the demodulator 17, the demodulator 17 can appropriately perform data demodulation, and the reproduced digital data RD is appropriately formed.

Further, when the reproduced digital data RD is input, the error detection / correction circuit 31 executes a predetermined error correction process, and the corrected reproduced digital data RD of the processing result.
c is sequentially output. When the processing for one sector at that time ends, the error detection / correction circuit 31 outputs an error signal ED representing the data error detected at that time to the mode determination unit 32.

As a result, the mode determination unit 32 checks, based on the error signal ED, whether the data error at that time is less than or equal to the predetermined value, and if it is determined that the data error is less than or equal to the predetermined value, , Holds the contents of the mode signal MOD at that time. On the other hand, when it is determined that the data error exceeds the predetermined value, the mode determination unit 32
Changes the value of the mode signal MOD to a value corresponding to the other operation mode (in this case, the second operation mode).

As a result, the timing generator 13 executes the following second operation mode for the next sector. However, when it is detected that the value of the mode signal MOD has been changed in the middle of the next sector, the timing generation unit 13 executes the above-described first operation mode for the next sector and then The second operating mode is started from the sector.

In the second operation mode, when the sector data reading is started, the timing generator 13
The sync signal extraction unit 12 is set to the detection state of the sector mark SM.

As a result, when the optical pickup device reads the sector mark SM, the data pattern of the sector mark SM appears in the reproduction pulse signal DP output from the binarization circuit 10, whereby the sync signal extraction section 12 is caused. The sector mark SM is detected, and a detection signal indicating that the sector mark SM has been detected is output from the synchronization signal extraction unit 12 to the timing generation unit 13.

As a result, the timing generation section 13 assumes the detection timing of the pit PC in the next servo area SBA from the detection timing of the sector mark SM, and outputs the detection window to the synchronization signal extraction section 12 at the estimated timing. Then, the operation of detecting the clock mark (pit PC) is performed. If the synchronization signal extraction unit 12 cannot detect the clock mark, the process returns to the detection of the sector mark SM again,
Similarly, the sync signal extraction unit 12 is caused to detect the clock mark.

When the synchronizing signal extracting section 12 can detect the clock mark, the synchronizing signal extracting section 12 is instructed to output the clock mark signal CM.

As a result, after that, when the synchronization signal extraction unit 12 detects a clock mark, the clock mark signal CM is output to the PLL circuit 14 at that timing, and this operation is repeated, and the sampling clock S
The pulling of the phase synchronization with respect to the P clock mark signal CM is completed.

In this way, the sampling clock S
With P being phase-synchronized with the clock mark, the timing generator 13 causes the switch 22 to select the delay amount command value Dx during the preamble signal reading period T1 (see FIG. 12) from the preamble signal detection start timing. At the same time, the delay amount command value Dx generated from the delay amount generating unit 23 is set to the delay time D1, D2, D at the timing when a period corresponding to 1 byte of the preamble signal elapses.
The values are sequentially changed to values corresponding to 3, D4, D4, D3, D2, D1.

At the same time, the timing generator 13
The operation of the difference detection unit 18 is started, and at the timing of changing the delay amount command value Dx, the calculation cycle of the average value calculation unit 33 is started in a state of notifying the delay time at that time.

Thereby, the sampling clock SP
The amount of delay of the recording pits changes cyclically at intervals corresponding to one byte of the preamble signal, and the reproduction signal RF
Sampling clock S generated before and after the timing
The difference of the digital reproduction data DF obtained by sampling at Pa is calculated by the difference detection unit 18, and the difference data D
It is output as d to the difference determination unit 25 and the average value calculation unit 33. Further, the difference discriminating unit 25 determines the difference data Dd.
Among them, the determination signal SS is output to the average value calculation unit 33 for the one determined to be within the appropriate range.

Of the difference data Dd obtained during the preamble signal reading period T1 in this way, only the difference data Dd determined by the difference discriminating unit 25 to fall within the proper range is sent to the average value calculating unit 33. The average value calculator 27 calculates the byte period average value of the difference data Dd at each delay time for each input 1-byte period.

In this way, in the preamble signal reading period T1, the average value calculating section 33 calculates the byte period average value and finishes reading the preamble signal.
When two sets of byte period average values for the respective delay times are obtained, the average value calculation unit 33 calculates the average value of the byte period average values of the delay times, respectively, and the difference average value data AV thus obtained is As described above, it is used for the calculation of the approximate straight line LL in the linear approximation calculation unit 20, and the zero phase delay amount calculation unit 21 calculates the zero phase delay amount using the calculation result. The calculations of the linear approximation calculation unit 20 and the zero phase delay amount calculation unit 21 are completed at least during the period T2 required to read the next servo area SBA.

After this period T2 has passed, the timing generator 13 causes the switch 22 to select the zero phase delay amount command value Dz output from the zero phase delay amount calculator 21, and after the next data area DTA, In the period T3 until the end of the sector, the state is maintained.

As a result, the zero phase delay amount command value Dz corresponding to the zero phase delay amount calculated by the zero phase delay amount calculating section 21 is changed to the variable delay line 16 as in the above embodiment.
Therefore, the sampling clock SPa output from the variable delay line 16 is
Is delayed by zero phase delay amount, resulting in
The demodulator 17 can appropriately perform data demodulation,
The reproduced digital data RD is appropriately formed.

Further, when the reproduced digital data RD is input, the error detection / correction circuit 31 executes a predetermined error correction process, and the corrected reproduced digital data RD of the processing result.
c is sequentially output. When the processing for one sector at that time ends, the error detection / correction circuit 31 outputs an error signal ED representing the data error detected at that time to the mode determination unit 32.

Thus, the mode determination section 32 checks whether the data error at that time is less than or equal to the predetermined value based on the error signal ED, and if it is determined that the data error is less than or equal to the predetermined value, , Holds the contents of the mode signal MOD at that time. On the other hand, when it is determined that the data error exceeds the predetermined value, the mode determination unit 32
Changes the value of the mode signal MOD to a value corresponding to the other operation mode (in this case, the first operation mode).

As a result, the timing generator 13 executes the above-mentioned first operation mode for the next sector. However, when it is detected that the value of the mode signal MOD has been changed in the middle of the next sector, the timing generation unit 13 executes the above-described second operation mode for the next sector and then The first operating mode is started from the sector.

As described above, in this embodiment, at the start of the operation, the phase adjustment operation is executed in the first operation mode, and there are many data errors contained in the reproduced digital data RD obtained after the phase adjustment of the sampling clock SPa. In this case, since the second operation mode is selected at the time of reproducing the next sector, the sampling clock SP is selected according to the state of the magneto-optical disk 1 used at that time.
The phase adjustment operation of a can be performed, and the zero phase delay amount can be set more appropriately.

Further, the difference discriminating unit 25 limits the difference data Dd used by the average value calculating unit 33 to calculate the difference average value data AV to a value within a predetermined appropriate range. Even if the recording area of the preamble signal has a defect and the sample value of the reproduction data DF includes an error (noise), the zero phase delay amount is accurately calculated without being affected by the noise. be able to.

FIG. 24 shows a main part of a control system of a magneto-optical disk drive device according to still another embodiment of the present invention. In the figure, the same parts as those in FIG. 22 and corresponding parts are designated by the same reference numerals. Further, in the figure, parts not directly related to the present invention are omitted.

In the figure, the control unit 35 is for executing the control processing of this control system, and exchanges various data with a host device which uses this magneto-optical disk drive device as an external storage device. In addition, the control unit 35
Designates the operation mode of the timing generation unit 13 to control the operation mode of the phase controller, controls the content of the recording data WD output to the write control unit 15, and reproduces the reproduced digital data output from the demodulator 17. RD, error detection and correction circuit 3
The corrected reproduced digital data RDc output from 1 and the error signal ED are input. At the same time, the control unit 35 also controls various other elements (for example, seek system).

FIG. 25 shows a processing example of the control unit 35 when the host apparatus issues an initialization processing command with the magneto-optical disk 1 mounted in the magneto-optical disk drive apparatus.

First, the control section 35 records test data having a predetermined data pattern on all sectors of all recording tracks of the magneto-optical disk 1 (Process 10).
1). Here, as the test data to be recorded at this time, in the recording modulation method of the magneto-optical disk drive device, a data pattern that is particularly prone to data errors is used.

Here, in the data recording at the time of initialization, the control section 35 first tracks the optical pickup device on the first recording track TK of the magneto-optical disk 1, and in that state, records the data in the timing generating section 13. Set the mode. As a result, the sector mark SM is detected, the clock mark is detected, and
Also, the phase synchronization of the PLL circuit 14 with respect to the clock mark signal CM of the sampling clock SP is pulled in.

In this way, the sampling clock S
When P is phase-synchronized with the clock mark, the control unit 35
The reproduced digital data RD output from the demodulator 17 is input, and the sector address SA, track address upper digit information TAH, track address lower digit information TAL, track address lower digit inversion information CTAL, track address upper digit inversion information CTAH, and , The recording data WD corresponding to the preamble signal is output from the start timing of the preamble signal notified from the timing generation unit 13 while confirming the sector address SA based on the sector address inversion information CSA. Record the preamble signal at.

When the recording of the preamble signal is completed, the recording data W formed by adding the error correction code to the test data from the start timing of the next user data area UDT.
D is output, whereby the recording operation of test data for one sector is completed.

This process is repeatedly executed for all sectors of all recording tracks, and the test data recording operation is completed.

Next, the control unit 35 sets the above-mentioned first operation mode in the timing generation unit 13 (process 10).
2) In that state, the test data reproducing operation is executed for all the sectors of all the recording tracks, and at that time, the error output from the error detection / correction circuit 31 for all the sectors of all the recording tracks. The value of the signal ED is stored as the error 1 signal for each sector (process 103).

Next, the control unit 35 controls the timing generation unit 1
3 is set to the second operation mode described above (Processing 10
4) In that state, the test data reproducing operation is executed for all the sectors of all the recording tracks, and at that time, the error output from the error detection / correction circuit 31 for all the sectors of all the recording tracks. The value of the signal ED is stored as an error 2 signal for each sector (process 105).

In this way, when the error 1 signal and the error 2 signal are stored for all the sectors of all the recording tracks, the error 1 signal and the error 2 signal are compared for each sector, and the smaller value is obtained. Of the error signal is determined, and the operation mode corresponding to the determined error signal is set as the optimum operation mode of the sector (process 106).

Then, the operation mode management information including the list information of the operation modes set for each sector is formed, and the operation mode management information is stored in the magneto-optical disk 1.
The data is recorded in a predetermined area of the management information area set in the predetermined recording area (step 107).

In this way, when the magneto-optical disk 1 is initialized, the test data is recorded on the entire surface of the magneto-optical disk 1, and the test data is recorded in each of the above-mentioned first operation mode and second operation mode. An operation mode with few data errors when reproduced is determined as an operation mode when reproducing each sector, and operation mode management information representing the determination result is recorded in a predetermined area of the management information area of the magneto-optical disk 1. .

FIG. 26 shows an example of processing executed when it is detected that the magneto-optical disk 1 is inserted in the magneto-optical disk drive device.

First, the recording data is read from a predetermined area of the management information area of the inserted magneto-optical disk 1, the content of the read data is checked, and the magneto-optical disk 1 is read.
Check if is formatted (decision 20
1).

When the result of judgment 201 is NO,
The host apparatus is notified that the magneto-optical disk 1 inserted at that time is unformatted (step 202), and the processing for this magneto-optical disk 1 is terminated.

When the result of the judgment 201 is YES, the operation mode management information is read from the management information area (process 203) and saved (process 204), the mounting of the magneto-optical disk 1 is completed, and the data is read. The host device is notified that the access is possible (step 205), and the standby state is entered in order to continue the operation for the magneto-optical disk 1 inserted at that time.

When the magneto-optical disk 1 is mounted in this manner, the control section 1 reads and saves the operation mode management information, and prepares for the subsequent data reproducing operation. Also,
When the unformatted magneto-optical disk 1 is loaded, the host device is notified of that fact and the processing for the magneto-optical disk 1 is interrupted.

FIG. 27 shows an example of processing executed by the control unit 35 when reproducing data.

First, in the reproduction range designated by the host device, the sector having the smallest sector address which is not reproduced is set as the target sector, and the operation mode of the target sector is read from the stored operation mode management information. hand,
The operation mode is set in the timing generator 13 (process 301).

Then, seek to the target sector (process 30
2) The corrected reproduced digital data RDc for one sector output from the error detection / correction circuit 31 is input and stored (process 303).

Next, it is judged whether or not the data reproduction has been completed for all the sectors designated by the host device (decision 304). When the result of the judgment 304 is NO, the process returns to step 301, The data reproducing operation from the sector is executed.

When the result of determination 304 is YES, the data stored at that time is sequentially output to the host device (process 305) and this operation is ended.

In this way, at the time of data reproduction, the operation mode of the sector for data reproduction is set in the timing generation unit 13 in sector units according to the content of the operation mode management information, and the reproduction operation is performed in that state. Therefore, the phase adjustment operation of the sampling clock SPa can be performed according to the state of the magneto-optical disk 1 used at that time, and the zero phase delay amount can be set more appropriately. As a result, it is possible to further reduce the probability of data error occurrence during data reproduction.

FIG. 28 shows a main part of a control system of a magneto-optical disk drive device according to still another embodiment of the present invention. In the figure, the same parts as those in FIGS. 23 and 24 and corresponding parts are designated by the same reference numerals. Further, in the figure, parts not directly related to the present invention are omitted.

In this embodiment, the control unit 35 executes the same control operation as that of the control unit 35 of the embodiment shown in FIG. 24 to execute the initialization operation of the magneto-optical disk 1 and the data reproducing operation.

Further, in this embodiment, the difference discriminating unit 25 limits the difference data Dd input to the average value calculating unit 33, so that the zero phase delay amount during the phase adjustment of the sampling clock SPa can be more appropriately adjusted. This can be set, and the probability of data error occurrence during data reproduction can be further reduced.

By the way, in the above-mentioned embodiment, the case where the recording tracks of the magneto-optical disk are formed concentrically has been described, but the present invention is similarly applied to the case where the recording tracks are formed spirally. Can be applied.

Further, in the above-described embodiment, the case where the magneto-optical disk is rotationally driven at a constant angular velocity has been described. However, a driving method in which the angular velocity is switched according to the radial position of the magneto-optical disk being accessed is used. The present invention can be similarly applied when used.

[0215]

As described above, according to the present invention,
Since the delay amount of the sampling clock is controlled based on the difference data of the reproduction data sampled at the timing before and after the recording pit of the preamble signal, even if the recording pit cannot be obtained, the delay amount of the sampling clock can be adjusted appropriately. Can be controlled. Further, when a recording defect is generated in the recording area of the preamble signal and difference data with a large error is obtained, the difference data is not used, so that the delay amount of the sampling clock should be controlled more accurately. You can Further, since two operation modes for setting the delay amount of the sampling clock are provided and the operation mode in which the data error is less likely to occur is selected, the error occurrence at the time of data reproduction can be suppressed. Also, by setting the length of the recording area of the preamble signal to be large, it is possible to more reliably perform the operation when adjusting the delay amount of the sampling clock.

[Brief description of drawings]

FIG. 1 is a schematic diagram showing an example of a track structure of a magneto-optical disk.

FIG. 2 is a schematic diagram illustrating the relationship between a servo area and a data area.

FIG. 3 is a schematic diagram showing an example of a servo pattern.

FIG. 4 is a schematic diagram showing an example of a data format of a sector and an example of data recorded in an address area.

FIG. 5 is a schematic diagram showing an example of a preamble signal.

FIG. 6 is a schematic diagram for explaining an example of a change in a difference between sampling values due to a phase difference between a sampling clock and a reproduction signal.

FIG. 7 is a schematic diagram for explaining an example of a change in a difference between sampling values due to a phase difference between a sampling clock and a reproduction signal.

FIG. 8 is a schematic diagram for explaining an example of a delay amount calculation method of the present invention.

9 is a schematic diagram showing an example of changes in delay time according to the method of FIG.

FIG. 10 is a graph showing an example of an approximate straight line.

FIG. 11 is a block diagram showing an example of a phase control device according to an embodiment of the present invention.

FIG. 12 is a schematic diagram showing an example of an operation period of the device of FIG.

FIG. 13 is a schematic diagram for explaining a problem that occurs when a recording medium has a defect.

FIG. 14 is a graph showing another example of an approximate straight line.

FIG. 15 is a block diagram showing an example of a phase control device according to another embodiment of the present invention.

FIG. 16 is a schematic diagram for explaining another example of the change in the difference between the sampling values due to the phase difference between the sampling clock and the reproduction signal.

FIG. 17 is a schematic diagram for explaining another example of the change in the difference between the sampling values due to the phase difference between the sampling clock and the reproduction signal.

FIG. 18 is a schematic diagram showing an example of changes in delay time according to the methods of FIGS. 16 and 17.

FIG. 19 is a block diagram showing an example of a phase control device according to still another embodiment of the present invention.

FIG. 20 is a block diagram showing an example of a phase control device according to still another embodiment of the present invention.

FIG. 21 is a schematic diagram showing another example of a preamble signal.

FIG. 22 is a block diagram showing an example of a phase control device according to another embodiment of the present invention.

FIG. 23 is a block diagram showing an example of a phase control device according to still another embodiment of the present invention.

FIG. 24 is a block diagram showing an example of a control system of a magneto-optical disk drive device according to still another embodiment of the present invention.

FIG. 25 is a flowchart showing an example of initialization processing of the apparatus of FIG. 24.

FIG. 26 is a flowchart showing an example of processing executed by the apparatus of FIG. 24 when a magneto-optical disk is inserted.

FIG. 27 is a flowchart showing an example of processing executed by the device of FIG. 24 when reproducing data.

FIG. 28 is a block diagram showing an example of a control system of a magneto-optical disk drive device according to still another embodiment of the present invention.

[Explanation of symbols]

 10 Binarization Circuit 11 Analog / Digital Converter 12 Synchronous Signal Extractor 13 Timing Generator 14 PLL Circuit 16 Variable Delay Line 18 Difference Detector 19, 26, 27, 30, 33 Average Value Calculator 20 Linear Approximation Calculator 21 Zero phase delay amount calculation unit 22 Switcher 23 Delay amount generation unit 25 Difference determination unit 32 Mode determination unit 35 Control unit

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[Procedure amendment]

[Submission date] December 4, 1992

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] Brief description of the drawing

[Correction method] Change

[Correction content]

[Brief description of drawings]

FIG. 1 is a schematic diagram showing an example of a track structure of a magneto-optical disk.

FIG. 2 is a schematic diagram illustrating the relationship between a servo area and a data area.

FIG. 3 is a schematic diagram showing an example of a servo pattern.

FIG. 4 is a schematic diagram showing an example of a data format of a sector and an example of data recorded in an address area.

FIG. 5 is a schematic diagram showing an example of a preamble signal.

FIG. 6 is a schematic diagram for explaining an example of a change in a difference between sampling values due to a phase difference between a sampling clock and a reproduction signal.

FIG. 7 is a schematic diagram for explaining an example of a change in a difference between sampling values due to a phase difference between a sampling clock and a reproduction signal.

FIG. 8 is a schematic diagram for explaining an example of a delay amount calculation method of the present invention.

9 is a schematic diagram showing an example of changes in delay time according to the method of FIG.

FIG. 10 is a graph showing an example of an approximate straight line.

FIG. 11 is a block diagram showing an example of a phase control device according to an embodiment of the present invention.

FIG. 12 is a schematic diagram showing an example of an operation period of the device of FIG.

FIG. 13 is a schematic diagram for explaining a problem that occurs when a recording medium has a defect.

FIG. 14 is a graph showing another example of an approximate straight line.

FIG. 15 is a block diagram showing an example of a phase control device according to another embodiment of the present invention.

FIG. 16 is a schematic diagram for explaining another example of the change in the difference between the sampling values due to the phase difference between the sampling clock and the reproduction signal.

FIG. 17 is a schematic diagram for explaining another example of the change in the difference between the sampling values due to the phase difference between the sampling clock and the reproduction signal.

FIG. 18 is a schematic diagram showing an example of changes in delay time according to the methods of FIGS. 16 and 17.

FIG. 19 is a block diagram showing an example of a phase control device according to still another embodiment of the present invention.

FIG. 20 is a block diagram showing an example of a phase control device according to still another embodiment of the present invention.

FIG. 21 is a schematic diagram showing another example of a preamble signal.

FIG. 22 is a block diagram showing an example of a phase control device according to another embodiment of the present invention.

FIG. 23 is a block diagram showing an example of a phase control device according to still another embodiment of the present invention.

FIG. 24 is a block diagram showing an example of a control system of a magneto-optical disk drive device according to still another embodiment of the present invention.

FIG. 25 is a flowchart showing an example of initialization processing of the apparatus of FIG. 24.

FIG. 26 is a flowchart showing an example of processing executed by the apparatus of FIG. 24 when a magneto-optical disk is inserted.

FIG. 27 is a flowchart showing an example of processing executed by the device of FIG. 24 when reproducing data.

FIG. 28 is a block diagram showing an example of a control system of a magneto-optical disk drive device according to still another embodiment of the present invention.

[Explanation of Codes] 10 Binarization Circuit 11 Analog / Digital Converter 12 Synchronous Signal Extraction Section 13 Timing Generation Section 14 PLL Circuit 16 Variable Delay Line 18 Difference Detection Section 19, 26, 27, 30, 33 Average Value Calculation Section 20 Linear approximation calculation unit 21 Zero phase delay amount calculation unit 22 Switcher 23 Delay amount generation unit 25 Difference determination unit 32 Mode determination unit 35 Control unit

[Procedure Amendment 2]

[Document name to be corrected] Drawing

[Correction target item name] All drawings

[Correction method] Change

[Correction content]

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Claims (12)

[Claims] 1. A phase of a sampling clock of reproduced data is controlled by a sampling servo method in which servo patterns including clock marks are recorded on a storage medium at regular intervals, and based on the level of a reproduced signal sampled by the sampling clock. In a phase control device for controlling the delay time of a sampling clock by means of a preamble recording means for recording a preamble signal consisting of a predetermined bit pattern in which recording pits do not appear around at least one clock prior to recording data, and the delay time of the sampling clock. Delay data generating means for outputting the set value of, and difference data detecting means for detecting the difference in signal level of the reproduction data obtained at the timing of the sampling clock before and after the recording pit of the preamble signal, When the preamble signal is detected, the delay time setting value output from the delay data generating means is cyclically switched to a predetermined plurality of steps to periodically switch the sampling clock delay time, and the delay time setting value is the same value. The average value of the plurality of difference data detected by the difference data detection means is calculated, the optimum delay amount of the sampling clock is calculated based on the average value of the difference data, and the sampling clock is detected after the preamble signal is detected. The phase control device is provided with a control means for setting the delay amount of the signal to the calculated optimum delay amount. 2. A phase of a sampling clock of reproduced data is controlled by a sampling servo system in which servo patterns including clock marks are recorded at a constant interval on a storage medium, and based on the level of a reproduced signal sampled by the sampling clock. In a phase control device for controlling the delay time of a sampling clock by means of a preamble recording means for recording a preamble signal consisting of a predetermined bit pattern in which recording pits do not appear around at least one clock prior to recording data, and the delay time of the sampling clock. Delay data generating means for outputting the set value of, and difference data detecting means for detecting the difference in signal level of the reproduction data obtained at the timing of the sampling clock before and after the recording pit of the preamble signal, When the preamble signal is detected, the delay time setting value output from the delay data generating means is periodically switched to a predetermined plurality of steps and in a unit of a predetermined number of sampling clocks to cyclically switch the delay time of the sampling clocks and delay. When the time set values are the same value, the average value of the plurality of difference data detected by the difference data detecting means is calculated, and the optimum delay amount of the sampling clock is calculated based on the average value of the difference data, and the preamble signal After the detection, the phase control device is provided with control means for setting the delay amount of the sampling clock to the calculated optimum delay amount. 3. The phase of a sampling clock of reproduction data is controlled by a sampling servo system in which servo patterns including clock marks are recorded on a storage medium at regular intervals, and based on the level of a reproduction signal sampled by the sampling clock. In a phase control device for controlling the delay time of a sampling clock by means of a preamble recording means for recording a preamble signal consisting of a predetermined bit pattern in which recording pits do not appear around at least one clock prior to recording data, and the delay time of the sampling clock. Delay data generating means for outputting the set value of, and difference data detecting means for detecting the difference in signal level of the reproduction data obtained at the timing of the sampling clock before and after the recording pit of the preamble signal, A difference data discriminating means for discriminating that the size of the difference data outputted from the difference data detecting means is within a predetermined range, and a predetermined delay time setting value outputted from the delay data generating means at the time of detecting the preamble signal. And the delay time of the sampling clock is switched periodically, and the difference data detected by the difference data detecting means is input when there is a judgment output from the difference data judging means. Based on the input difference data, the average value of the difference data having the same delay time setting value is calculated, the optimum delay amount of the sampling clock is calculated based on the average value of the difference data, and after the preamble signal is detected. A control means for setting the delay amount of the sampling clock to the calculated optimum delay amount Phase control apparatus, characterized in that. 4. The phase of a sampling clock of reproduction data is controlled by a sampling servo system in which servo patterns including clock marks are recorded at a constant interval on a storage medium, and based on the level of a reproduction signal sampled by the sampling clock. In a phase control device for controlling the delay time of a sampling clock by means of a preamble recording means for recording a preamble signal consisting of a predetermined bit pattern in which recording pits do not appear around at least one clock prior to recording data, and the delay time of the sampling clock. Delay data generating means for outputting the set value of, and difference data detecting means for detecting the difference in signal level of the reproduction data obtained at the timing of the sampling clock before and after the recording pit of the preamble signal, A difference data discriminating means for discriminating that the size of the difference data outputted from the difference data detecting means is within a predetermined range, and a predetermined delay time setting value outputted from the delay data generating means at the time of detecting the preamble signal. Of the predetermined number of sampling clocks, the delay time of the sampling clocks is periodically switched, and the difference data detecting means detects the difference output when the difference data determining means outputs the difference. Difference data is input, the average value of the difference data when the delay time setting value is the same value is calculated based on the input difference data, and the optimum delay amount of the sampling clock based on the average value of the difference data is calculated. After the preamble signal is detected, the delay amount of the sampling clock is calculated as Phase control apparatus characterized by comprising a control means for setting the optimum delay amount issued. 5. The phase of a sampling clock of reproduced data is controlled by a sampling servo system in which servo patterns including clock marks are recorded at a constant interval on a storage medium, and based on the level of a reproduced signal sampled by the sampling clock. In a phase control device for controlling the delay time of a sampling clock by means of a preamble recording means for recording a preamble signal consisting of a predetermined bit pattern in which recording pits do not appear around at least one clock prior to recording data, and the delay time of the sampling clock. Delay data generating means for outputting the set value of, and difference data detecting means for detecting the difference in signal level of the reproduction data obtained at the timing of the sampling clock before and after the recording pit of the preamble signal, When the preamble signal is detected, the delay time setting value output from the delay data generating means is cyclically switched to a predetermined plurality of steps to periodically switch the sampling clock delay time, and the delay time setting value is the same value. The average value of the plurality of difference data detected by the difference data detection means is calculated, the optimum delay amount of the sampling clock is calculated based on the average value of the difference data, and the sampling clock is detected after the preamble signal is detected. First, the delay amount of the first delay is set to the calculated optimum delay amount.
Operation mode and the delay time setting value output from the delay data generating means at the time of detecting the preamble signal are sequentially switched to a predetermined plurality of steps and in a unit of a predetermined sampling clock, and the delay time of the sampling clock is periodically changed. And the average value of the plurality of difference data detected by the difference data detecting means when the delay time set value is the same value, and the optimum delay amount of the sampling clock is calculated based on the average value of the difference data. After the calculation and the detection of the preamble signal, the timing control means having a second operation mode for setting the delay amount of the sampling clock to the calculated optimum delay amount, and the operation mode of the timing control means are set to the first operation mode. Mode setting for selectively setting either the operation mode or the second operation mode A phase control device comprising means. 6. The phase of a sampling clock of reproduction data is controlled by a sampling servo system in which servo patterns including clock marks are recorded on a storage medium at regular intervals, and based on the level of a reproduction signal sampled by the sampling clock. In a phase control device for controlling the delay time of a sampling clock by means of a preamble recording means for recording a preamble signal consisting of a predetermined bit pattern in which recording pits do not appear around at least one clock prior to recording data, and the delay time of the sampling clock. Delay data generating means for outputting the set value of, and difference data detecting means for detecting the difference in signal level of the reproduction data obtained at the timing of the sampling clock before and after the recording pit of the preamble signal, A difference data discriminating means for discriminating that the size of the difference data outputted from the difference data detecting means is within a predetermined range, and a predetermined delay time setting value outputted from the delay data generating means at the time of detecting the preamble signal. And the delay time of the sampling clock is switched periodically, and the difference data detected by the difference data detecting means is input when there is a judgment output from the difference data judging means. Based on the input difference data, the average value of the difference data having the same delay time setting value is calculated, the optimum delay amount of the sampling clock is calculated based on the average value of the difference data, and after the preamble signal is detected. , A first operation mode for setting the delay amount of the sampling clock to the calculated optimum delay amount. And when the preamble signal is detected, the delay time setting value output from the delay data generating means is periodically switched to a predetermined plurality of steps and in a unit of a predetermined number of sampling clocks to switch the delay time of the sampling clocks periodically. The difference data detected by the difference data detecting means is inputted when there is a discrimination output from the difference data discriminating means, and the average of the difference data when the delay time set value is the same value based on the inputted difference data. Calculate the value, calculate the optimal delay amount of the sampling clock based on the average value of the difference data,
After detecting the preamble signal, the timing control means has a second operation mode for setting the delay amount of the sampling clock to the calculated optimum delay amount, and the operation mode of the timing control means is set to the first operation mode or A phase control device comprising a mode setting means for selectively setting one of the second operation modes. 7. The phase of a sampling clock of reproduction data is controlled by a sampling servo system in which servo patterns including clock marks are recorded on a storage medium at regular intervals, and based on the level of a reproduction signal sampled by the sampling clock. In a phase control device for controlling the delay time of a sampling clock by means of a preamble recording means for recording a preamble signal consisting of a predetermined bit pattern in which recording pits do not appear around at least one clock prior to recording data, and the delay time of the sampling clock. Delay data generating means for outputting the set value of, and difference data detecting means for detecting the difference in signal level of the reproduction data obtained at the timing of the sampling clock before and after the recording pit of the preamble signal, When the preamble signal is detected, the delay time setting value output from the delay data generating means is cyclically switched to a predetermined plurality of steps to periodically switch the sampling clock delay time, and the delay time setting value is the same value. The average value of the plurality of difference data detected by the difference data detection means is calculated, the optimum delay amount of the sampling clock is calculated based on the average value of the difference data, and the sampling clock is detected after the preamble signal is detected. First, the delay amount of the first delay is set to the calculated optimum delay amount.
Operation mode and the delay time setting value output from the delay data generating means at the time of detecting the preamble signal are sequentially switched to a predetermined plurality of steps and in a unit of a predetermined sampling clock, and the delay time of the sampling clock is periodically changed. And the average value of the plurality of difference data detected by the difference data detecting means when the delay time set value is the same value, and the optimum delay amount of the sampling clock is calculated based on the average value of the difference data. After the calculation and the detection of the preamble signal, the timing control means having the second operation mode for setting the delay amount of the sampling clock to the calculated optimum delay amount, and the data error contained in the reproduction data are detected. Error detection means and the timing control means set to the first operation mode When the number of data errors detected by the error detecting means exceeds the predetermined range when the data reproducing operation is executed in the above state, the mode controlling means for setting the timing controlling means to the second operation mode is provided. A phase control device characterized by the above. 8. The phase of a sampling clock of reproduction data is controlled by a sampling servo system in which servo patterns including clock marks are recorded on a storage medium at regular intervals, and based on the level of a reproduction signal sampled by the sampling clock. In a phase control device for controlling the delay time of a sampling clock by means of a preamble recording means for recording a preamble signal consisting of a predetermined bit pattern in which recording pits do not appear around at least one clock prior to recording data, and the delay time of the sampling clock. Delay data generating means for outputting the set value of, and difference data detecting means for detecting the difference in signal level of the reproduction data obtained at the timing of the sampling clock before and after the recording pit of the preamble signal, A difference data discriminating means for discriminating that the size of the difference data outputted from the difference data detecting means is within a predetermined range, and a predetermined delay time setting value outputted from the delay data generating means at the time of detecting the preamble signal. And the delay time of the sampling clock is switched periodically, and the difference data detected by the difference data detecting means is input when there is a judgment output from the difference data judging means. Based on the input difference data, the average value of the difference data having the same delay time setting value is calculated, the optimum delay amount of the sampling clock is calculated based on the average value of the difference data, and after the preamble signal is detected. , A first operation mode for setting the delay amount of the sampling clock to the calculated optimum delay amount. And when the preamble signal is detected, the delay time setting value output from the delay data generating means is periodically switched to a predetermined plurality of steps and in a unit of a predetermined number of sampling clocks to switch the delay time of the sampling clocks periodically. The difference data detected by the difference data detecting means is inputted when there is a discrimination output from the difference data discriminating means, and the average of the difference data when the delay time set value is the same value based on the inputted difference data. Calculate the value, calculate the optimal delay amount of the sampling clock based on the average value of the difference data,
After detecting the preamble signal, timing control means having a second operation mode for setting the delay amount of the sampling clock to the calculated optimum delay amount, and error detection for detecting a data error included in the reproduced data And the timing control means when the number of data errors detected by the error detection means exceeds a predetermined range when the data reproducing operation is executed in the state where the timing control means is set to the first operation mode. A phase control device comprising mode control means for setting the means to a second operation mode. 9. The recording medium is divided into sectors having a predetermined data length, and each sector records an address area in which address data for identifying each sector is recorded in advance and arbitrary data. And a preamble area provided between the address area and the user data area for setting the preamble signal, the interval being set to be longer than the interval of the servo pattern. Claim 1 or Claim 2 or Claim 3 or Claim 4 or Claim 5 or Claim 6 characterized by the above.
Alternatively, the phase control device according to claim 7 or claim 8. 10. The phase of a sampling clock of reproduced data is controlled in units of sectors by a sampling servo system in which servo patterns including clock marks are recorded on a storage medium at regular intervals, and reproduced signals sampled at the sampling clock are controlled. In a control method of a phase control device for controlling a delay time of a sampling clock based on a level, a preamble recording means for recording a preamble signal having a predetermined bit pattern in which a recording pit does not appear at least about one clock before recording data, A delay data generating means for outputting the set value of the delay time of the sampling clock, and a difference in the signal level of the reproduction data obtained at the timing of the sampling clock before and after the recording pit of the preamble signal are detected. And the differential data detecting means for detecting the preamble signal, the delay time setting value output from the delay data generating means is periodically switched to a plurality of predetermined steps to periodically switch the delay time of the sampling clock, When the set values are the same value, the average value of the plurality of difference data detected by the difference data detecting means is calculated, and the optimum delay amount of the sampling clock is calculated based on the average value of the difference data, and the preamble signal is calculated. After the detection, the delay amount of the sampling clock is set to the calculated optimum delay amount.
Operation mode and the delay time setting value output from the delay data generating means at the time of detecting the preamble signal are sequentially switched to a predetermined plurality of steps and in a unit of a predetermined sampling clock, and the delay time of the sampling clock is periodically changed. And the average value of the plurality of difference data detected by the difference data detecting means when the delay time set value is the same value, and the optimum delay amount of the sampling clock is calculated based on the average value of the difference data. After the calculation and the detection of the preamble signal, the timing control means having the second operation mode for setting the delay amount of the sampling clock to the calculated optimum delay amount, and the data error contained in the reproduction data are detected. Error detection means to activate each section of the recording medium when the recording medium is initialized. A predetermined data pattern is recorded on each of the sectors, the number of data errors detected by the error detection means when the first operation mode is set in the timing control means, and the second in the timing control means for each sector. When the operation mode is set, the number of data errors detected by the error detecting means is compared, the operation mode with the smaller number of data errors is discriminated for each sector, and the management information indicating the discrimination result is recorded. After recording on the medium and after initializing the recording medium, read the management information recorded on the recording medium, and select the operation mode to be set in the timing control means for each sector based on the contents of the management information. A method for controlling a phase control device, comprising: 11. The phase of a sampling clock of reproduction data is controlled by a sampling servo method in which servo patterns including clock marks are recorded on a storage medium at regular intervals, and based on the level of a reproduction signal sampled by the sampling clock. In a control method of a phase control device for controlling a delay time of a sampling clock by means of a preamble recording means for recording a preamble signal consisting of a predetermined bit pattern in which recording pits do not appear around at least one clock before recording data, and the sampling clock. Delay data generating means for outputting the set value of the delay time of the preamble signal, and differential data for detecting the difference in the signal level of the reproduction data obtained at the timing of the sampling clock before and after the recording pit of the preamble signal A detecting means, a difference data judging means for judging that the size of the difference data outputted from the difference data detecting means is within a predetermined range, and a delay time outputted from the delay data generating means at the time of detecting the preamble signal. The set value is cyclically switched to a predetermined plurality of steps to cyclically switch the delay time of the sampling clock, and the differential data detected by the differential data detecting means when there is a discriminative output from the differential data discriminating means. The average value of the difference data having the same delay time setting value is calculated based on the input difference data, and the optimum delay amount of the sampling clock is calculated based on the average value of the difference data. After detecting the signal, the delay amount of the sampling clock is set to the calculated optimum delay amount. Operation mode and the delay time setting value output from the delay data generating means at the time of detecting the preamble signal are sequentially switched to a predetermined plurality of steps and in a unit of a predetermined sampling clock, and the delay time of the sampling clock is periodically changed. And the difference data detected by the difference data detecting means is input when there is a discrimination output from the difference data discriminating means, and the difference when the delay time setting value is the same value based on the inputted difference data. Calculate the average value of the data, calculate the optimal delay amount of the sampling clock based on the average value of the difference data,
After detecting the preamble signal, timing control means having a second operation mode for setting the delay amount of the sampling clock to the calculated optimum delay amount, and error detection for detecting a data error included in the reproduced data Means for recording a predetermined data pattern in each sector of the recording medium at the time of initialization of the recording medium, and setting the first operation mode in the timing control means for each sector, the error detecting means Of the number of data errors detected by the above-mentioned timing control means and the number of data errors detected by the above-mentioned error detection means when the second operation mode is set in the above-mentioned timing control means, and the number of data errors is higher for each sector. The operating mode that has few errors is recorded, and the management information showing the judgment result is recorded on the recording medium. After the body initialization, the management information recorded on the recording medium is read out, and the operation mode to be set in the timing control means is selected for each sector based on the content of the management information. Device control method. 12. The recording medium is divided into sectors of a predetermined data length, and each sector records an address area in which address data for identifying each sector is recorded in advance and arbitrary data. And a preamble area provided between the address area and the user data area for setting the preamble signal, the interval being set to be longer than the interval of the servo pattern. Claim 10 or claim 11 characterized in that
A method for controlling the described phase control device.