JPS60212877A - Data recording system - Google Patents

Abstract

PURPOSE:To surely attain sector synchronism, by distributing plural sector synchronizing signals to a preamble. CONSTITUTION:A bit synchronizing signal BS1, plural sector synchronizing signals SS, and plural sector synchronizing Nos. SN0, SN1... corresponding to the signals SS are provided at the preamble PA1 of a preformat area before a data area. The preamble PA1 is read out by an optical pickup and processed by a bit synchronism detecting section 11 including a PLL, pattern comparation counting section 12, estimated function generating section 13, sector synchronizing signal discriminating section 14, adder 15, comparator 16, etc., and each signal SS is discriminated and synchronism of the signals is made. At the same time, the ending timing of the preamble PA1 is surely discriminated from the values of the sector synchronizing signals SNn-SN0. Therefore, sector synchronism can be attained surely and sector synchronizing signals and sector addresses of the succeeding preamble area of the preamble PA1 are highly reliably detected. Thus, accessing of a data area is always accurately performed.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to a sector-configured data recording system, and in particular to a format of a format section suitable for using an optical disc as a recording medium. [Prior Art] Devices using magnetic recording media such as magnetic tapes and magnetic disks are widely used as auxiliary storage devices, but in recent years, optical recording media (e.g. There are proposals to use optical disks (optical disks, etc.) as auxiliary storage devices.

For example, on an optical disc, the diameter of 1
Two micrometer-sized bits (small holes) are placed on the recording track on the surface.
Data is recorded by forming them at a period (interval) of about μm, and the recording capacity 1 has a diameter of about 30 crn, and 1 sheet per sheet.
It is about 011 to 1012 pi.

Usually, one recording track is set in a spiral shape,
Additionally, in order to increase the recording density, CLV (Constant
t Linear Velocity).

Now, since the access speed of the auxiliary storage device is generally slower than that of the main storage device, data is recorded in a continuous area in blocks of a certain amount.

At that time, to ensure that data can be read and written in a short time, predetermined blocks of data are organized into sectors,
'An address (sector address) is assigned to each sector for identification.

FIGS. 1(a) and 1(b) show conventional examples of data recording formats on tracks of optical discs.

In the same figure (,), a glyph format area PF, a data area DF, a preformer,
A plurality of sectors SC consisting of a gap GPI separating the data area PF and the data area PF are successively set apart from each other by the gear GP2.

Note that the glyph format area PF is formed in advance (for example, at the time of shipment of the optical disc) by the data area DF and the gap GP.
Tracks are formed with a total of 2 bits 1 apart.

As shown in the same figure (b), the preformat area PF is a synchronizing signal for matching the circuit conditions, that is, a pit gate of the data write/read circuit, and a signal for synchronizing the data write/read circuit with the generation timing of the recorded data. , a sector synchronization signal SS consisting of a bit string (non-turn) with a sharp autocorrelation for detecting the preformer, a synchronization signal BS, and a sector address SA for distinguishing the sector SC. Ranal.

The bit synchronization signal BS forming the preamplifier is a PLL (PhILse-Loc) for extracting the bit clock and data from the read signal from the optical pickup section.
A signal is used that allows the ked Loop circuit to be properly locked. For example, it is a signal that changes the state of successive signals at the minimum inversion period (ie, "0101..." in which the recording state is a repetition of the minimum bit length).

Further, the data area DF consists of a plurality of pieces of data to which a frame synchronization signal FS is attached and forms a frame, and a preamble (bit synchronization signal BS) attached to the beginning of these data. Note that the preamble in the data area DF only requires a smaller number of bits than the preamble in the glyph format area PF. Additionally, the frame synchronization signal FS consists of a sharp pattern of autocorrelation similar to the sector synchronization signal SS.

Now, when recording data in such a recording format, after bit synchronization is achieved with the preamble of the Amazu preformat area PF, the sector synchronization signal SS is detected, and the sector address SA is read out based on the detection timing. .

If it hails the desired sector, gear.

After 70GP2, write the grid in the data area DF, and then write the data of the first frame to the frame synchronization signal F.
Following S, the data of each frame is recorded sequentially.

When reading data, read the sector address SA in the same manner as described above, and if it indicates the desired sector, re-synchronize the bits with the preamble of the data area DF, then at the timing when the frame synchronization signal FS is detected. Read data for each frame based on

In this way, data is recorded and read by referring to the preformat area PF recorded in advance.

Incidentally, although optical disks can have extremely high recording densities as described above, they currently have a fairly high bit error rate of about 10<-5 >and are low in reliability.

Therefore, conventionally, there is a high probability that an error will occur in the sector synchronization signal SS of the preformer and VPF, and if this sector synchronization signal SS cannot be detected, the sector address SA
and the entire data area DF becomes inaccessible. Furthermore, since optical discs are generally not rewritable, a problem arises in that only the sector SC becomes unusable.

〔the purpose〕

The present invention has been made in order to eliminate the above-mentioned drawbacks of the prior art, and provides a data recording method that can ensure sector synchronization by arranging a sector synchronization signal etc. in the preamble of a preformat area. It is an object.

〔composition〕

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 2 shows a serial PAI of a preformatted tilted castle PF according to an embodiment of the present invention. Incidentally, as a matter of course, the preamble FAI is followed by the sector synchronization signal SS and the sector address SA as in FIG. 1(b).

This preamble FAI includes (n+1) bit synchronization signal BSI (length a1 bits), sector synchronization signal SS and sector synchronization number SN (value is n), and sector synchronization number 5N0 (value is O). The bit synchronization signal BS1'i is placed next to the bit synchronization signal BS1'i.

The preformat area PF and data area DF having such a preamble PAL are generated according to the format K by the signal generator shown in FIG.

That is, the format controller 1 operates the bit synchronization signal 3 generator 2 to generate the bit synchronization signal BS of the a1 bit.
After outputting I, the sector synchronization signal generator 3 is activated to output a sector synchronization signal SS, and further the sector synchronization number generator 4 is caused to generate a sector synchronization number 5Nni with a value of n. Then, the bit synchronization signal generation section 2, sector synchronization signal generation section 3, and sector synchronization number generation section 4 are operated repeatedly in sequence while decreasing the sector synchronization number 5NnO value 't-1 until it reaches O. The synchronizing signal generator 2 is activated to complete the preamble FAI.

Thereafter, after activating the sector synchronization signal generation section 3, the sector address generation section 5 is activated to generate the sector synchronization signal SS.
and generates sector address SA.

Then, the format controller 1 sequentially executes the above processing for each sector over the entire area of the track TR of the optical disc.

These signals output from the bit synchronization signal generation section 2, sector synchronization signal generation section 3, sector synchronization number generation section 4, and sector address generation section 5 are outputted to a recording section (not shown) via an OR circuit 9. , thereby forming a glyph format @Hani PF on the optical disc.

The former, former controller 1, bit synchronization signal generator 2, sector synchronization signal generator 3, sector synchronization number generator 4, and sector address generator 5 all operate in a predetermined manner.
It operates in sync with Tokuro and Ri. Further, 6 is a preamble generation unit that generates a grid signal (bit synchronization signal) for the data area DF, 7 is a frame synchronization signal generation unit that generates a frame synchronization signal FS, and 8 is a recording data DR.
This is a data buffer that stores data for one frame.

Next, a device for determining the preamble PAL'(j and detecting the sector synchronization signal SS of the preformat area is installed in the fourth
As shown in the figure.

In the figure, a read signal SR output from an optical pickup (not shown) is applied to a bit synchronization detection section 11 consisting of a PLL circuit, a data center/sererator circuit, etc. The PLL circuit is locked by the bit synchronization signal BSI in FAI, thereby separating the bit clock CP and read data RD.

The focus black and CP are applied to the black and white input terminals of the P-turn comparison calculation unit 12, the prediction function generation unit 13, and the sector redundancy and period number determination unit 14, and the read data RD is applied to the pattern comparison calculation unit 12 and the sector synchronization input terminal. It is added to the data input terminal of the number discriminator 14. Note that the bit black, CP, and read data RD are also added to a read/write control section (not shown).

The turn comparison/counting section 12 compares the consecutive predetermined number of bits of read data RD and the number of turns forming the sector synchronization signal SS, counts the number of matching bits, and adds the result to the adder 15. Further, the prediction function generating section 13 generates a prediction function for detecting the sector synchronization signal 5sl at a predetermined timing, and adds this to the adder 15.

The adder 15 adds the two input values and provides the result to the comparator 16, and the comparator 16 generates a sector synchronization detection signal DS when the input value is greater than or equal to a predetermined threshold. It is added to the AND circuit 17 and the sector synchronization number determination section 14.

For example, if the sector synchronization signal SS is
Assuming a 7-bit turn loloJ, the prediction function is given as r12321J (see Figure 5), which is the number of timings at which the 7th bit of the sector synchronization signal SS occurs when there is no bit shift (bit slip, f). The operation timing of section 13 is set. Also, in this case comparator 1
The threshold value set to 6 is "8", which is the number of bits of the sector synchronization signal SS plus 1.

Therefore, if there is no bit shift, the sector synchronization signal S
At the timing when the final bit of S is input, the count value of the i4 turn comparison and counting section 12 becomes 7, and at the same time, the output of the prediction function generation section 13 becomes 3, and the output of the adder 15 becomes 1.
Since the signal becomes 0, the comparator 16 outputs the sector synchronization detection signal DS.

Note that according to the sector synchronization signal SS and the prediction function in this case, sector synchronization can be detected even if a bit error occurs in two bits and one due to a bit slip due to jitter or the like.

In addition, examples of other optimal combinations of synchronization signals (synchronization codes) and prediction functions are shown in the following table. (Ezu; τ, auto) 1□1,
: 001 , 31 1□2, 1ooio ・4′ middle 1131 :010o1 5 ↓ 1141 1010110 6 ,'1221110110106 11331 '01011001 s : ・11111 1 00001 5 □ 1121 1 , 010011 6 1 ′ ・ 11311 ′ 010011 6 ′□j 11
41110”00”017: Sector synchronization number determination unit 14
receives the read data RD and sets the sector synchronization number S based on the timing when the sector synchronization detection signal DS is applied.
N (~5N0) Focus counter setting value BC and determined sector synchronization number SN for predicting 'i determination and next sector synchronization' signal SS (~SN)
The value NS of is output to the prediction function generating section 13.

As a result, the prediction function generating section 13 generates the prediction function complete pits one by one at the above-mentioned timing, and
If the value NS is 0, it is determined that the Noriample PAI has ended, and a final sector synchronization detection window signal W D lf is generated for determining the sector synchronization signal SS following the Noriample PAL, and this is output to the AND circuit 17. do.

The output of the AND circuit 17 becomes the logic level rHJ at the timing when the sector synchronization signal SS following the preamble FAI is detected, and as a result, the sector address discriminator 18
extracts the sector address SA from the read data RD based on the timing, determines whether the value matches the sector address AS given by the controller, and if so, extracts the sector address SA from the read data RD. Address detection signal DA k
'r:r Output to starvation section.

In this way, in the device shown in FIG.
The end timing of the preamble PAI, that is, the preamble PAIK, is determined from the values of the sector synchronization numbers SN to SN.
Since the timing of the subsequent sector synchronization signal SS is determined, the reliability of detecting the sector synchronization signal SS is greatly increased.

Also, even if a burst error occurs in the preamble PAL, any one sector synchronization number 5Nn-S
If it is possible to determine at least No', the end timing of the preamble PAI can be detected, so the preamble PAI
The probability of detecting the subsequent sector synchronization signal ss and sector address SA becomes much higher. Note that in some cases, even if the sector synchronization signal SS after the preamble PAI disappears for some reason, the sector address 5A ((() can be determined.

By the way, the Noriamp FAI shown in FIG. 2 is not able to determine the sector synchronization signal SS, nor can it deal with the case where the sector address SA disappears.

Therefore, FIG. 6 shows a preamble PAZ according to another embodiment of the present invention that can cope with the case where the sector address SA disappears.

This preamble PA2 has a configuration in which a sector address SA is inserted between the sector synchronization signal SS and the sector synchronization number SN in the Norimple PAL.

Further, FIG. 7 shows an example of a device for detecting the preamble PA2 (z).

In this device, the sector address discriminator 18& extracts the sector address sA from the read data RD every time the sector synchronization detection signal DS is generated, and the sector address detected after the output logic level of the AND circuit 17 becomes "H". It is determined whether or not the sector address SA with the largest number of detection signals matches the sector address AS, and if they match, the sector address detection signal DA (< is output to the control section).

In FIG. 7, the same parts as in FIG. 4 are designated by the same reference numerals, and their explanation will be omitted.

In addition, sector address error detection by the sector address discriminating unit 18m is performed using a CRC (Cyclic Redundancy Code) attached to the sector address SA in advance.
heck) The well-known method of reference isogeography of the code may be used.

In this way, since a plurality of sector addresses are set in serial PA2, the probability that sector address SA can be detected becomes very high.

By the way, if the bit synchronization can be maintained for a certain length at the beginning of the grid, the bit synchronization detection unit 11 can be matched.

Therefore, as shown in FIG. 8(,), (b), the bit synchronization signal BS of the preamble PAI and PA2
Pre-angle PA with a formation in which all I are gathered at the beginning
3, PA4'fl- can also be used.

In each of the embodiments described above, the sector synchronization numbers SN to SNSN- are used to indicate the end of the preamble, but the number is not limited to this. Next, another embodiment will be described in which the end of the preamble is indicated by placing a bit synchronization signal with a different number of bits at the end of the preamble.

The Noriamp PA 10 according to another embodiment of the present invention shown in FIG. 9 includes a bit synchronization signal BS5 of a predetermined bit length,
It consists of a sector synchronization signal SS inserted between the bit synchronization signals BS5 and a bit synchronization signal BS6 shorter than the bit synchronization signal BS5, and this bit synchronization signal BS6 is located at the rearmost part of the quadrangle PAIO and is connected to the quadrangle P.
AIO complete display.

This preamble PAIO (i-containing preformat area PF and data area DFVi) is formed by the signal generator shown in FIG.

That is, the former controller 1a alternately operates the bit synchronization signal generator 2a and the sector synchronization signal generator 3 to generate the bit synchronization signal BS5 and the sector synchronization signal S.
In addition to generating S all alternately, Norian pull PAIO
At the last part, the bit synchronization signal generating section 2a generates the bit synchronization signal BS6.

Similarly to the preamble PAIO shown in FIG. Hm1, a sector synchronization signal S81, a sector address SA and a data area DF follow. Also, the first
In FIG. 0, the same parts as in FIG.

FIG. 11 shows an apparatus for detecting the gliample PA10t. In the figure, the same parts as in FIG. 4 are designated by the same reference numerals, and the explanation thereof will be omitted.

In the same figure, the prediction function generation unit 13a is designed to be able to detect both the sector synchronization signal SS next to the bit synchronization signal BS5 and the sector synchronization signal SS next to the bit synchronization signal BS6 (that is, the sector synchronization signal after the Noriample PA100). , at time 1 as shown in FIG. ．． 1. A prediction function is generated corresponding to both timings.

Note that the time point to is the operation start timing of the prediction function generating section 13a, and the time point 1. corresponds to the length of the bit synchronization signal BS6. Further, the prediction function generating section 13a includes a comparator 16
It is reset by the sector synchronization detection signal DSK output from the controller, and its operation is restarted.

Furthermore, as shown in FIG. 12, the bit synchronization signal BS
If the preamble PA11e in which the sector synchronization signal SS and the sector address SA are located between 7 and 7 is used, the detection probability of the sector address SA can be improved in the same way as the preamble PA2.

A device [1] for detecting this preamble PAII is shown in FIG. In this figure, the same or corresponding parts as in FIG. 7 or FIG. 11 are given the same reference numerals, and the explanation thereof will be omitted.

Furthermore, preamples PAIO, PAII gold-deformed preamples PA12. PA13'i Figure 14 (a)
, (b) K indicates. These preamples PA12
, PA13, there are three types of appearance timings of the sector synchronization signal SS, so it is necessary to generate a prediction function corresponding to each timing.

Furthermore, this preamble PA12. PA13 to 15th
Preamble PA in the format shown in Figures (a) and (b)
14. It may be modified to PA15.

Note that the arrangement order of the sector synchronization signal, sector synchronization number, and sector address in the Norimple according to each of the embodiments described above is not limited to that shown in the drawings.

In addition, in preamble PAI O to PA15,
The bit synchronization signal placed at the end may be longer than the others.

〔effect〕

As described above, according to the present invention, since a plurality of sector synchronization signals are arranged in the quadrangle, the reliability of detecting sector synchronization signals can be significantly improved. Further, in the case where a plurality of sector addresses are arranged, the sector address can be reliably detected, so there is an advantage that it is possible to prevent inaccessible sectors from appearing.

[Brief explanation of the drawing]

Figure 1 (,) is a signal arrangement diagram showing the recording format of data in the recording track, Figure 1 (b) is a signal arrangement diagram showing the data recording format per sector, and Figure 2 is a signal arrangement diagram showing the data recording format per sector. 3 is a signal arrangement diagram showing a preamble according to an embodiment of the present invention, FIG. 3 is a block diagram showing an example of a signal generating device, and FIG.
The figure is a block diagram showing an example of the device for detecting the norian pull shown in Fig. 2, Fig. 5 is a graph showing an example of the predicted sailway, and Fig. 6 is another embodiment of the present invention. FIG. 7 is a block diagram showing an example of a device for detecting the preamble shown in FIG. 6, and FIG. 9(b) is a signal arrangement diagram showing a preamble according to still another embodiment of the present invention. FIG. 9 is a signal arrangement diagram showing a preamble according to still another embodiment of the present invention. Related glia/
FIG. 10 is a signal arrangement diagram showing another example of the signal generating device, and FIG. Fig. 12 is a signal arrangement diagram showing a preamble according to yet another embodiment of the present invention, and Fig. 13 shows an example of a device for detecting the preamble shown in section 12. FIG. 14(a) is a signal arrangement diagram showing a preamplifier according to still another embodiment of the present invention;
b) is a signal arrangement diagram showing a preamble according to yet another embodiment of the present invention; FIG. FIG. 2B is a signal arrangement diagram showing still another embodiment of the present invention. 1.1a...Format controller, 2,2a...
- Bit synchronization signal generation section, 3... Sector synchronization signal generation section, 4... Sector synchronization signal generation section, 5... Sector address generation section, 6... Preamble generation section, 7...
Frame synchronization signal generator, 8... data buffer, 9
...OR circuit, 11...Bit synchronization detection section, 12.
... Turn comparison counting section, 13.13a... Prediction function generation section, 14... Sector synchronization number determination section, 15...
・Adder, 16... Comparator, 17... AND circuit,
18.18a...Sector address determination unit. Inaba Agent Patent Attorney Crest 1) Makoto) He Shun ■ く(＼-++( Figure 70 Figure 71 Figure 73 Procedure Supplement J 4 to 3 branches (self-motivated) June 4, 1980 B To the Commissioner of the Japan Patent Office Display of the case Patent Application No. 69250 of 1982 Name of the invention Data recording system Amendment person Relationship with the case Patent applicant Address 1-3-6 Nakayangome, UJ-ku, Tokyo Name (67
1I) Ricoh Co., Ltd. Representative - 1 Hama 1fl Hiro Agent 105 Address 1-1118-6 Nishi-Shinbashi, Minato-ku, Tokyo Contents of the amendment (1) "Also, Recording density”
"Also, CAV (ConsjanL Angular
(velocity) or recording density”. (2) Delete "1 frame" on page 10, line 3 of the same book. that's all

Claims (3)

[Claims] (1) A preformatted area consisting of a grid area for matching circuit conditions, a sector synchronization signal for detecting the start of a sector, and a sector address signal for identifying a sector, and a data area consisting of multiple information frames. A data recording method in which a plurality of sector synchronization signals are arranged in the preamble in a data recording method with a sector configuration set before. (2) A preformat section consisting of a serial pulse for matching circuit conditions, a sector synchronization signal for detecting the beginning of a sector, and a sector address signal for identifying sectors is created from multiple information frames. 1. A data recording method having a sector configuration set before a data area, characterized in that a plurality of sector synchronization signals and number information for identifying the sector synchronization signals are arranged in the preamble. (3) A gliamp for matching circuit conditions,
a sector synchronization signal for detecting the beginning of a sector;
In a sector-configured data recording method in which a preformat area consisting of a sector address signal for identifying a sector is set before a data area consisting of a plurality of information frames, a plurality of sector synchronization signals and sector address signals are set in the above-mentioned Noriamp. A data recording method characterized by being arranged in