JP2000090593A - Optical disk recording and reproducing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enhance the reliability of recording data by phase locking wobbles with the number of reference clocks and judging the synchronizing staus between the period of the wobbles and the number frequency-demultiplication of the reference clocks based on criteria different for recording and for other than recording. SOLUTION: A wobble frequency error detecting circuit 17 detects rising pulses of a wobble binary signal, and outputs a synchronization detection signal when pulses whose priod T becomes to be within the range from the number 186-a of wobble clocks to the number 186+a of wobble clocks continue by (b) times. Moreover, the circuit 17 outputs an off-synchronization detection signal when pulses whose period T becomes to be within the number 183+c of wobble clocks continue by (d) times or when pulses whose period T becomes to be within the number 186-c of wobble clocks continue by (d) times. A wobble PLL status outputting circuit 18 makes a wobble synchronizing signal synchronized when the synthronization detection signal is outputted, and makes it asynchronized when the off-synchronization detection signal is outputted according to outputs of the circuit 17.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a rewritable optical disk recording / reproducing apparatus.

[0002]

2. Description of the Related Art A DVD-RAM format disk is composed of four pre-pit IDs in each sector and a recordable / reproducible data part. The data part is composed of tracks (lands, grooves) for guiding a light spot. That is, the track meanders at a period of 186 times the channel clock, and the meandering is reproduced as an electric signal in the push-pull tracking error signal. Since the frequency of the meandering signal (hereinafter referred to as wobble) is proportional to the physical linear velocity on the optical disk, the wobble signal and the 186 frequency division are divided by PLL.
By controlling the rotation speed of the spindle motor so that the clock whose phase is synchronized (hereinafter, referred to as a wobble clock) has a constant frequency, a constant linear velocity can be controlled. If data generated using the wobble clock as a reference clock is recorded, it is possible to record data completely synchronized with the sector, except for a PLL synchronization error.

[0003]

However, conversely, when the clock of the wobble PLL is not synchronized with the wobble on the disk, it is dangerous to use the wobble clock as a reference, and the constant linear velocity control cannot be performed correctly. Or the control signal using the wobble clock is not activated at the correct position, and the focus servo that focuses the light spot on the recording surface and the tracking servo that controls the light spot to follow the track become unstable. There is also. Also, in recording, a predetermined time is required from the end of sector recording until the laser reproduction power servo and high-frequency module control settle for ID reproduction, so if the recording control signal comes after the regular position, the subsequent May not be detected. If the recording control signal comes extremely behind, the pre-pit ID may be overwritten and the ID may become unreadable thereafter.

[0004] Further, if the disk has a defect or dust on the disk and the light is hardly reflected, the tracking error signal is also absent, but there is no wobble PLL for the no signal. , The accuracy of the clock itself deteriorates and the reliability is lost.

For this reason, the wobble PLL needs a means for detecting whether or not the PLL is locked. However, if the determination is made strict and it is easy to detect that the lock has been released, the constant linear velocity control, Switching of the clock used to generate the control signal becomes severe, and the system becomes unstable. Conversely, if the judgment is made loose and it is difficult to detect unlocking, reliability will be degraded such as undetected subsequent IDs or overwriting on pre-pit IDs.

[0006]

According to the present invention, in order to solve the above-mentioned problems, an optical disk recording / reproducing apparatus for recording / reproducing data synchronized with a reference clock on an optical disk having tracks meandering in a radial direction has been described. The reliability of the recording data is improved by determining the synchronous state of the meandering cycle and the frequency division of N (N is a natural number) of the reference clock by a different determination criterion other than during recording.

Also, in an optical disk recording / reproducing apparatus for recording / reproducing data synchronized with a reference clock on an optical disk whose tracks meander in a radial direction, the lack of the meandering is determined at different times or lengths during recording and during non-recording. By doing so, the reliability of the recorded data is improved.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing an optical disk recording / reproducing apparatus to which the present invention is applied. 1 is an optical disk, 2 is a spindle motor, 3 is an optical head, 4 is an arithmetic circuit, 5 is a servo control circuit, 6 is a reproduction signal processing circuit, 7 is a recording pulse generation circuit, 8 is a formatter, and 9 is a RISC.
Processing unit, 10 is a system controller, 11 is a polarity selection circuit, 12 is a band-pass filter, 13 is a wobble 2
A value conversion circuit, 14 is a wobble PLL circuit, 15 is a wobble PLL detection circuit, and 16 is a laser drive circuit.

The operation of the optical disk recording / reproducing circuit configured as described above will be described below.

The optical disk 1 is a DVD-RAM format disk, and tracks (lands, grooves) of a recording section meander in a substantially constant cycle, and the meandering cycle is 186 times the channel clock cycle. While the spindle motor 2 rotates the optical disk 1, the amount of light is controlled by the laser drive circuit 16, the laser light emitted from the optical head 3 is reflected on the optical disk 1, and the head amplifier receives a signal received by the photodetector of the optical head 3. The arithmetic circuit 4 performs an IV conversion, and outputs the output to the servo focus error signal, tracking error signal, address reproduction,
It is processed into a wideband push-pull tracking error signal and a full addition signal for wobble reproduction and data reproduction, and the focus error signal and the tracking error signal are sent to the servo control circuit 5, and the wideband push-pull tracking error signal and the full addition signal are sent to the reproduction signal processing circuit 6. Are output to the polarity selection circuit 11 of the wobble signal processing block. Focus servo control is performed on the light spot by the servo control circuit 5 so that the light spot is condensed on the recording surface of the optical disk 1, and the light spot is formed on a track (land or land on the recording surface of the optical disk 1) of the optical disk 1. Tracking servo control is performed so as to follow the groove). However,
In the tracking servo control, the gain is sufficiently low at the wobble frequency of the track of the optical disk, and the tracking servo control does not follow the wobble.

In the reproduction signal processing circuit 6, an ID gate generated by the formatter 8 selects a wideband push-pull tracking error signal in the header portion and a full addition signal in the recording portion, and the read gate generated by the formatter 8 is activated. By becoming an address,
Then, the data is reproduced and PLL is performed, and is output to the formatter 8 as digital data. The read gate is active only in the ID section during the standby state and during recording,
During reproduction, it becomes active in the ID section and the data section. The digital data reproduced by the reproduction signal processing circuit 6 is subjected to demodulation and error checking of a plurality of IDs at the head of the sector by the formatter 8, and the address from the last ID of the plurality of IDs is determined according to the ID number and the ID reproduction timing. After the reproduction signal processing delay time, the physical address position in the sector is detected and output to the wobble PLL detection circuit 15 as a sector synchronization signal based on the physical ID.

In the wobble signal processing block, the arithmetic circuit 4
And the tracking control polarity signal from the servo control circuit 5 is input to the polarity selection circuit 11, and the polarity of the signal output to the band-pass filter 12 is selected. The band-pass filter 12 performs recording / reproduction even when the linear velocity is different from the prescribed linear velocity when the light spot follows the track of the optical disc 1 and the frequency obtained from the meandering cycle of the track existing on the optical disc 1 is the center. Considering that it is possible, the bandwidth is such that the wobble signal can be sufficiently passed even in the range of 1/2 to 2 times the specified linear velocity. Bandpass filter 12
Is input to the wobble binarization circuit 13 and converted from analog to digital. At this time, since the wobble binarization circuit 13 performs binarization with a predetermined offset, when the wobble signal is smaller than a predetermined amplitude, the binarization signal is fixed to “L”. The header part and a few pulses immediately after it are masked by a mask gate generated by the formatter 8 so that the binarized signal of the header part is fixed to "L". With respect to the masked wobble binary data, the wobble binary data and the VCO clock are divided by 186 (the reference clock of the wobble cycle) so that the signal obtained by dividing the output clock of the VCO by N is phase-synchronized. The wobble PLL circuit 14 is configured so that the phase error of the VCO is fed back to the input of the VCO through a low-pass filter, and the output clock of the VCO of the wobble PLL thus configured is hereinafter referred to as a wobble clock. The wobble clock is used as a recording pulse generation circuit 7, a formatter 8, a wobble PLL detection circuit 1
5 is output. The formatter 8 determines whether to generate a wobble clock for each gate, control the constant linear velocity using the wobble clock, and perform recording using the wobble clock according to the determination of the wobble PLL detection circuit 15.

At the time of data recording, the data output from the system controller 10 is applied to the RISC processing unit 9.
, An error correction code is added, interleaved, and scrambled, output to the formatter 8, and stored in a FIFO memory inside the formatter. The system controller 10 is a formatter 8
When the formatter 8 reaches the recording target sector while reproducing the address, the formatter 8
The data in O is modulated, and the modulated data is output to the recording pulse generation circuit 7 while adding VFO, SYNC, and the like. However, if the output of the wobble PLL detection circuit 15 indicates that the wobble PLL is not synchronized, the recording is not performed or the recording is performed by the reference clock. If the wobble PLL detection circuit 15 detects out-of-synchronism during the recording by the wobble clock, the recording is stopped or interrupted, and the system controller 1
0 indicates that a recording error has occurred, and a recording retry is performed or a block in which a recording error has occurred is replaced with a spare area. The recording pulse generation circuit 7 processes the modulated data output from the formatter 8 into pulses for actually emitting a laser,
The laser is driven by the laser drive circuit 16 to perform recording on the optical disc 1.

(Embodiment 1) FIG. 2 is a diagram showing the details of the wobble PLL detection circuit 15 of FIG. 1 in the first embodiment, 17 is a wobble frequency error detection circuit, and 18 is a wobble PLL state output circuit. is there. The wobble frequency error detection circuit 17 detects a rising pulse of the wobble binarized signal, and outputs a synchronization detection signal when a pulse whose cycle T is within the range of the number of wobble clocks 186-a to 186 + a continues b times. The period T of the rising pulse of the wobble binary signal is equal to the number of wobble clocks 186 + c.
Are repeated d times or the number of wobble clocks 186-c is d
If it is repeated consecutively, an out-of-sync detection signal is output. According to the output of the wobble frequency error detection circuit 17, the wobble state output detection circuit 19 sets the wobble synchronization detection signal to the synchronization state when the synchronization detection signal is output, and outputs the wobble synchronization detection signal when the out-of-synchronization detection signal is output. Asynchronous state. The values of a, b, c, and d shown here are set by the system controller.

Next, the detailed operation of the embodiment of the present invention will be described. In the normal state other than during recording, a, b, c, d
Are set to values a0, b0, c0, and d0, respectively. In the data recording, the system controller 10 in FIG. 1 sets the values a1, b1, c1, and d1 to a, b, c, and d, respectively, immediately before the recording, and performs the actual recording operation. The values of b, c, d, and e are returned to a0, b0, c0, and d0. a1, b1, c
If the combination of 1, d1 is set to a value that maintains the accuracy required for the recording clock, the reliability of the recording data is maintained, and a, b, c, and d are set to the accuracy required for the recording clock except during recording. Set a value that does not detect even if it deviates slightly.

(Embodiment 2) FIG. 3 is a diagram showing details of the wobble PLL detection circuit 15 of FIG. 1 in a second embodiment. 19 is a wobble phase error detection circuit. The wobble phase error detection circuit 19 integrates the phase error between the wobble binary signal and the wobble clock divided by 186, and outputs a synchronization detection signal if the integrated value I is I <f, and I> g
If it is, an out-of-sync signal is output. The values of f and g shown here are set by the system controller.

In a normal state other than during recording, f and g are set to values f0 and g0, respectively. In the data recording, the system controller 10 in FIG. 1 sets the values f1 and g1 to f1 and g1, respectively, immediately before recording, and performs an actual recording operation. When the recording operation is completed, the values of f and g are set to f0 and g0. return. If the combination of f1 and g1 is set to a value that maintains the accuracy required for the recording clock, the reliability of the recording data is maintained, and f and g are slightly different from the accuracy required for the recording clock except during recording. Use a value that will not be detected.

(Embodiment 3) FIG. 4 is a diagram showing details of the wobble PLL detection circuit 15 of FIG. 1 in a third embodiment. Reference numeral 20 denotes a wobble sector error detection circuit. The wobble sector error detection circuit 20 measures an error D between a sector period determined by reproducing the physical ID and a sector period determined by counting the wobble clock, and D <h
If D> i, a sync detection signal is output. H and i shown here are set by the system controller.

In a normal state other than during recording, h and i are set to values h0 and i0, respectively. In data recording, the system controller 10 in FIG. 1 sets the values h1 and i1 to h and i, respectively, immediately before recording, and performs an actual recording operation. When the recording operation is completed, the values of h and i are set to h0 and i0. return. If the combination of h1 and i1 is set to a value that maintains the accuracy required for the recording clock, the reliability of the recording data is maintained, and h and i are slightly different from the accuracy required for the recording clock except during recording. Use a value that will not be detected.

(Embodiment 4) FIG. 5 is a diagram showing details of the wobble PLL detection circuit 15 of FIG. 1 in a fourth embodiment. 21 is a wobble synchronization detection circuit, and 22 is a wobble signal missing detection circuit. The wobble synchronization detection circuit 21
The first embodiment, the second embodiment, shown in the third embodiment,
Either a wobble frequency error detection circuit, a wobble phase error detection circuit, or a wobble sector error detection circuit, which outputs a wobble PLL synchronization detection signal and an out-of-synchronization detection signal. The wobble signal missing detection circuit 22 counts the cycle of the rising pulse of the wobble binary signal by dividing the reference clock by M (M is a natural number), and the value is j [j = missing detection time / (reference clock cycle × M). ], A missing detection signal is output. In a normal state other than during recording, j is set to a value of j0. In data recording, the system controller 10 in FIG. 1 sets the value of j1 to j immediately before recording, performs an actual recording operation, and returns the value of j to j0 when the recording operation is completed. If the value of j1 is set to a value such that missing is detected in a shorter time than a defect having a length that may cause an ab jump, erroneous recording due to the ab jump can be prevented.

FIG. 6 shows a case where there is a defect on the disk.
This is an example in which j = 8 is set during recording and j = 12 other than recording. In cases other than recording, even if there is a defect as shown in the figure, the wobble PLL detection circuit remains at "H" and is constantly used for constant linear velocity control by the wobble clock and generation of control signals, and the system is stable. It has become. In the recording, since the wobble binary signal is missing in the defective section during the recording, the output value of the wobble PLL detection circuit becomes "L" because the set value during recording is 8 pulses or more, and the wobble PLL shifts due to no signal. Even so, the recorded data is guaranteed by retry or replacement processing. Even if an ab jump occurs during a defect, the recording is stopped or interrupted, so that the reliability of the recorded data on the adjacent track is maintained.

(Embodiment 5) FIG. 7 is a diagram showing details of the wobble PLL detection circuit 15 of FIG. 1 in a fifth embodiment. 23 is a wobble pulse missing detection circuit. The wobble synchronization detection circuit 21 is the wobble frequency error detection circuit, the wobble phase error detection circuit, or the wobble sector error detection circuit shown in the first, second, and third embodiments. , And an out-of-synchronization detection signal. The wobble pulse missing detection circuit 22 counts the period of the rising pulse of the wobble binary signal by dividing the wobble clock by L (L is a natural number), and the value is k [k = the number of detected wobble pulse missing * (186 / L)], a loss detection signal is output. In a normal state other than during recording, k is set to a value of k0. In data recording, the system controller 10 in FIG. 1 sets the value of k1 to k immediately before recording, performs an actual recording operation, and returns the value of k to k0 when the recording operation ends. If the value of k1 is set to a value such that missing is detected in a shorter time than a defect having a length that may cause an ab jump, erroneous recording due to the ab jump can be prevented.

FIG. 8 shows a case where there is a defect on the disk.
This is an example in which k = 8 during recording and k = 12 other than recording. In cases other than recording, even if there is a defect as shown in the figure, the wobble PLL detection circuit remains at "H" and is constantly used for constant linear velocity control by the wobble clock and generation of control signals, and the system is stable. It has become. In the recording, since the wobble binary signal is missing in the defective section during the recording, the output value of the wobble PLL detection circuit becomes "L" because the set value during recording is 8 pulses or more, and the wobble PLL shifts due to no signal. Even so, the recorded data is guaranteed by retry or replacement processing. Even if an ab jump occurs during a defect, the recording is stopped or interrupted, so that the reliability of the recorded data on the adjacent track is maintained.

In the embodiment of the present invention, the value during recording and the value other than during recording are respectively changed from the system controller. However, the system has respective setting values other than during recording and during recording. It is easily presumed that the same effect can be obtained by the switching method.

In the present embodiment, the loss of the wobble is detected by binarization by a binarization circuit having a predetermined offset. However, a wideband push-pull tracking error signal or a signal after passing through a band-pass filter is detected. A similar effect can be obtained by measuring the length of a continuous period in which the amplitude is equal to or less than a predetermined value. In addition, loss detection can also be performed by integrating the amplitude level of the wideband push-pull tracking error signal or the signal after passing through the bandpass filter and binarizing the signal with a predetermined value.

It should be noted that wobble P is not used during recording or playback.
In a system in which the state of the LL detection circuit is ignored or the stability is not involved, it is easily presumed that the same effect can be obtained by a method of changing the set value during playback and other than during playback. Also, during recording, playback, other than that,
In a system in which the accuracy required for the reference clock is different from each other, the wobble PL is different between during recording, during reproduction, and other states.
It can be easily inferred from the present invention that the effect is exhibited by setting different setting values for the L detection circuit.

[0027]

According to the present invention, constant linear velocity control, generation of various control signals, and generation of recording signals using a clock synchronized by a PLL with a wobble signal obtained from a meandering track on an optical disk are performed. In recording, the reliability is high, and other than recording, there is an effect of stabilizing the system.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an optical disk system according to an embodiment.

FIG. 2 is a diagram showing details of a wobble PLL detection circuit according to the first embodiment;

FIG. 3 is a diagram illustrating details of a wobble PLL detection circuit according to a second embodiment;

FIG. 4 is a diagram illustrating details of a wobble PLL detection circuit according to a third embodiment;

FIG. 5 is a diagram illustrating details of a wobble PLL detection circuit according to a fourth embodiment;

FIG. 6 is a diagram showing a state of each signal when there is a defect in the fourth embodiment.

FIG. 7 is a diagram illustrating details of a wobble PLL detection circuit according to a fifth embodiment;

FIG. 8 is a diagram showing a state of each signal when there is a defect in the fifth embodiment.

[Explanation of symbols]

 Reference Signs List 1 optical disk 2 spindle motor 3 optical head 4 arithmetic circuit 5 servo control circuit 6 reproduction signal processing circuit 7 recording pulse generation circuit 8 formatter 9 RISC processing unit 10 system controller 11 polarity selection circuit 12 bandpass filter 13 wobble binarization circuit 14 wobble PLL circuit 15 Wobble PLL detection circuit 16 Laser drive circuit 17 Wobble frequency error detection circuit 18 Wobble PLL state output circuit 19 Wobble phase error detection circuit 20 Wobble sector error detection circuit 21 Wobble synchronization detection circuit 22 Wobble signal missing detection circuit 23 Wobble pulse missing Detection circuit

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5D044 BC06 CC04 DE32 DE46 DE61 GM19 5D090 AA01 BB04 CC01 CC04 DD03 DD05 FF07 FF37 FF38 GG09 GG23 GG26

Claims (4)

[Claims] An optical disk recording / reproducing apparatus for recording / reproducing data synchronized with a reference clock on an optical disk whose tracks meander in a radial direction, wherein the meandering and N (N is a natural number) of the reference clock are phase-synchronized. Control,
An optical disc recording / reproducing apparatus, comprising: means for judging a synchronous state of the meandering cycle and the N-frequency division of the reference clock based on different judgment criteria during recording and other than during recording. 2. An optical disk recording / reproducing apparatus for recording / reproducing data synchronized with a reference clock on an optical disk whose tracks meander in a radial direction, wherein the control is performed to synchronize the phase of the meandering cycle with the N frequency division of the reference clock. Wobble P to do
LL means, a wobble PLL detecting means for detecting a synchronous state of the meandering cycle and the N-frequency division of the reference clock according to a set value from a system controller, and different from the wobble PLL detecting means during recording and other than during recording. An optical disc recording / reproducing apparatus comprising a system controller for setting a set value. 3. An optical disk recording / reproducing apparatus for recording / reproducing data synchronized with a reference clock on / from an optical disk whose tracks meander in a radial direction, wherein the meandering is lost at different times or different times during recording and during non-recording. An optical disc recording / reproducing apparatus, comprising: means for judging the condition. 4. An optical disk recording / reproducing apparatus for recording / reproducing data synchronized with a reference clock on an optical disk whose tracks meander in a radial direction, wherein the control is performed to synchronize the phase of the meandering cycle with the frequency division by N of the reference clock. A wobble PLL means for detecting the wobble loss detecting means for detecting the meandering loss of a length or time longer than the set value from the system controller, and a different set value for the wobble missing detecting means during recording and other than during recording. An optical disk recording / reproducing apparatus having a system controller for setting.