JP2815283B2 - Data playback device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data reproducing apparatus, and more particularly, to an automatic adjustment control of a DC level of a data reproducing signal, an automatic gain control of a reproducing signal amplitude, and an automatic slice level in an optical information recording / reproducing apparatus. Adjustment function and VF
The present invention relates to a data reproducing circuit having a function of generating a synchronous clock of reproduced data by an O circuit and the like.

[0002]

2. Description of the Related Art In general, an optical information recording / reproducing apparatus divides a track of an optical disk into a plurality of sectors, and in each sector, an area (an ID section) in which a sector number and other information necessary for recording / reproduction are recorded. ) Is allocated to a data section for recording user data. In a conventional data reproducing circuit for reproducing information recorded in the ID section and the data section, for example, as described in Japanese Patent Application Laid-Open No. 62-40665 (literature 1), a plurality of data recorded on an optical disc are disclosed. The gap position provided between the sectors is detected by the reproduction signal, and the gain of the ID section and the data section following the gap is automatically controlled by timing based on the gap position, so that each reproduction signal has a fixed width. Is provided with an automatic gain control (AGC).

As described in Japanese Patent Application Laid-Open No. 1-229429 (Document 2), there are cases where data is written using a write flag signal recorded between an ID portion and a data portion. , And if not written,
A method of switching the control method of AGC has been proposed.

[0004]

The data reproducing circuit according to the prior art described in the above document 1 is effective for a write-once type optical information recording / reproducing apparatus, but the recording methods of the ID section and the data section are different. In a device having a significantly different signal amplitude ratio and DC level, for example, a magneto-optical recording device, no consideration is given to obtaining optimum gains in both the ID section and the data section, and the resolution in the data section is degraded. And so on. The data section has a state where data is recorded and a state where data is not recorded. If the gain of the data section is changed only at the timing from the ID section, a data setting error occurs. There is fear. With respect to this problem, a method of changing the gain of the data portion only when data is recorded is proposed under the condition of a write flag signal according to the above-mentioned document 2,
Control method of data section gain in recording format without write flag, control method in case of dropout in data, control method in case data section timing fluctuates due to disk eccentricity and motor rotation fluctuation, recording No consideration is given to a method of controlling the gain of the data portion at the time of erasing, a method of correcting the DC level, and the like.

[0005] Further, data recording / reproducing is performed with the recording capacity per unit length of a track on a disk kept constant irrespective of the distance from the center of the disk to the track, and with the rotation speed of the disk per unit time kept constant. So-called M
In the case of the CAV method, the bit cycle of the reproduced data is long in the inner track and shorter in the outer track, and the VFO unit that generates the reproduced clock needs to oscillate a clock in a wide frequency range. In general, a VFO circuit having a wide range of oscillation frequency has a VFO that oscillates at almost a single frequency.
As compared with the O circuit, it takes a longer time to synchronize with the data from the free-run state. In such a scheme,
When continuously reproducing a plurality of continuous sectors including a sector in which no data is recorded, it is desirable that the VFO circuit maintain the oscillation frequency without entering a free-run state.

Accordingly, an object of the present invention is to solve the above-mentioned problems of the prior art, and to provide a case where the reproduction amplitude and the DC level of the ID section and the data section are significantly different in a sector format without a write flag. It is also possible to perform gain control and DC level correction so that the amplitude and DC level of both are set to appropriate values, and to keep the oscillation frequency of the VFO circuit at a predetermined value even in a non-recorded sector. An object of the present invention is to provide a data reproducing device of an optical information recording / reproducing device that can be used.

[0007]

According to the present invention, there is provided an optical head for reading a signal from an optical recording medium having a sector including a prerecorded ID portion and a data portion in which arbitrary data can be recorded. In a data reproducing apparatus for reproducing data, a DC correction unit for controlling the level of a DC level of a signal read by the optical head, and a DC level of an output signal of the DC correction unit. A DC level detecting section for detecting, and when the ID section is detected, by instructing the DC correcting section to set a DC level of the ID section, the magnitude of the DC level detected by the DC level detecting section is determined. An ID part DC level determination part for controlling the DC correction part so as to obtain a value, and a DC part of the data part to the DC correction part when a head part of the data part is detected. By instructing the setting of the Le, magnitude of the DC level detected by the DC level detector is that a data section DC level determining section that controls the DC correction unit to a predetermined value.

A data reproducing apparatus for reproducing data from an optical head for reading a signal from an optical recording medium having a sector including a prerecorded ID section and a data section having a reproduction clock generating VFO section at the head. A gain control unit that controls a gain of a signal read by the optical head; a signal amplitude detection unit that detects an amplitude of an output signal of the gain control unit; and when the ID unit is detected, By instructing the gain control section to set the gain of the ID section, an ID section gain determination section that controls the gain control section so that the amplitude detected by the signal amplitude detection section becomes a predetermined value, and a head of the data section. A data head detection unit for detecting the VFO portion pattern as a portion; and a gain control portion when the VFO portion pattern as a head portion of the data portion is detected. By instructing the setting of the gain of the data portion, in which the amplitude detected by the signal amplitude detector is provided with a data unit gain determination section that controls the gain control unit to a predetermined value.

An optical head for reading a signal from an optical recording medium having a sector including a prerecorded ID portion and a data portion on which arbitrary data can be recorded, and a clock synchronized with the signal read by the optical head A VFO unit for generating a signal, wherein the VFO unit reproduces data when the ID unit is detected.
After instructing the VFO section to generate a clock synchronized with the playback signal of the ID section, and instructing the VFO section to generate a clock synchronized with the playback signal of the data section when the head of the data section is detected. And a control circuit for holding a frequency of a clock synchronized with a reproduction signal of the ID section when the head of the data section is not detected.

In a data reproducing apparatus for reproducing data from an optical head for reading a signal from an optical recording medium having a sector including a prerecorded ID portion and a data portion in which arbitrary data can be recorded, A first timing generation circuit for generating a control timing signal for reproducing the data portion by detecting a portion, and a control timing signal for reproducing the data portion by detecting a head portion of the data portion And a changeover switch for switching between the first timing generation circuit and the second timing generation circuit, wherein the changeover switch is set on the side of the second timing generation circuit. Data reproduction for switching to the first timing generation circuit side when reproduction cannot be performed It is the location.

An optical head for reading a signal from an optical recording medium having a sector including a data portion having a prerecorded ID portion and a VFO portion for generating a reproduction clock at the head;
A data reproducing apparatus for reproducing data by slicing a signal read by the optical head with a predetermined voltage value and binarizing the signal, wherein an input signal of the binarizing circuit is provided. A DC level detector for detecting the magnitude of the DC level of
An ID section DC level determination section for controlling a slice level of the binarization circuit in accordance with the magnitude of the DC level detected by the DC level detection section after instructing the value conversion circuit to set the DC level of the ID section; After instructing the binarization circuit to set the slice level of the data section by detecting the VFO section pattern, which is the head of the data section,
A data level DC level determining section for controlling a slice level of the binarization circuit in accordance with the magnitude of the DC level detected by the DC level detecting section.

When recording and erasing data, an instruction to set a DC level of the data section, an instruction to set a gain of the data section, an instruction to generate a clock to the VFO section in synchronization with a data section reproduction signal, None of the slice level setting instructions of the data section can be performed.

[0013]

The operation based on the above configuration will be described.

According to the present invention, when the ID part (sector mark or the like) is detected, the DC part of the ID part determines the DC level.
The correction unit is instructed to set the DC level of the ID unit, and the data unit DC level determination unit instructs the DC correction unit to set the DC level of the data unit when the head (head pattern) of the data unit is detected. By doing so, the DC correction unit is controlled so that the magnitude of the DC level always becomes a predetermined value (constant value). Both DC levels can be set to appropriate values. In this case, when no data is recorded, the head of the data part is not detected, so that no instruction is made to set the DC level of the data part. As a result, the DC level value for the previous sector is continuously held, and the DC level is incorrectly set. Is prevented.

When the ID section (sector mark or the like) is detected, the ID section gain determination section instructs the gain control section to set the gain of the ID section. When the section (head pattern) is detected, the gain control section is instructed to set the gain of the data section, thereby controlling the gain control section so that the amplitude always becomes a predetermined value (constant value). Even if the amplitude of the ID part and the amplitude of the data part are significantly different, both amplitudes can be set to appropriate values. In this case, when no data is recorded, the head of the data portion is not detected, so no instruction to set the data portion gain is made, and as a result, the gain value for the previous sector is kept and the erroneous gain setting is prevented. You. In addition, the head itself of the data portion is detected without using a special flag to detect whether or not data is recorded, so that a correct determination can be made with a simple configuration.

Further, when the ID section (sector mark or the like) is detected, the control circuit section instructs the VFO section to generate a clock synchronized with the reproduction signal of the ID section, and thereafter, starts the data section. When the first pattern is detected, VF
By instructing the O section to generate a clock synchronized with the reproduced signal of the data section, it is possible to always generate a clock having a frequency synchronized with the reproduced signal even when the bit periods of the reproduced signal are greatly different. Can be prevented from being in a free-run state. In this case, even when no data is recorded, the clock frequency synchronized with the reproduction signal of the ID section is maintained, so that the VFO circuit does not enter a free-run state.

[0017]

Embodiments of the present invention will be described below in detail with reference to the drawings.

The following embodiment is an example applicable to an optical disk, but the present invention is not limited to this, and can also be applied to an information reproducing circuit using another recording medium.

FIG. 2 is a diagram showing a format recorded on an optical disk used in an embodiment of the present invention. FIG.
Shows a recording format for one sector. This sector includes an ID section (pre-format section) 81 including a sector mark 90 and an index 89, a data section 84 including a VFO section 82 and data 83, and an ID section. 81 and V
And a GAP section 91 which is a non-signal area between the FO section 82. In the format shown in FIG. 2, the sector mark 90 is provided for convenience of description, but other mark signals or the like serving as a reference for the timing of the sector may not be located at the head of the ID portion. No problem.

FIG. 1 is a block diagram showing a configuration of a data reproducing circuit according to a first embodiment of the present invention. 1 includes an optical head 1 for reproducing data from the optical disk, a preamplifier 2 for amplifying a signal read by the optical head 1, and a DC component of an output signal 51 of the preamplifier 2 having a predetermined magnitude. DC correction unit 7 that adjusts the output to a constant level and outputs the same.
And an automatic gain control (AGC) unit 12 for amplifying the signal with a gain such that the output amplitude becomes constant, and a VFO unit 6 for generating a clock synchronized with the gain-controlled signal 56. The data reproducing circuit includes a DC level detector 8 for detecting the magnitude of the DC component of the signal 52, a sector mark detector 18 for detecting a sector mark 90 from the preamplifier output signal 51, The signals 54, 58, 62,
, 66, a data head detection unit 21 for detecting the head of the data part 84 from the preamplifier output signal 51 during a period when the data head detection gate signal 66 is at the H level, and a detection signal of the detection unit 21. A gate generation unit 22 that outputs signals 55, 59, and 63 at a timing from 65, and an ID unit DC level determination gate signal 54
Determines the magnitude of the DC level of the ID section signal from the detection signal 53 of the DC level detection section 8 during the H level.
D-section DC level determination section 9 and data section DC level for determining the magnitude of the DC level of the data section signal from detection signal 53 of DC level detection section 8 while data section DC level determination gate signal 55 is at H level. It comprises a judging section 10, a selector 11 for selectively inputting the outputs of the judging sections 9 and 10 to the DC correcting section 7 and controlling the DC level. Further, the data reproducing circuit includes a signal amplitude detecting section 13 for detecting the amplitude of the signal 56, and an ID section signal Part AG that determines the gain of
During the period when the C determination unit 14 and the data unit AGC determination gate signal 59 are at the H level, the detection signal 5 of the signal amplitude detection unit 13 is used.
7, a data section AGC determination section 15 for determining the gain of the data section signal, and a selector 16 for selectively inputting the outputs of the determination sections 14 and 15 to the AGC section 12 and controlling the gain.
And Further, the data reproducing circuit includes an ID section VF
The OR gate 23 instructs the VFO unit 6 to instruct the VFO unit 6 to perform the VFO withdrawal timing by taking the logical sum of the O withdrawal instruction signal 62 and the data portion VFO withdrawal instruction signal 63 and outputting the VFO withdrawal instruction signal 63.

In the data reproducing circuit configured as described above, the data signal read from the disk by the optical head 1 is amplified by the preamplifier 2 and then amplified.
The DC level is controlled by the DC correction unit 7,
After gain control is performed by the C section 12 and binarized in the VFO section, a synchronous clock is generated, discriminated and output. First, in the DC level correction unit 3, the DC correction unit 7 causes the magnitude of the DC component of the read signal to fluctuate greatly due to a difference in the recording method between the ID unit and the data unit and a variation between the optical disk and the optical head. VF
In order to prevent the O section 6 from malfunctioning, the DC level is controlled so as to be substantially constant. To prevent this, the ID section DC level determining section 9 and the data section DC level determining section 10 issue an instruction. The DC level is controlled.
In the AGC gain correction unit 4, the AGC unit 1
2 is to prevent the amplitude of the read data signal from fluctuating greatly due to the difference in the recording method between the ID section and the data section and the variation in the optical disk and the optical head, causing the VFO section 6 to malfunction. The amplitude is controlled so as to be substantially constant.
4, and the gain is controlled by the instruction of the data part AGC determination part 15. Below, this DC level control and A
The GC control will be described.

First, when the ID section 81 of the format shown in FIG. 2 is read by the optical head 1, the signal of the sector mark 90 of this ID section is output as the signal 51 amplified by the preamplifier 2, and the DC correction section 7 , The sector mark detection unit 18 and the data head detection unit 21. The sector mark detector 18 detects the sector mark 90
Outputs a sector mark detection signal 64 to urge the gate generation unit 19 to start timing. The gate generation unit 19 sends the ID unit DC level determination gate signal 54 to the ID unit DC level determination unit 9 at a predetermined timing. Send. The ID section DC level determination section 9 determines the DC level of the DC level detection signal based on the gate signal 54, and according to the determination result, the DC correction section 7 via the selector 11.
Instructs the correction amount of the DC level of the ID section. At this time, if the DC component of the output signal 52 of the DC correction unit 7 is not a predetermined magnitude, the DC level detection unit 8 detects this and the ID unit DC level determination unit 9 corrects the DC level of the DC correction unit 7. Control the amount to an appropriate value. Here, the sector mark 90 is used as a reference for the control signal of the ID section.
However, the reference may be generated by detecting another mark signal or the like, or a non-signal area between the end of data and the ID part.

The data part following the ID part has a state where data is recorded and a state where data is not recorded.
If the gain of the data portion is changed only at the timing from the ID portion, there is a possibility that a DC level setting error may occur in a data non-recording state. In order to cope with this, in the present embodiment, the data portion head detection gate signal 66 is generated based on the sector mark detection signal 64, and when data is recorded, the data head detection gate signal 66 is generated during the period when the gate signal 66 becomes H level. The detecting section 21 detects the pattern of the VFO section 82 and outputs a data head detection signal 65. The gate generation unit 22 generates the data part DC level determination gate signal 55 based on the detection signal 65, and
5 is input to the data part DC level determination part 10. The data section DC level determination section 10 detects the amount of correction of the DC level from the detection signal 53 of the DC level detection section 8 based on the gate signal 55 and controls the DC correction section 7 via the selector 11.

On the other hand, when the data is not recorded, the VFO section 82 in the data head detection section 21 during the period when the data section head detection gate signal 66 is at the H level.
Is not detected, the gate generation unit 22 is not activated. As a result, the data portion DC level determination gate signal 55 is at L level and does not instruct the data portion DC level determination portion 10 to correct the DC level.
The level determination unit 10 keeps the correction amount for the previous sector and prevents the setting error of the DC level from occurring.

As a method of detecting the VFO unit, a method of counting the number of pulses, a method of measuring the width and cycle of the pulse, and a method of detecting in combination with the detection of GAP are conceivable. Further, in the present embodiment, the method of detecting the head of the data part using the detection gate is used as an example, but the method of detecting the head of the data part on condition that the GAP part is detected, the method of detecting the head of the data part, A method is also conceivable in which the data pattern head is detected without using a detection gate by using the pattern (1) as a unique pattern.

Next, the operation of the AGC gain correction section 4 will be described. When detecting the sector mark 90, the sector mark detection unit 18 outputs a detection signal 64 to urge the gate generation unit 19 to start timing, and the gate generation unit 19 generates the ID portion AGC determination gate signal 58 at a predetermined timing. The ID is transmitted to the AGC determination unit 14. This gate signal 5
8, the ID section AGC determination section 14 determines the amplitude of the signal amplitude detection signal 57, and selects the selector 1
6, the AGC unit 12 is instructed on the gain of the ID unit.
At this time, if the amplitude of the output signal 56 of the AGC section is not a predetermined magnitude, the signal amplitude detection section 13 detects this and outputs
The gain of the AGC section 12 is controlled by the D section AGC determination section 14 so that the output amplitude of the AGC section 12 becomes an appropriate value (a predetermined amplitude).

The data part following the ID part has a state where data is recorded and a state where data is not recorded.
If the gain of the data part is changed only by the timing from the ID part, there is a possibility that an AGC setting error may occur in the data non-recording state. To deal with this, in this embodiment,
A data part head detection gate signal 66 is generated based on the sector mark detection signal 64, and when data is recorded, the data head detection part 21 outputs the data part head detection signal 65.
Is detected. The gate generation unit 22 generates a data part AGC determination gate signal 59 based on the detection signal 65, and inputs the gate signal 59 to the data part AGC determination unit 15. The data section AGC determination section 15 detects an appropriate gain value from the detection signal 57 of the signal amplitude detection section 13 based on the gate signal 59, and controls the AGC section 12 via the selector 16.

On the other hand, when no data is recorded, the data generation unit 21 does not detect the pattern of the VFO unit 82, so that the gate generation unit 22 is not activated. As a result, the data part AGC determination gate signal 59 does not instruct the data part AGC determination part 15 to perform AGC gain control, and the data part AGC determination part 15 holds the correction amount (gain value) for the previous sector, This prevents a gain setting error from occurring.

It should be noted that the determination units 9 and 10 by the selector 11
The switching timing of the selector 16 and the switching timing of the determination units 14 and 15 by the selector 16 are determined by the gate generation unit 19.
Can be determined by the timing signal generated in step (1).

Next, a control method of the VFO unit 6 will be described. The MCAV method of recording and reproducing data with a fixed recording capacity per unit length of a track on a disk irrespective of the distance from the center of the disk to the track and with a fixed number of rotations of the disk per unit time. ,
The bit cycle of the playback data is long on the inner track,
The VFO section, which becomes shorter on the outer track and generates a synchronization clock for the reproduced data, needs to oscillate a clock in a wide frequency range. In general, a VFO circuit having a wide oscillation frequency range has a longer time from the free-run state to the synchronization with data as compared to a VFO circuit which oscillates at almost a single frequency. In such a system, when reproducing data of a plurality of continuous sectors including a sector where data is not recorded, in a sector where data is not recorded, the VFO circuit does not go into a free-run state but remains in a free-run state. It is desirable to keep the oscillation frequency synchronized with the reproduced data. For this reason, in this embodiment, the ID section 81 generates the ID section VFO pull-in instruction signal 62 in the gate generation section 19 based on the sector mark detection signal 64, and outputs the VFO through the OR gate 23.
It instructs the unit 6 to generate a clock synchronized with the reproduction data. If data is recorded in the data section,
The data head detection unit 21 detects the pattern of the VFO unit 82, the gate generation unit 22 generates a data unit VFO pull-in instruction signal 63 based on the detection signal 65, and outputs the reproduced data to the VFO unit 6 via the OR gate 23. Indicates generation of a synchronized clock. If no data is recorded in the data portion, the data head detection portion 21 does not detect the pattern of the VFO portion 82, so that the timing of the gate generation portion 22 is not activated and the data portion pull-in instruction signal 63 does not become active. When the data part pull-in instruction signal 63 is supplied to the V
The signal is transmitted to the FO unit 6, and the VFO unit 6 keeps the oscillation frequency up to this point based on this instruction, thereby preventing the free-run state.

FIGS. 3 and 4 are time charts showing the operation of the data reproducing circuit (FIG. 1) according to the embodiment of the present invention. FIG. 3 shows a time chart in a state where data is recorded in the data part, and FIG. 4 shows a time chart in a state where data is not recorded in the data part. In FIG.
When the data head detection unit 21 detects the pattern of the VFO unit 82 of the preamplifier output signal 51 while the data head detection gate signal 66 is at the H level, a pulse signal is output as the data head detection signal 65 and the data head detection signal is output. The timing is generated based on 65 pulses, and the data part DC level determination gate signal 55 and the data part AGC are generated.
The determination gate signal 59 and the data section VFO pull-in instruction signal 63 are set.

In FIG. 4, when no data is recorded, no pattern is detected in the VFO section while the data head detection signal 66 is at the H level. Therefore, the timing is not activated in the gate generation unit 22, and the data unit D
C level determination gate signal 55, data part AGC determination gate signal 59, and data part VFO pull-in instruction signal 63
Is not set.

FIG. 5 is a time chart showing another effect of the embodiment of the present invention. In FIG. 5, I in the second, third, and fourth sectors of the preamplifier output signal 51 are shown.
The case where the dropout 85 occurs in the D section is shown. From the preamplifier output signal 51, a sector mark 90 is detected in the first sector, and a sector mark detection signal 64 is detected.
, And based on the pulse signal of the sector mark detection signal, the timing of the gate generation unit 19 is activated to generate the data detection gate signal 66. At the beginning of the ID portion of the second, third, and fourth sectors, there is a dropout, the sector mark 90 is not detected, and no pulse signal of the sector mark detection signal 64 is generated. The data start detection gate signal 66 for the third and fourth sectors is generated at predetermined timing intervals with reference to the pulse of the sector mark detection signal 64 for the first sector. The reproduced signal read from the disk has a frequency fluctuation due to the eccentricity of the disk and the rotation fluctuation of the motor. When the data head detection gate signal 66 is generated with a fixed clock, the data head detection gate 66 and the preamplifier output signal 51 , The timing is gradually shifted. The lower time chart in FIG. 5 is an enlarged view of the time axis of the timing at the beginning of the fourth sector. Although a timing shift 86 occurs between the preamplifier output signal 51 and the data head detection signal 66, the data part DC level determination gate signal 55, the data part AGC determination gate signal 59,
Since the data section VFO pull-in instruction signal 63 is generated based on the position of the detection pulse of the data head detection signal 65, the gate signals 55, 59, and 63 are transmitted to the GAP section 91 where no data is recorded. If the DC level or the gain of the AGC unit 12 is set incorrectly,
The FO unit 6 does not enter a free-run state.

FIG. 6 is a time chart showing another effect of this embodiment. FIG. 6 shows the V of the preamplifier output signal 51.
The case where a dropout 87 occurs at the head of the FO unit 82 is shown. Although the leading signal of the VFO unit 82 of the preamplifier output signal 51 is missing due to the dropout 87,
Data part DC level determination gate signal 55, data part AG
Since the C determination gate signal 59 and the data portion VFO pull-in instruction signal 63 are generated based on the position of the detection pulse of the data head detection signal 65 generated after the dropout 87 stops, the gate signals 55 and 59 are used. , And 63 can be set to avoid the dropout 87.

FIG. 7 shows a second embodiment of the data reproducing apparatus. In the present embodiment, another function is added to the control timing generator 5 of the embodiment of FIG. 1, and the configuration other than the control timing generator 5 is the same as that of FIG. In the configuration of FIG. 7, the sector mark detection unit 18 for detecting the sector mark 90 from the preamplifier output signal 51, and the signals 54, 58,
Gate generation unit 19 that outputs 62, 66, and 67
A data head detection unit 21 for detecting the head of the data part 84 from the preamplifier output signal 51 during a period when the data head detection gate 66 is at the H level; a detection signal 65 of the data head detection unit 21 and a data head embedding signal 67; Switch 24 for switching and outputting a signal, and a signal 5 obtained by timing the output signal 68 of the switch 24.
5, 59, and 63, and the gate generation unit 22 that outputs 63. This data head embedded signal 67 is
This pulse is generated at a predetermined timing from the sector mark 90, and is used instead of the data head detection signal 65.

FIG. 8 is a time chart when the changeover switch 24 of the embodiment of FIG. 7 is set to the data head detection signal 65 side. Noise 8 in preamplifier output signal 51
8, the noise 88 is erroneously detected as the data head, and the noise causes the data head detection signal 6 to be detected.
5 and the timing of the gate generation unit 22 is started by the pulse of the data head detection signal 65,
Data part DC level determination gate signal 55, data part AG
A C determination gate signal 59 and a data section VFO pull-in instruction signal 63 are generated. Thus, the noise 88 is generated in the GAP unit 91.
When the gate signals 55, 59 and 63 are generated based on the noise 88, the gate signals 55 and 59 protrude into the GAP unit 91 where no signal is recorded, and the DC There is a possibility that a setting error of the level and the gain of the AGC unit 12 may occur. When the gate signal 63 is turned on in the GAP section 91, it takes time to bring the VFO section 6 into a free-run state and synchronize the reproduced data with the clock again. Therefore, when the switch 24 is set to the data head detection signal 65 and the reproduction cannot be performed, the switch 24 can be switched to the data head embedded signal 67 to perform reading again.

FIG. 9 is a time chart when the changeover switch 24 in the embodiment of FIG. 7 is set to the data head embedded signal 67 side. When a noise 88 is generated in the preamplifier output signal 51, the noise 88 is erroneously detected as the data head, and a pulse of the data head detection signal 65 is generated by this noise. Is set,
Gate signals 55, 59, and 63 are generated based on the pulse of the data head embedding signal 67 generated at a predetermined timing from the sector mark 90. As a result, the gate signals 55, 59, and 63 are generated. Is GAP
It does not run over the part 91. That is, according to the embodiment of FIG. 7, even when noise occurs in the
An apparatus is provided which prevents the setting error of the DC level of the C correction section 7 and the gain of the AGC section 12 from occurring and prevents the VFO section 6 from being out of synchronization between the reproduction data and the reproduction clock.

FIG. 10 shows a third embodiment of the data reproducing apparatus. In the present embodiment, another function is added to the control timing generator 5 of the embodiment of FIG. 1, and the configuration other than the control timing generator 5 is the same as that of FIG. In the embodiment shown in FIG. 10, the sector mark 9 is output from the preamplifier output signal 51.
0, and a sector mark detector 18 for detecting the
8 from the detection signal 64 of FIG.
A gate generation unit 19 that outputs 8, 62, and 66;
The data head detection section 21 for detecting the head of the data section 84 from the preamplifier output signal 51 while the data head detection gate 66 is at the H level, and the recording instruction signal 69 and the erasure instruction signal 70 both instruct recording and erasing. A NOR gate 25 which outputs an H level when there is no
AND gate 26, which outputs a detection signal 65 of the data head detection unit 21 when the output signal 71 of the
The output signal 72 of the AND gate 26 is constituted by the gate generation unit 22 which outputs signals 55, 59 and 63 at a timing.

During recording and erasing, no signal is reproduced in the data section 84, but the preamplifier output signal 51
Since the signal level at the time of recording and erasing of the data portion is different from that at the time of normal reproduction, if the DC level of the data portion DC level determination portion 10 and the gain of the data portion AGC determination portion 15 are detected and set, the DC level and the automatic gain are reduced. There is a risk of being set incorrectly. In the embodiment of FIG. 10, the DC level of the data part DC level determination unit 10 and the gain of the data part AGC determination unit 15 are set at the time of recording and erasure so that data can be stably reproduced even in the sector immediately after recording and erasure. The function is added to prohibit the operation. At the time of recording and erasing, even if a data head is erroneously detected by the data head detector 21 due to noise on the preamplifier output 51 or the like, and a detection pulse is output to the output 65 of the detector 21, the output of the NOR gate 25 at the time of recording / erasing is output. Becomes L level and the NOR gate 2
5, the output of the AND gate 26 becomes L level, so that the timing of the gate generation unit 22 is not started, and the data part DC level determination gate signal 55, the data part AGC determination gate signal 59, and the data part pull-in are performed. The instruction signal 63 is not activated, thereby preventing the DC level and the gain of the data part from being set erroneously.

In the above embodiment, the DC correction unit 7 controls the DC level of the reproduction signal read by the optical head so that the ID level and the data level are always constant (same level). However, instead of such a DC correction section 7, the DC level of the reproduction signal read by the optical head is different between the ID section and the data section (generally, the ID section is higher than the data section). (A high level), and a binarization circuit (not shown) that slices and binarizes the ID portion and the data portion of the reproduction signal with predetermined voltage values corresponding to the respective DC levels. Can be provided. In this case, a DC level detection unit that detects the magnitude of the DC level of the input signal of the binarization circuit;
After instructing the binarization circuit to set the DC level of the ID section by detecting the ID section (sector mark), the binarization is performed in accordance with the magnitude of the DC level detected by the DC level detection section. A data level DC level determining section for controlling a slice level of the binarization circuit in accordance with the magnitude of the DC level detected by the DC level detecting section after instructing the setting of the slice level of the circuit. Thereby, the ID section and the data section can be sliced by the voltage values corresponding to the different DC levels set by the ID section DC level determination section and the data section DC level determination section, respectively, and can be binarized. Note that the circuit for slicing and binarizing can be provided in the VFO unit 6.

[0041]

As described above in detail, according to the present invention, when the ID part of the reproduced signal and the head of the data part are detected, the DC part of the ID part and the DC part of the data part are detected. By instructing the correction section to set the DC level of the ID section and the data section, the DC correction section is controlled so that the magnitude of the DC level always becomes a predetermined value. Even when the DC levels are largely different, an effect is obtained that both DC levels can be set to appropriate values and stable data reproduction can be performed. In this case, when there is no recording data, the setting of the DC level to the data section is not performed, and the immediately preceding DC level is held, so that the effect of preventing the erroneous setting of the DC level is obtained.

When the ID portion and the data portion gain determining portion detect the ID portion and the VFO portion pattern, which are the leading portions of the data portion, of the reproduced signal, the ID portion and the data portion determine the ID portion and the data portion. The gain control section controls the gain control section so that the output amplitude of the gain control section always becomes a predetermined value by setting and instructing the gain of the reproduction signal. Has an effect that the amplitude of the data can be set to an appropriate value and stable data can be reproduced. In this case, the immediately preceding gain is held even when there is no recording data, so that an effect of preventing erroneous gain setting is obtained. Further, instead of detecting a special format specific to data such as a recorded flag, a VFO for generating a reproduction clock is used.
By using the part pattern (in addition to the original function of generating the reproduction cook in the VFO part), it is possible to detect the head part of the data part and set the gain of the data part.

Further, the control circuit unit instructs the VFO unit to generate a clock in synchronization with the reproduction signal of the ID unit when the ID unit is detected.
Since the O section is instructed to generate a clock synchronized with the reproduced signal of the data section, a clock having a frequency synchronized with the reproduced signal can always be generated even when the bit cycle of the reproduced signal is greatly different. The effect that the free-run state can be prevented can be obtained. In this case, even when there is no recording data, the clock frequency synchronized with the reproduction signal of the ID section is maintained, so that the VFO
The effect of preventing the free-run state of the circuit can be obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a data reproducing circuit according to one embodiment of the present invention.

FIG. 2 is a diagram showing a recording format of an optical disk used in an embodiment of the present invention.

FIG. 3 is a waveform diagram showing an operation when data is recorded in one embodiment of the present invention.

FIG. 4 is a waveform diagram showing an operation when data is not recorded in one embodiment of the present invention.

FIG. 5 is a waveform diagram illustrating an operation when a dropout occurs in an ID section according to an embodiment of the present invention.

FIG. 6 is a waveform diagram showing an operation when a dropout occurs at the head of a VFO unit in one embodiment of the present invention.

FIG. 7 is a block diagram showing a data reproducing circuit according to another embodiment of the present invention.

8 is a waveform chart showing the operation of the embodiment of FIG.

FIG. 9 is a waveform chart showing the operation of the embodiment of FIG. 7;

FIG. 10 is a block diagram showing a data reproducing circuit according to still another embodiment of the present invention.

[Explanation of symbols]

 Reference Signs List 1 optical head 2 preamplifier 3 DC level correction unit 4 AGC gain correction unit 5 control timing generation unit 6 VFO unit 7 DC correction unit 8 DC level detection unit 9 ID unit DC level determination unit 10 data unit DC level determination unit 11 selector 12 AGC Unit 13 signal amplitude detection unit 14 ID unit AGC determination unit 15 data unit AGC determination unit 16 selector 18 sector mark detection unit 19 gate generation unit 21 data head detection unit 22 gate generation unit 23 OR gate 24 changeover switch 25 NOR gate 26 and gate 51 preamplifier Output signal 52 DC correction section output signal 53 DC level detection signal 54 ID section DC level determination gate signal 55 Data section DC level determination gate signal 56 AGC section output signal 57 Signal amplitude detection signal 58 ID section AGC determination gate signal 59 Data section AGC determination gate signal 61 VFO lead-in instruction signal 62 ID part VFO lead-in instruction signal 63 Data part VFO lead-in instruction signal 64 Sector mark detection signal 65 Data head detection signal 66 Data head detection gate signal 67 Data head embedded signal 68 Data part Timing reference signal 69 Recording instruction signal 70 Erase instruction signal 71 NOR gate output signal 72 AND gate output signal 81 ID section 82 VFO section 83 Data 84 Data section 85 Dropout 86 Timing shift 87 Dropout 89 Index 90 Sector mark 91 GAP section

──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Yutaka Narita 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Inside Hitachi Image Information Systems Co., Ltd. (72) Inventor Nobuhiro Yokoi 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa (56) References JP-A-1-229429 (JP, A) JP-A-62-235710 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) G11B7 / 00 G11B 20/14 351

Claims (5)

(57) [Claims] 1. A data reproducing apparatus for reproducing data, comprising: an optical head for reading a signal from an optical recording medium having a sector including a prerecorded ID portion and a data portion on which arbitrary data can be recorded. A DC correction unit that controls the magnitude of the DC level of the signal read by the head; a DC level detection unit that detects the magnitude of the DC level of the output signal of the DC correction unit; and the ID unit is detected. When the DC correction unit is instructed to set the DC level of the ID unit,
An ID section DC level determination section that controls the DC correction section so that the magnitude of the DC level detected by the level detection section becomes a predetermined value; and when the head section of the data section is detected, the DC correction section A data section DC level determination section for controlling the DC correction section so that the DC level detected by the DC level detection section becomes a predetermined value by instructing the setting of the DC level of the data section. A data reproducing apparatus characterized by the above-mentioned. 2. An ID section recorded in advance and a playback
An optical head for reading a signal from an optical recording medium having a sector including a data section having a lock generation VFO section ;
What is claimed is: 1. A data reproducing apparatus for reproducing data, comprising: controlling a gain of a signal read by the optical head.
Gain control unit, a signal amplitude detection unit that detects the amplitude of the output signal of the gain control unit, and when the ID unit is detected, by instructing the gain control unit to set the gain of the ID unit, An ID part gain determination part that controls the gain control part so that the amplitude detected by the signal amplitude detection part becomes a predetermined value; and a data head detection part that detects the VFO part pattern that is a head part of the data part. When the VFO section pattern, which is the head of the data section, is detected, by instructing the gain control section to set the gain of the data section, the amplitude detected by the signal amplitude detection section becomes a predetermined value. A data reproducing apparatus comprising: a data section gain determination section for controlling the gain control section as described above. 3. An optical head for reading a signal from an optical recording medium having a sector including a prerecorded ID portion and a data portion on which arbitrary data can be recorded, and a clock synchronized with the signal read by the optical head V that generates the signal
A data reproducing apparatus for reproducing data, comprising: when the ID section is detected, instructing the VFO section to generate a clock synchronized with a reproduction signal of the ID section. When the head portion is detected, the VFO unit is instructed to generate a clock synchronized with the reproduction signal of the data portion. When the head portion of the data portion is not detected, the frequency of the clock synchronized with the reproduction signal of the ID portion is detected. A data reproducing apparatus, comprising: a control circuit unit for holding the data. 4. A data reproducing apparatus, comprising: an optical head for reading a signal from an optical recording medium having a sector including a prerecorded ID portion and a data portion on which arbitrary data can be recorded, and reproducing data; A first timing generation circuit for generating a control timing signal for reproducing the data portion by detecting a portion; and a control timing signal for reproducing the data portion by detecting a head portion of the data portion. And a changeover switch for switching between the first timing generation circuit and the second timing generation circuit , wherein the changeover switch is configured to generate the second timing generation circuit.
If playback cannot be performed by setting to the roadside, the first
A data reproducing apparatus characterized by switching to a timing generation circuit side . 5. An ID section recorded in advance and a playback clip at the beginning.
An optical head for reading a signal from an optical recording medium having a sector composed of a data section having a lock generation VFO section, and a binarization for slicing the signal read by the optical head with a predetermined voltage value and binarizing the signal A data reproduction device for reproducing data, comprising: a DC level detection unit for detecting a magnitude of a DC level of an input signal of the binarization circuit; and a DC level detection unit for detecting the ID unit. I
After instructing the setting of the DC level of the D section, an ID section DC level determining section for controlling a slice level of the binarization circuit according to the magnitude of the DC level detected by the DC level detecting section; After instructing the binarization circuit to set the slice level of the data section by detecting the VFO section pattern at the head , the binarization is performed according to the magnitude of the DC level detected by the DC level detection section. A data reproducing apparatus, comprising: a data section DC level determining section for controlling a slice level of a circuit.