JPH11144253A - Recording signal demodulation method and optical disk device using it - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a demodulation method strong for fluctuation in a slice level even in a distinctive circuit constituted of a single PLL. SOLUTION: The detected edge data 101 are inputted to the PLL 102, and a synchronizing clock 104 and the distinctive data 103 are detected. The distinctive data 103 are separated to the front edge data and the rear edge data by a data separation circuit 105, and are delayed by shift registers 109, 110 to be supplied to an edge interval detection circuit 113. A write-in address control circuit 114 detects a synchronizing pattern from a detection result of an edge interval, and judges the presence and the direction of the fluctuation of the slice level in a data part held between two synchronizing patterns to correct properly the distinctive data.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a recording signal demodulation method suitable for reproducing a digital data signal recorded on an optical disk, and an optical disk apparatus using the same.

[0002]

2. Description of the Related Art When digital data is recorded as a pit train on an optical disk and reproduced, the data is modulated and recorded so that the abundance ratio of pits and non-pits is 50%.
A means for reproducing recorded data by slicing a reproduced signal from a pickup at its average DC level is often used. This type of reproducing means can sufficiently suppress a relatively low-frequency component corresponding to the sector period among the fluctuations in the average DC level of the reproduced signal. However, in an actual optical disc, a level change having a relatively high frequency component such as a change in recording conditions and a change in disc reflectivity occurs. In these cases, the suppression becomes insufficient, and the reproduced signal may be sliced at a position outside the original slice level.

To solve such a problem, for example, a known technique disclosed in Japanese Patent Application Laid-Open No. 2-81324 is
The above-described slice level correction is performed only in a specific pattern portion in which the ratio of pits and non-pits added to the head of a data sector is 50%. By performing high-speed negative feedback of the phase difference between the synchronized PLL clock and the reproduced data to the slice level, stable data demodulation including the PLL is realized.

A conventional technique for controlling a slice level by feeding back a phase difference from a PLL clock synchronized with reproduced data is disclosed in Japanese Patent Laid-Open No. 62-254.
514. The details of this known technique will be described below with reference to FIG.

In FIG. 9, an analog signal 401 reproduced from a pickup (not shown) includes a comparator 402 and positive and negative envelope detection circuits 403 and 40.
4 is input. These envelope detection circuits 403 and 404
Detects the positive and negative envelope levels of the reproduced analog signal 401, respectively. Output signals from the positive and negative envelope detection circuits 403 and 404 are output from a voltage dividing resistor 405 connected between its output terminals.
And after passing through a subtractor 406,
The slice level is input to the inverting terminal of the comparator 402.

The output A of the comparator 402 is a binary digital signal of a high level and a low level, as shown in FIG. 10, that is, if the reproduced analog signal 401 is on the positive side of the slice level. High level, low level if below. The output A of the comparator 402 is further input to an edge detector 407, where a pulse signal B is generated at the rising edge of the digital signal (output A).

The pulse signal B is input to a phase comparator 408, which outputs a phase difference signal from the rising timing of a clock signal generated from a voltage controlled oscillator (VCO) 409. The high-frequency component of this phase difference signal is removed by a low-pass filter (LPF) 410, and the VCO
409 is input to the control terminal. In other words, the clock signal C synchronized with the digital signal A detected by the comparator 402 is
Extracted as L clock. On the other hand, a flip-flop 411 whose input terminal is connected to the output of the comparator 402 outputs the comparator output A to the PLL clock C
To obtain an output indicated by symbol D in the figure. Then, the output D is input to the non-inverting (+) terminal of the differential amplifier 412.

On the other hand, the inversion (−) of the differential amplifier 412
The comparator output A is directly input to the terminal, and therefore, the error signal E corresponding to the slice level setting deviation is output from the output of the differential amplifier 412. The error signal E is input to the subtractor 406 after the high-frequency component is further removed by the LPF 413, whereby the slice level obtained from the envelope signal level is corrected.

The fact that the slice level can be corrected by such a circuit configuration will be apparent from the time chart waveform diagram of FIG. 10 showing the signal waveforms of each part in the above-described circuit configuration. Note that the time chart waveform shown in FIG. 10A shows the waveform of each part when the slice level rises and the period of the high level of the comparator output A is shortened. It can be seen that the DC level (dashed line) is increasing.

On the other hand, the time chart waveform shown in FIG. 10 (b) shows a case where the slice level has decreased and the period of the high level of the comparator output A has become longer.
The average DC level of the error signal E has dropped. Therefore,
By subtracting the signal proportional to the error signal E from the slice level obtained from the envelope signal level, the slice level can be controlled to the optimum level.

[0011]

As described above, in the above-mentioned prior art, the slice level can be controlled by feeding back the phase difference from the PLL clock synchronized with the reproduced data. In the case where an EFM modulation code generally used in a CD or the like and a modulation code of the series are used, there are a plurality of slice levels at which the phase error signal of the PLL becomes zero. As a result, a phenomenon in which the phase error signal of the PLL becomes zero at an incorrect slice level and the PLL is locked, that is, a pseudo locking phenomenon occurs.

This phenomenon will be briefly described with reference to FIG. The signal waveform 501 shown on the left side of FIG.
7) An eye pattern of a reproduced signal from a pit row recorded by applying NRZI modulation to a modulation code having a minimum run length of 2, such as RLL or EFM. In this case, when the slice is performed at the levels 502, 503, and 504 indicated by the dashed line in the drawing, the eye opening of the detection window Tw is seen. That is, not only the original level 502,
Even when the slice level is pulled into the other levels 503 and 504, both the phase and the frequency are stable for the PLL. Thus, levels 503, 50
The state in which the slice level is pulled into 4 and the PLL is locked is called pseudo lock.

On the right side of the figure, the envelope of the reproduced signal of the sector is shown in an enlarged manner, and here, the eye pattern on the left side of the figure and the signal level are displayed together. In the envelope of the reproduced signal of this sector, reference numerals 505, 507, 509, and 511 denote synchronization pattern portions, which are embedded between user data 506, 508, and 510 having a fixed data capacity.

In the envelope of the reproduced signal of this kuta, the slice level 512 is at the normal level 502 in the section A (indicated by an arrow below) and the section C. However, in the section B, it follows the lower level 503 (the level of the pseudo lock). However, this section B
Then, the PLL does not run away and the abnormality cannot be known. However, all of the latter half of 506 and 508 which are user data corresponding to this section B, and
The data in the first half of 510 has been incorrectly discriminated and these user data are in error.

In the illustrated example, the user data 5
Reference numeral 10 indicates that the lock has returned to the normal locked state in the latter half thereof due to some trigger. However, if there is no such trigger, most of the reproduced data will be discriminated in the pseudo lock state, and a normal error will occur. It is expected that correction (ECC) will not be possible.

As described above, the prior art described above does not sufficiently consider a pseudo-lock phenomenon that occurs due to some defect or the like, and does not take sufficient measures against it. is there.

In view of the foregoing, an object of the present invention is to provide a method for demodulating a recording signal in an optical disc apparatus for reproducing a CD or the like using an EFM modulation code or a series of modulation codes. Even if a pseudo lock occurs, it is reliably detected, the data in the pseudo locked area is corrected, and thus a demodulation method capable of reducing a demodulation error and an optical disc using the same. It is to provide a device.

[0018]

According to the present invention, in order to achieve the above object, known data is embedded in user data to form recording data, and bit "1" of the recording data is used.
In a method of demodulating the recording data from a pit row in which the recording data is recorded in correspondence with the leading edge and the trailing edge of the pit, the recording data is obtained from position information of a leading edge or a trailing edge of a reproduced signal of the pit row. A first step of discriminating the data into leading edge data and a trailing edge data, a second step of retaining the discrimination data obtained in the first step, and a discrimination obtained in the first step A third step of detecting position information of a leading edge or a trailing edge in which the known data is embedded from data, wherein the discrimination held in the second step is performed based on at least two subsequent discrimination results of the known data. A recording signal demodulation method characterized in that the recording data is demodulated by correcting a relative positional relationship between data corresponding to a leading edge and a trailing edge in the obtained data.

According to the present invention, in order to achieve the above object, known data is embedded in user data as recording data, and bit "1" of the recording data corresponds to the leading edge and the trailing edge of the pit. In an optical disc apparatus for demodulating the recorded data from the pit train on which the recording data is recorded, the recording data is converted to the leading edge data and the trailing edge from the position information of the leading edge or trailing edge of the reproduced signal of the pit train. First means for discriminating data from data, second means for holding discrimination data obtained by the first means, and the known data embedded from the discrimination data obtained by the first means. Third means for detecting the position information of the leading edge or the trailing edge, and from a result of discrimination of at least two succeeding known data, a leading edge in the discriminated data held by the second means. And means for correcting the relative positional relationship of the data corresponding to the edge, the optical disk apparatus characterized by demodulating the recording data is provided.

[0020]

Embodiments of the present invention will be described below in detail with reference to the accompanying drawings. First, the concept of data resynthesis used in the present invention will be described with reference to FIGS. The circuit for performing such data re-synthesis and its operation are described below.
For example, it is disclosed in JP-A-2-183471.

That is, the concept of data resynthesis is used in the present invention. First, a circuit and an operation thereof will be briefly described with reference to FIGS. FIG.
FIG. 9 is a block diagram of a reproduced data synthesizing circuit for performing data re-synthesis. In this case, first, an analog reproduced signal reproduced from a pickup (not shown) is first converted to the above-described FIG.
As shown in, the edge data of the signal obtained by binarization by comparison with the comparator is separated into a rising edge and a falling edge, and after performing independent discrimination processing, respectively, using a synchronization pattern, The final discrimination data is obtained by realigning the phase shift between the leading edge discrimination data and the rear edge discrimination data in bit units.

Incidentally, in an optical disc apparatus of a type in which a pit or a non-pit length is recorded on an optical disc, if the slice level is not precisely adjusted according to the change in the length of the pit or the non-pit, , The relative positional relationship between the front edge and the rear edge changes.
On the other hand, the edge interval between the front edges or between the rear edges does not change even if the slice level slightly changes, so that the respective detected edge pulses 601, 60
By providing two PLLs 603 and 604 for 2, the data discrimination can be performed stably. At this time, the slice level of the comparator may be adjusted to the average DC level of the VFO pattern provided at the head of the data, and then held. These two PL
Data 605 and 606 discriminated from L603 and 604
Are the synchronous clocks 607 and 608 output from them.
At the same time, it is sent to the pattern detection circuits 609 and 610.

Next, the processing of the pattern detection circuit will be described.
This will be described with reference to the time chart waveform shown in FIG.
In this example, for simplicity, the synchronization pattern is 3 Tw / 3
The VFO pattern is Tw. However, since the slice level of the output signal (VFO pattern) from the comparator fluctuates, the duty is broken as is apparent from the drawing.

The pattern detection circuits 609 and 610 output data "1" immediately after the signals of the front edge data (DATA1) and the rear edge data (DATA2) together with the pattern detection signals 611 and 612 as detection pulses 613 and 614. . On the other hand, register A619, register B62
Addresses 617 and 618 of 0 correspond to the detection pulse 61
Count-up is started from the point in time when 3,614 is input. Here, in the above-mentioned VFO pattern, since the leading edge data and the trailing edge data have a phase difference of three clocks, the write address of the register B 620 is +3 with respect to the write address of the register A 619.

That is, in the waveform of the time chart of FIG. 7, the write addresses of the register A 619 and the register B 620 are "0" and "3", respectively. Next, the data written in the register A 619 and the register B 620 is read out using a common address. The register A and B output control circuits 621 perform this control. That is, when the address of the register B 620 is counted up to “4”, the data generation permission signal 62
5 is generated, and the data generation control circuit 629 is instructed that the data sequence following the completion of reproduction / synthesis is completed.

Next, the data generation control circuit 629 sequentially reads out the outputs of the register A 619 and the register B 620 according to the common address 624, and outputs the data 627 by taking the logical sum of the read out outputs.

As described above, when writing the two discrimination data strings of the leading edge and the trailing edge into the two registers, the write address is given a time difference of clock unit so that a known pattern is reproduced. For example, the result of reading the data of each of the two registers at a common address becomes a normal discrimination data string.

Next, a recording signal demodulation unit in the optical disk device according to the embodiment of the present invention will be described with reference to FIG. As is clear from the figure, for example, the leading and trailing edge data 1 obtained from the slice circuit as shown in FIG.
01 is first supplied to the PLL circuit 102, from which the data 103 and the clock (CL
K) 104 is output. These two signals are supplied to the data separation circuit 105 and are converted into discrimination data of the leading edge and the trailing edge. The data separation circuit 10
FIG. 2 shows a specific configuration example of No. 5.

In FIG. 2, discrimination data (A) 201
Is delayed by one clock by the delay circuit 202, and the adder 203 executes mod2 addition with the original data (A). Here, the mod2 addition is a remainder term modulo 2, and specifically, 0 + 0 = 1 + 1 = 0,1
The calculation rule of + 0 = 0 + 1 = 1 is followed.

As a result, assuming that the data string after the addition of mod 2 is (B), the AND gate 204 performs a logical product of (A) and (B) and outputs the leading edge data 106. The AND gate 206 performs a logical product of (B) and (A) inverted by the inverting circuit 205, and outputs the trailing edge data 107. Also, the data separation circuit 105
The clock 104 described above may be used as the PLL clock 108 output from. It can be easily understood by those skilled in the art from the specific example of the operation chart shown in FIG. 3 that the leading edge data and the trailing edge data can be separated by this circuit.

Here, returning to FIG. 1 again, the leading edge data (DAT
A1) 106, trailing edge data (DATA2) 107
Are synchronized with the PLL clock 108, respectively.
It passes through a shift register A109 and a shift register B110. The lengths of these shift registers are determined so as to substantially match the user data and the data amount of the synchronization pattern added to both ends thereof. Note that a delay element such as a RAM may be used instead of these shift registers. From these shift registers A and B, the leading edge data 106 and the trailing edge data 107 are delayed data, that is, the delayed leading edge data (D-DAT
A1) After the delay with 111, the edge data (D-DATA)
2) 112 is output.

The preceding and following edge data 106 and 107
Next, the edge data 111 and 112 before and after the delay and the clock 108 are supplied to the edge interval detection circuit 113 and the write address control circuit 114, whereby
Write addresses 117 and 118 to the register A115 and the register B116 are determined.

As a result, the delayed leading edge data (D-DATA1) 111 is stored in the registers A115 and B116 in accordance with the determined write address.
After that, the edge data (D-DATA2) 112 is sequentially written. After that, after the write addresses 117 and 118 are determined, the registers A and B output control circuits 122 send the data generation permission signal 120 to the data generation control circuit 1.
21 and the data generation control circuit 121
The output of the register A115 and the register B116 is sequentially read out by the common address 119, and the output of the data 123 is obtained by taking the logical sum of both outputs in the same manner as the circuit of FIG.

Here, specific circuit configurations of the edge interval detection circuit 113 and the write address control circuit 114 are shown in FIG.
FIG. 5 shows time chart waveforms for explaining the operation of these circuits.

First, the edge interval detection circuit 113 includes four edge interval detection circuits 301, 302, 303, and 304.
Consists of Of these, 301 and 303, 302 and 304
Have the same circuit configuration. That is, the edge interval detection circuits 301 and 303 exist by counting the edge interval between the leading edge data 106 and the trailing edge data 107 by the PLL clock 108, that is, in the leading edge data pulse 106 and the trailing edge data pulse 107. The edge spacing is measured respectively.

In this embodiment, the synchronization pattern is detected by using a known combination of pits and non-pits existing in the synchronization pattern. Here, for example, as a known pattern of a pit and a non-pit, a (14 Tw−4 Tw) pattern of 100000000000000010001 will be described as an example. It is assumed that this pattern does not come out of the rules of the modulation code used.

The edge interval detecting circuit 301 detects the fixed length pattern having a length of 18 clocks. Note that the first "1" in this known pattern may be the leading edge of the recording pit or the trailing edge, so that the output is the detection signal 30 for the leading edge.
5 and a detection signal 306 for the trailing edge are output, respectively. For this purpose, a dedicated counter circuit (not shown) is provided for each of the leading edge data and the trailing edge data. Then, the counter outputs of these counter circuits are compared with a fixed value "18", and if they match, pulse signals having a fixed width are output as detection signals 305 and 306.

FIG. 5A shows a case where a fixed length pattern exists at the front edge interval, and a pulse signal indicating that a fixed length pattern having a length of 18 clocks has been detected appears in the detection signal 305 for the front edge. ing.

Similarly, FIG. 5B shows a case where a fixed length pattern exists at the trailing edge interval, and the detection signal 306 for the trailing edge indicates a pulse indicating that a fixed length pattern having a length of 18 clocks has been detected. A signal is appearing.

Next, the edge interval detection circuit 302 also counts the edge interval from the leading edge data to the next trailing edge data by the PLL clock 108, and latches the edge interval at the rising timing of the detection signal 305 or 306. Output M data 309 and S data 310.

Here, the edge interval detection circuit 3
M data 309 and S data 310 output from 02
Will be described. These M data and S data have a fixed length pattern at the leading edge interval (FIG. 5).
(See (a)), if the slice level is normal,
M data = “14” and S data = “4”. On the other hand, when a pseudo lock occurs, these data are increased or decreased by ± 1.

The M data and S data have a fixed length pattern at the trailing edge interval (FIG. 5).
(B)), if the slice level is normal, M
When data = "4", S data = "14". On the other hand, when the pseudo lock occurs, the increase or decrease of ± 1 occurs in the same manner as described above.

The edge interval detecting circuits 303 and 304
Is the same circuit configuration and operation as above,
Here, the description is omitted. However, as described above, the data lengths of the shift register A 109 and the shift register B 110 are set in accordance with the cycle of the user data. As a result, a fixed length pattern is detected.

As described above, whether the synchronization pattern is detected by the edge interval detection circuit 113 is the leading edge data or the trailing edge data, the slice level is normal, or a pseudo lock occurs. Is determined. Then, the detection signal and detection data generated from the edge interval detection circuit 113 are sent to the write address determination units 313 and 314 of the address control circuit 114, respectively, where the temporary determination of the write address is performed.
In this method, write address candidates are respectively determined based on detection results of two synchronization patterns detected by the synchronization patterns at both ends of a certain user data area.

Next, the write address judging section 31
Operations 3 and 314 will be described in detail. Based on the detection signals 305 and 306 sent from the edge interval detection circuit 301, the write address determination unit 313 detects whether the synchronization pattern is detected by leading edge data or trailing edge data. Further, the edge interval detection circuit 3
Based on the M data 309 and the S data 310 sent from 02, it is determined whether or not the pseudo lock is performed.

Here, for example, when a detection pulse is present in the detection signal 305 (see FIG. 5A), it is understood that "18" has been detected from the leading edge data, and the M data is "14". , S data is “4”, it is a normal operation. That is, the M data 309 is "1"
4 ", if the S data 310 is" 4 ", it can be understood that the slice level is set to the normal level.
Write addresses 117 and 118 to the register A115 and the register B116 (see FIG. 1) are both set to "0".
In the following description, the write address to the register A and the write address to the register B are abbreviated using (), and, for example, in the above case, these are expressed as (0, 0). I do.

On the other hand, if the M data 309 is "13" and the S data 310 is "5", the trailing edge data is advanced by one clock due to the pseudo lock, so that writing to the registers A and B is performed. Address (0, 1)
And Conversely, if the M data 309 is “15” and the S data 310 is “3”, it means that the trailing edge data is delayed by one clock, so it is set to (1, 0).

When a detection pulse is present in the detection signal 306 (see FIG. 5B), it is found that "18" is detected from the trailing edge data, and the S data is "1".
The normal operation is that "4" and the M data are "4".
Therefore, the M data 309 is “4” and the S data 310
Is "14", it can be understood that the slice level is set to the normal level, so that (0, 0) is set.

On the other hand, if the M data 309 is "5" and the S data 310 is "13", the leading edge data is advanced by one clock due to the pseudo lock.
(1, 0). Conversely, the M data 309 is "1"
5 "and S data 310 of" 3 ", the leading edge data is delayed by one clock, so (0,
1).

The write address judging section 314 shown in FIG.
Is the same as the operation of the write address judging section 313, and the detailed description thereof is omitted. By the above operation, the write address candidate 315,
316 is sent to the write address determination unit 317.

Thereafter, the write address determining section 31 shown in FIG.
At 7, the write address is finally determined by looking at both the write address candidates 315 and 316. The criterion for this determination will be described below with reference to the envelope of the reproduced signal of the sector shown on the right side of FIG.

(Case 1) Write Address Candidate 31
If both 5 and 316 are (0, 0), it is determined that the slice level is normal in the user data area during this period, and the write addresses 117 and 118 to the register A 115 and the register B 116 are both set to “0”. .

(Case 2) Write Address Candidate 31
When both 5 and 316 are (0, 1), it is determined that the pseudo lock is performed at the same slice level in the user data area during this period, and the register A 115 and the register B 1
16 is set to "0",
1 ". Write address candidates 315, 316
Are also (1, 0). That is,
In this case, the user data 508 of the reproduction signal envelope in FIG. 8 corresponds to this case.

(Case 3) Write Address Candidate 31
5, 316 are (0, 0) and (0, 1), or (0, 0) and (1, 0), or (0,
1) and (0,0) or (1,0) and (0,0)
In the user data area during this time, there is a high probability that a pseudo lock phenomenon has occurred on the way. Therefore, the write address 1 to the register A115 and the register B116
17 and 118 are set to "0" and "0", and no data correction is performed. This corresponds to the user data 506 and 510 of the reproduction signal envelope in FIG.

(Case 4) Write Address Candidate 31
In the case where 5, 316 are (0, 1) and (1, 0), or (1, 0) and (0, 1), respectively, in the user data area between them, the pseudo lock Since the probability of occurrence of the phenomenon is high, the write addresses 117 and 118 to the register A115 and the register B116 are used.
Are set to "0" and "0", and no data correction is performed in this case as well. This is because, in the reproduced signal envelope of FIG. 8 described above, the slice level is changed from the pseudo lock level 503 through the normal level 502 to the opposite pseudo lock level 504.
Corresponds to this.

It will be apparent to those skilled in the art that a circuit that outputs the write addresses 117 and 118 in accordance with the criteria shown in the above four cases can be easily formed by, for example, a selector.

[0057]

As is apparent from the above detailed description, the CD using the EFM modulation code or the modulation code of the series is used.
In the method of demodulating recorded signals in an optical disc device for reproducing data, etc., even if the above-mentioned pseudo lock occurs, the data can be reliably detected and corrected in the pseudo-locked area, thereby reducing demodulation errors. In addition, it is possible to provide a recording signal demodulation method that is resistant to a change in slice level even if the discrimination circuit is configured by a single PLL, and an optical disk apparatus using the same.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an overall configuration of a data demodulation circuit according to the present invention.

FIG. 2 is a block diagram showing a specific circuit configuration of a separation circuit for leading and trailing edge data in the data demodulation circuit.

FIG. 3 is a diagram illustrating the operation of a leading and trailing edge data separation circuit in the data demodulation circuit.

FIG. 4 is a block diagram showing a specific circuit configuration of an edge interval detection circuit and a register write address control circuit in the data demodulation circuit.

FIG. 5 is a time chart waveform chart for explaining operations of an edge interval detection circuit and a register write address control circuit in the data demodulation circuit.

FIG. 6 is a block diagram of a reproduced data synthesizing circuit for explaining the concept of data re-synthesis used in the present invention.

FIG. 7 is a time chart waveform diagram of a reproduced data synthesizing circuit for explaining the concept of data re-synthesis used in the present invention.

FIG. 8 is an explanatory conceptual diagram for explaining a pseudo lock phenomenon that is to be solved by the present invention.

FIG. 9 is a block diagram illustrating an example of a conventional data demodulation circuit.

FIG. 10 is a time chart waveform chart for explaining the operation of the conventional data demodulation circuit.

[Explanation of symbols]

 102 PLL 105 front and rear edge data separation circuit 109, 110 shift register, 113 edge interval detection circuit 114 register write control circuit 106 data generation control circuit

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Koichi Hirose 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Inside the Multimedia Systems Development Division of Hitachi, Ltd. (72) Inventor Kuki Sugiyama Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa 292, Hitachi, Ltd. Video Information Media Division (72) Inventor Toshimitsu Kaku 292 Yoshida-cho, Totsuka-ku, Yokohama, Kanagawa Prefecture Hitachi, Ltd. Video Information Media Division (72) Inventor Toru Kawashima Totsuka-ku, Yokohama, Kanagawa 292 Yoshidacho Co., Ltd. Inside Hitachi Image Information System

Claims (2)

[Claims] 1. A method of embedding known data in user data to form recording data, and from a pit row in which the recording data is recorded in correspondence with a leading edge and a trailing edge of a pit in bit “1” of the recording data, the recording is performed. A method of demodulating data, a first step of discriminating the recording data into leading edge data and trailing edge data from position information of a leading edge or a trailing edge of a reproduced signal of the pit string; A second step of holding the discrimination data obtained in the step, and a third step of detecting position information of a leading edge or a trailing edge in which the known data is embedded from the discrimination data obtained in the first step. A relative position of the data corresponding to the leading edge and the trailing edge in the discriminated data retained in the second step from a discrimination result of the at least two subsequent known data steps. A recording signal demodulation method, wherein the recording data is demodulated by correcting the relationship. 2. A method of embedding known data in user data to form recording data, and from a pit row in which the recording data is recorded corresponding to a leading edge and a trailing edge of a pit in bit “1” of the recording data, the recording is performed. An optical disc device for demodulating data, a first means for discriminating the recording data into front edge data and rear edge data from position information of a front edge or a rear edge of a reproduced signal of the pit row; A second means for holding the discrimination data obtained by the means, and a third means for detecting position information of a leading edge or a trailing edge in which the known data is embedded from the discrimination data obtained by the first means. Means for correcting the relative positional relationship between the data corresponding to the leading edge and the trailing edge in the discriminated data held by the second means from at least two subsequent discrimination results of the known data. Means for demodulating the recording data.