JPH0528539B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a frame synchronization circuit, typically a frame synchronization circuit system in a demodulation circuit of an apparatus that records digital signals on a recording medium and reproduces them from the recording medium.

[Prior Art] Figure 3 is a block diagram of a frame synchronization circuit in a conventional demodulation circuit.
PROCESSING TO BE USED IN
“COMPACT”DISC DIGITAL AUDIO”
PLAYERS”, AN AUDIO ENGINEERING
Disclosed in SOCIETY PREPRINT 71st Convention 1982. In FIG. 3, a conventional frame synchronization circuit receives a digital signal applied to an input terminal 1, detects a frame synchronization signal included in the digital signal, and generates a frame synchronization detection signal.
A frame synchronization detection circuit 2 that generates SYNC receives the frame synchronization detection signal SYNC and a window signal SWIND from a selector 10 (described later), extracts the frame synchronization detection signal SYNC in response to the window signal SWIND, extracts the gate, and performs frame synchronization detection. The gate circuit 4 generated by the signal GSYNC starts counting operation in response to the gate extraction frame synchronization detection signal GSYNC, and every time a predetermined count is reached, an operation timing signal is generated and given to the window generation circuit 7. a first counter 6; and a window generation circuit that generates a window signal WIND that provides timing for extracting a frame synchronization signal in response to an operation timing signal from the first counter 6, and provides the window signal WIND to the second counter 9 and selector 10; 7 and the window signal from the window generation circuit 7
It receives WIND and the gate extraction frame synchronization detection signal GSYNC from the gate circuit 4, performs a counting operation in response to the window signal WIND, and resets the counting operation in response to the gate extraction frame synchronization detection signal GSYNC. A second counter 9 that provides count information to the selector 10 receives the count information from the second counter 9 and the window signal WIND from the window generation circuit 7, and generates a window according to the count information from the second counter 9. Wind signal from generation circuit 7
A selector 10 is provided which generates a window signal SWIND, which is an "H" level signal for allowing WIND to pass through as is or for canceling the window, and supplies it to the gate circuit 4.

FIG. 2 is a diagram showing an example of a signal form suitable for the digital signal applied to the demodulation circuit of FIG. 3. As seen in FIG. 2, a frame synchronization signal S and an error detection code P are inserted at a predetermined position in data DATA to constitute one frame of a digital signal.

FIG. 4 is a diagram showing the timing of signals in each part of the circuit of FIG. 3. In FIG. 4, the solid line indicates the signal when operating at normal timing, and the broken line indicates the waveform of the signal when operating at incorrect timing. Furthermore, a dashed line indicates a frame synchronization signal that is not detected. The operation of the circuit shown in FIG. 3 will be explained below with reference to FIGS. 2 to 4.

First, in the initial state (until the frame synchronization signal is detected), the first counter 6 and the second
The counter 9 is in a free running state. The first counter 6 starts counting operation in response to the gate extraction frame synchronization detection signal from the gate circuit 4, and at every predetermined count, the window generation circuit 7
gives an operation timing signal to the The window generating circuit 7 generates a window signal WIND in response to the signal from the first counter 6 and provides it to the selector 10 and the second counter 9.

The second counter 9 counts the number of signals WIND from the window generation circuit 7 and counts the number of signals WIND from the gate circuit 4.
The count number is cleared (reset) by the signal GSYNC from the selector 10, and an "L" level signal is given to the selector 10 until the count number reaches a predetermined count number.

Since the selector 10 selects the signal from the window generation circuit 7 while the signal from the second counter 9 is "L" and passes it through as is, the selector 10 outputs the window signal SWIND synchronized with the signal from the window generation circuit 7. is output and applied to the gate circuit 4. Gate circuit 4 receives window signal SWIND
Frame synchronization detection signal only when is at “H” level
Since it passes SYNC, the wind signal WIND
The frame synchronization detection signal (FIG. 4, 1e) outside (timing-wise position shifted) is excluded, and only the frame synchronization detection signal (FIG. 4, 1a) with the correct timing is detected.

Here, the frame synchronization detection signal that appears first
If the SYNC was detected in error (4th
2a), the first counter 6 operates based on this erroneous frame synchronization detection signal SYNC, so
The window generating circuit 7 generates a window signal WIND (FIG. 4, 2b) at a position different from the normal frame synchronization position. Since the window signal WIND at the wrong position is applied to the gate circuit 4 via the selector 10, the gate extraction frame synchronization detection signal GSYNC from the gate circuit 4 is continuously lost. The second counter 9 counts the window signal WIND from the window generation circuit 7 and receives the gate extraction frame synchronization signal from the gate circuit 4.
Since it is cleared by GSYNC, the number of missing frames is counted, and when this count value exceeds a predetermined number, the selector 10 sends a signal that forces the output of the selector 10 to "H".
(Figure 4, 2c). The gate circuit 4 receives the "H" level signal from the selector 10, extracts the next appearing frame synchronization detection signal SYNC, and supplies it to the first counter 6 as the gate extracted frame synchronization detection signal GSYNC. make it work.

In the manner described above, the above operations are repeated until a normal frame synchronization detection signal SYNC is obtained, thereby obtaining a normal frame synchronization detection signal SYNC.

[Problems to be Solved by the Invention] Since the frame synchronization circuit in the conventional demodulation circuit is configured as described above, in cases where the S/N ratio is significantly degraded, the operation based on the erroneous frame synchronization detection signal SYNC cannot be performed. occurs continuously, it takes a long time to pull in frame synchronization, and the signal until frame synchronization is lost.

When digital signals are input continuously, the above point is not a big problem, but in devices such as digital magnetic recording and reproducing devices where digital signals appear continuously for short periods of time, it is difficult to obtain frame synchronization. The disadvantage is that the signal components that are lost are important, and the above-mentioned circuit system cannot be used.

Therefore, it is an object of the present invention to eliminate the above-mentioned drawbacks and to replace the original normal frame synchronization detection signal SYNC.
It is an object of the present invention to provide a frame synchronization circuit which detects a frame synchronization state and minimizes signal components lost before entering a frame synchronization pull-in state.

[Means for Solving the Problems] The frame synchronization circuit of the demodulation circuit according to the present invention performs error detection for each frame of a digital signal and utilizes the determination result.

That is, the frame synchronization circuit of the present invention includes: synchronization detection means that detects a synchronization signal included in a given digital signal and generates a synchronization detection signal; and a synchronization detection means that receives the digital signal and generates a synchronization detection signal from the synchronization detection means. an error determination means for detecting an error detection code included in the digital signal in response to the error detection code and determining the presence or absence of an error; and means for controlling the operation timing of the synchronization detection means in accordance with the determination result of the error determination means. This is a frame synchronization circuit.

More specifically, the control means causes the synchronization detection means to continuously operate when no error is detected in the error determination means, and also controls the synchronization detection signal from the synchronization detection means and the error determination means to operate the synchronization detection means continuously. If at least one of the error non-detection signal and the error non-detection signal is continuously lost, the frame synchronization circuit controls the synchronization detection means to perform a continuous detection operation.

[Operation] In the above configuration, it is determined whether synchronization pull-in is normally performed for each frame of the digital signal, and the operation of the synchronization detection means is controlled using the determination result. Therefore, it is possible to prevent the circuit from operating due to an erroneous frame synchronization detection signal as much as possible.

[Embodiment of the Invention] FIG. 1 is a block diagram showing the configuration of a frame synchronization circuit which is an embodiment of the invention. This first
As for the configuration of the digital signal applied to the circuit shown in the figure, the digital signal shown in FIG. 2 is used as in the conventional example.

First, the configuration of the circuit shown in FIG. 1 will be explained.
A frame synchronization circuit which is an embodiment of the present invention is
a frame synchronization detection circuit 2 that receives a digital signal applied to the input terminal 1, detects a frame synchronization signal included in the digital signal, and generates a frame synchronization detection signal SYNC; and frame synchronization detection from the frame synchronization detection circuit 2. Upon receiving the signal SYNC, the first OR circuit 12 (described later)
The received signal is passed through as is only when the signal from
The gate circuit 4 is applied to one input terminal of the OR circuit 15, and the count number is reset each time the gate extraction frame synchronization detection signal GSYNC from the gate circuit 4 is applied, and the operation timing is reset at every predetermined count number. a third circuit which generates a signal and supplies it to the window generation circuit 7 and the error detection circuit 13;
counter 5, and generates a window signal WIND in response to the operation timing signal from the third counter 5.
A window generating circuit 7 which supplies one input terminal of the OR circuit 12 is first provided.

Next, an error detection circuit 13 receives the digital signal applied to the input terminal 1, detects an error detection code in response to the operation timing signal from the third counter 5, and generates an error determination result ERR; A second circuit receives the error judgment result ERR from the circuit 13 and the gate extraction frame synchronization detection signal GSYNC from the gate circuit 4 and performs a logical sum.
The OR circuit 15 receives the signal from the second OR circuit 15 and the error determination result ERR from the error detection circuit 13, and selects and outputs one of them according to the signal from the comparison circuit 17, which will be described later. a fourth counter 8 that receives the signal from the selector 16 and counts the number of frames in which the loss of the gate extraction frame synchronization detection signal GSYNC and the "error" of the error determination result ERR occur simultaneously; The count information Nc from the counter 8 is received and compared with a predetermined count number setting value _N0 , and if Nc> _N0 , an "H" signal is output.
When Nc<N ₀ , a comparison circuit 17 is provided which generates an "L" signal and supplies it to the selector 16 and the other terminal of the first OR circuit 12.

Here, the selector 16 selects and outputs the error determination result ERR from the error detection circuit 13 if the signal from the comparison circuit 17 is at the "H" level, and when the signal from the comparison circuit 17 is at the "L" level. is the second
The signal from the OR circuit 15 is selected and output.

Next, the operation will be explained. As shown in FIG. 2, the structure of the input signal includes an error detection code for error detection immediately after the frame synchronization signal.
The frame synchronization detection circuit 2 detects a frame synchronization signal from the digital signal applied via the input terminal 1, and generates a frame synchronization detection signal accordingly.
Generates SYNC. In an initial state (a state in which the frame synchronization detection signal SYNC has not yet appeared), both the third counter 5 and the fourth counter 8 are running independently of the frame synchronization signal.
Since the window generating circuit 7 is operated by the timing signal from the third counter 5, the window signal WIND from the window generating circuit 7 is also generated at a position unrelated to the frame synchronization detection signal SYNC. Also, at this time, since the count output of the fourth counter 8 is smaller than the set value _N0 , the signal WS from the comparison circuit 17 is at the "L" level. 1st OR
The circuit 12 receives the "L" level signal WS from the comparison circuit 17 and the window signal from the window generation circuit 7.
Since it is logically ORed with WIND, the gate circuit 4 receives the window signal from the window generation circuit 7.
WIND is given as is. Therefore, in this state, the gate circuit 4 receives the synchronization detection signal.
SYNC is not passed and the gate extraction frame synchronization detection signal GSYNC is not generated.

On the other hand, since the error detection circuit 13 operates in response to the timing signal from the third counter 5, it is natural that the error determination result of the error detection circuit 13
ERR indicates "error". While the output signal WS from the comparison circuit 17 is at "L" level, the selector 16 selects and outputs the output of the second OR circuit 15.
The second OR circuit 15 outputs the logical sum of the fact that the error judgment result ERR of the error detection circuit 13 is "correct" and the appearance of the gate extraction frame synchronization detection signal GSYNC, and provides it to the fourth counter 8. In the initial state, the count of the fourth counter 8 is not cleared, and the count number of the fourth counter 8 continues to increase. When the count value of the fourth counter 8 exceeds the set value _N0 , the output signal WS from the comparison circuit 17 becomes "H" level, so the output of the first OR circuit 12 also becomes "H" level, and the selector Reference numeral 16 selectively outputs the error determination result ERR from the error detection circuit 13. As a result,
The frame synchronization detection signal SYNC passes through the gate circuit 4 as it is and becomes the gate extraction frame synchronization detection signal GSYNC. If the gate extraction frame synchronization detection signal GSYNC is detected by mistake at this time, the third counter 5 is not operating at the normal timing, and the error detection circuit 13 is also not operating at the normal timing. Therefore, the error determination result ERR from the error detection circuit 13 indicates "error". Since the output signal WS from the comparison circuit is at the "H" level, the selector 16 selects and outputs only the error determination result ERR from the error detection circuit, so the fourth counter 8 is not reset and continues counting operation. .

Correct gate extraction frame synchronization detection signal
When GSYNC is detected, the third counter 5 operates at normal timing, and the error detection circuit 13 also operates at normal timing, so that the error judgment result ERR "correct" signal from the error detection circuit is output. show. In response, the fourth counter 8 is reset, its count number becomes smaller than the set value _N0 , the output signal WS from the comparator circuit 17 becomes "L" level, and the selector 16 resets the second OR
The output of the circuit 15 is selected, and the gate circuit 4 detects the frame synchronization signal SYNC in synchronization with the window signal WIND from the window generation circuit 7. As a result, erroneously detected signals other than the original normal frame synchronization signal are eliminated.

That is, if the count number in the fourth counter 8 does not exceed the set value _N0 , the error determination result ERR from the error detection circuit 13 is "error".
Indicating and gate extraction frame synchronization detection signal
Synchronization is considered to be maintained unless loss of GSYNC (when the frame synchronization detection signal SYNC does not appear where it should appear) occurs simultaneously and consecutively, and if they occur consecutively, the window from the window generation circuit 7 Ignoring the signal WIND (the "H" signal WS is output from the comparator circuit 17), the frame synchronization detection signal SYNC is extracted from the gate as it is, and the error check result ERR from the error detection circuit 13 is output as the frame synchronization detection signal GSYNC.
I am trying to only monitor and bring it into synchronization.

Although the frame synchronization circuit in the demodulation circuit has been described in the above embodiment, the present invention improves the reliability of signal detection by performing signal detection and error detection in the same manner as in the above embodiment in other circuits as well. It becomes possible to improve the performance.

[Effects of the Invention] As described above, according to the present invention, frame synchronization is configured such that a frame synchronization gate is applied according to the error determination result for each frame of a digital signal, so that the analog frame synchronization signal is This has the effect of minimizing circuit malfunctions and providing a device that can quickly pull in frame synchronization.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a frame synchronization circuit system for demodulation in one embodiment of the present invention. FIG. 2 is a circuit diagram showing the structure of a digital signal to be demodulated. FIG. 3 is a block diagram of a conventional frame synchronization circuit system of a demodulation circuit. FIG. 4 is a diagram showing the timing of signals in each part of the circuit of FIG. 3. In the figure, 2 is a frame synchronization detection circuit, 4 is a gate circuit, 5, 6, 8, 9 are counters, 7 is a window generation circuit, 10, 16 are selectors, 13 is an error detection circuit, 12, 15 are OR circuits, 17 indicates a comparison circuit. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Scope of Claims] 1. A circuit for synchronizing the frame of a digital signal in which a frame synchronization signal and an error detection code are inserted at predetermined positions, the circuit comprising: receiving the digital signal; frame synchronization extraction means for extracting a included frame synchronization signal to generate an extracted frame synchronization signal; and detecting the error detection code from the digital signal in response to the extracted frame synchronization signal from the frame synchronization extraction means. , determining means for determining whether the digital signal is correct or incorrect based on the detected error detection code and outputting a signal indicating the determination result; in response to the output of the frame synchronization extraction means;
window signal generating means for generating a window signal that provides the frame synchronization signal extraction timing of the frame synchronization extraction means, the window signal having a duration for removing signals other than the frame synchronization signal, and the determining means further comprising control means for selecting either the window signal or a fixed level activation signal and applying it to the frame synchronization extraction means in response to the output from the frame synchronization extraction means and the frame synchronization extraction means; The synchronization extraction means performs a signal extraction operation according to the output of the control means, and the control means selects the window signal and applies it to the frame synchronization extraction means in an operation mode in which the extracted frame synchronization signal is missing and the determination is performed. When the output of the means indicates an error in the digital signal occurs simultaneously and consecutively a predetermined number of times, selecting the fixed level activation signal in place of the window signal and extracting it to the frame synchronization extracting means. A frame synchronization circuit including means for providing as a control signal.