JP2736448B2 - Frame synchronization circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frame synchronization circuit, and more particularly to an improvement in synchronization protection for detecting a frame synchronization signal.

[Prior Art] FIG. 2 is a circuit block diagram showing a reproduction system circuit in a conventional digital audio tape recorder (hereinafter referred to as DAT). Referring to FIG. 2, this reproducing system circuit
A head 21 for reproducing a signal recorded on a magnetic tape,
An amplifier 22 for amplifying the reproduced signal and a waveform shaping circuit 23
And a comparator 24 for converting the waveform-shaped signal into a digital signal, and a digital signal in a unit of 10 bits in response to the output signal So from the frame synchronization circuit 30.
It includes a demodulation circuit 25 for demodulating to a digital signal of bits, an error correction circuit 26, and a D / A converter 27 for converting an error-corrected digital signal into an analog signal. An audio signal reproduced from the D / A converter 27 is obtained.

A conventional example of the frame synchronization circuit 30 is disclosed in
A circuit disclosed in Japanese Patent Publication No. 1045 is known, and this circuit is shown in FIG.

FIG. 3 is a circuit block diagram showing a conventional frame synchronization circuit. Referring to FIG. 3, the frame synchronization circuit includes a frame synchronization detection circuit 2, a game circuit 4, a counter 5, a window generation circuit 7, an OR gate 12, an error detection circuit 13, and an OR gate 15. , A selector 16, a counter 8, and a comparison circuit 17. A digital signal is provided through an input terminal 1. The output signal So is output from the counter 5.

FIG. 4 is a data configuration diagram showing a configuration of a digital signal provided to the frame synchronization circuit shown in FIG. Referring to FIG. 4, the digital signal is a frame synchronization signal S
And an error detection code P and necessary data DATA.
One frame is composed of the signal S, the code P and the data DATA.

Next, the operation of the frame synchronization circuit shown in FIG. 3 will be described. First, the frame synchronization detection circuit 2 detects a frame synchronization signal from a digital signal supplied via the input terminal 1 and responds to the detection by a frame synchronization detection signal SY.
Output NC. In an initial state (a state in which the frame synchronization detection signal SYNC has not been given yet), each of the counters 5 and 8 is running independently of the frame synchronization signal. Since the window generation circuit 7 operates according to the timing signal from the counter 5, the window signal WIND output from the circuit 7 is also output at a position unrelated to the signal SYNC.
At this time, since the count output of the counter 8 is smaller than the set value No, the signal WS from the comparison circuit 17 is at the L level.

The OR gate 12 ORs the L-level signal WS from the comparison circuit 17 and the window signal WIND from the window generation circuit 7. Therefore, window signal WIND from window generating circuit 7 is applied to gate circuit 4 as it is. As a result, in this state, the gate circuit 4 does not pass the synchronization detection signal SYNC, and the gate extraction frame synchronization detection signal GSYNC is not output.

On the other hand, since the error detection circuit 13 operates in response to the timing signal from the counter 5, the output signal ERR indicating the error determination result naturally indicates "error". While the output signal WS from the comparison circuit 17 is at the L level, the selector 16 selectively outputs the output of the OR gate 15. The OR gate 15 outputs the logical sum of the fact that the error determination result ERR of the error detection circuit 13 is “correct” and the appearance of the gate extraction frame synchronization detection signal GSYNC, and supplies the result to the counter 8. Therefore, in the initial state, the count of the counter 8 is not cleared,
The count number in the counter 8 increases as it is. When the count value of the counter 8 exceeds the set value No, the output signal WS from the comparison circuit 17 becomes H level, so that the output of the OR gate 12 also becomes H level, and the selector 16 determines the error judgment result from the error detection circuit 13. Selectively output ERR. as a result,
The frame synchronization detection signal SYNC passes through the gate circuit 4 as it is and becomes a gate extraction frame synchronization detection signal GSYNC. At this time, if the gate extraction frame synchronization signal GSYNC is erroneously detected, the counter 5 does not operate at the normal timing, and the error detection circuit 13 does not operate at the normal timing. Circuit 13
From the error determination result ERR indicates “error”. Since the output signal WS from the comparison circuit is at the H level, the selector 16 selects and outputs only the error determination result ERR from the error detection circuit, so that the counter 8 continues counting without being reset.

However, when the gate extraction frame synchronization detection signal GSYNC is detected, the counter 5 operates at a normal timing,
In response, the error detection circuit 13 also operates at normal timing. Therefore, the error detection circuit 13 outputs the error determination result ER
R Outputs "correct" signal. In response,
The counter 8 is reset, and the count value becomes the set value No.
The output signal WS from the comparison circuit 17 becomes L level, the selector 16 selects the output of the OR gate 15, and the gate circuit 4 synchronizes with the window signal WIND from the window generation circuit 7 to synchronize the frame synchronization signal. Detect SYNC. As a result, erroneously detected signals other than the normal frame synchronization signal are eliminated.

That is, the count number of the counter 8 is equal to the set value No.
Is not exceeded, the error determination result ERR from the error detection circuit 13 indicates "error" and the gate extraction frame synchronization detection signal GSYNC is missing (the frame synchronization detection signal SSYNC
Synchronization is maintained unless YNC does not appear where it should originally appear). If they occur consecutively, the window signal WIND from the window generation circuit 7 is ignored (the H signal WS is output from the comparison circuit 17), and the frame synchronization detection signal SYNC is directly gate-extracted and the frame synchronization is performed. Detection signal
As GSYNC, only the error detection result ERR from the error detection circuit 13 is pulled into synchronization.

[Problems to be Solved by the Invention] Since the conventional frame synchronization circuit is configured as described above, even if the quality of the input digital signal is deteriorated, it is necessary to detect the frame synchronization detection signal SYNC erroneously. It can be reduced as much as possible. However, when a tape is run at a high speed in a rotary head type DAT, for example, in a special mode such as a high speed search, the periodicity of a synchronization signal in a reproduced digital signal is disturbed. Since the conventional frame synchronization circuit is configured on the assumption that a periodic synchronization signal is input as described above, it cannot respond to a non-periodically input synchronization signal in a high-speed search.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has as its object to obtain a frame synchronization circuit capable of appropriately controlling synchronization protection according to a mode to be used.

[Means for Solving the Problems] A frame synchronization circuit according to the present invention includes: a synchronization detection unit that outputs a synchronization detection signal in response to a frame synchronization signal included in an input digital signal; Extraction means for selectively extracting the synchronization detection signal at a predetermined time interval, and eliminating a predetermined time interval in the extraction means in a specific mode specified externally, and continuously outputting the synchronization detection signal to the extraction means. And control means for extracting.

[Operation] In the frame synchronization circuit according to the present invention, in the specific mode specified externally, the predetermined time interval in the extraction means is eliminated, and the extraction means continuously extracts the synchronization detection signal. Synchronization protection is released.

FIG. 1 is a circuit block diagram of a frame synchronization circuit showing one embodiment of the present invention. Referring to FIG. 1, a difference from the conventional circuit shown in FIG. 3 is that a mode selection switch 18 for designating a specific mode is provided. OR gate 12 is connected to receive a signal from switch 18. By operating the switch 18, an H level signal is supplied to the OR gate 12 in the high speed search mode and an L level signal in the normal reproduction mode. The other circuits are the same as the circuits shown in FIG.

Next, the operation will be described. First, in the normal reproduction mode, the switch 18 is connected to the terminal b, and an L-level signal is given to the OR gate 12. Therefore, the operation in this mode is the same as that of the conventional circuit shown in FIG. That is, the gate circuit 4 is controlled in response to the window signal WIND output from the window generation circuit 7 when synchronization is established, and the comparison circuit
Control of gate circuit 4 is performed in response to output signal WS from 17.

In the high-speed search mode, the switch 18 is connected to the terminal a, so that an H-level signal is supplied to the OR gate 12. As a result, since the OR gate 12 always supplies a signal of H level to the gate circuit 4, the gate circuit 4 outputs the frame synchronization detection signal SY output from the frame synchronization detection circuit 2.
NC is removed from the gate as it is Frame synchronization detection signal GSYNC
Output as That is, control of gate circuit 4 by window signal WIND output from window generation circuit 7 and signal WS output from comparison circuit 17 is not performed. Therefore, the counter 5 outputs the frame synchronization detection signal SY
Since control is performed in response to the NC, even if frame synchronization is lost due to intermittent loss of digital signals in a high-speed search, a synchronization pull-in operation is started as soon as a digital signal appears. Therefore, in the conventional circuit, data loss occurs until the set value No is reached. However, the frame synchronization circuit shown in FIG. 1 prevents this loss.

Although the input signal of the OR gate 12 is controlled in the above embodiment, the same effect can be obtained by controlling the set value No given to the comparison circuit 17 according to the mode.

[Effects of the Invention] As described above, according to the present invention, the synchronization detection signal is not extracted at predetermined time intervals in the externally designated specific mode, and the synchronization detection signal is continuously output. Since the frame synchronization circuit is extracted, a frame synchronization circuit capable of appropriately applying synchronization protection according to the mode used is obtained.

[Brief description of the drawings]

FIG. 1 is a circuit block diagram of a frame synchronization circuit showing one embodiment of the present invention. FIG. 2 is a circuit block diagram showing a conventional DAT reproduction system circuit. FIG. 3 is a circuit block diagram showing a conventional frame synchronization circuit. FIG. 4 is a data configuration diagram showing a configuration of a digital signal provided to the frame synchronization circuit shown in FIGS. 1 and 3. In the figure, 2 is a frame synchronization detection circuit, 4 is a gate circuit, 5 is a counter, 7 is a window generation circuit, 12 is an OR gate, and 18 is a mode selection switch.

Claims (1)

(57) [Claims] 1. A circuit for establishing frame synchronization of a digital signal in which a frame synchronization signal and an error detection code are inserted at a predetermined position, wherein the synchronization is performed in response to a frame synchronization signal included in the digital signal. Synchronization detection means for outputting a detection signal; extraction means connected to the synchronization detection means for selectively extracting the synchronization detection signal at a predetermined time interval in response to the synchronization detection signal; A frame synchronization circuit comprising: a control unit that eliminates the predetermined time interval in the extraction unit in a specific mode and causes the extraction unit to continuously extract a synchronization detection signal.