JPH03129935A - Frame synchronizing circuit - Google Patents

Abstract

PURPOSE:To suitably control the synchronization protection in accordance with a mode to be used by providing an extracting means for extracting selectively a synchronization detecting signal at the time intervals determined in advance in response of a synchronization detecting means, and a disabling means for disabling the extracting means in a specific mode designated externally. CONSTITUTION:In a high speed search mode, a switch 18 is connected to a terminal (a) side, and accordingly, the signal of an H level is applied to an OR gate 12. As a result, since the OR gate 12 always applies the signal of an H level to a gate circuit 4, a frame synchronization detecting signal SYNC is outputted as it is as a gate slip-out frame synchronization detecting signal GSYNC. That is, the control of the gate circuit 4 by a window signal WIND outputted from a window generating circuit 7 and a signal WS outputted from a comparing circuit 17 comes not to be executed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a frame synchronization circuit, and more particularly to an improvement in synchronization protection for detecting a frame synchronization signal.

[Prior Art] Figure 2 shows a conventional digital audio tape recorder (
FIG. 2 is a circuit block diagram showing a reproduction system circuit in the DAT (hereinafter referred to as DAT). Referring to FIG. 2, this reproduction system circuit is as follows:
A head 21 for reproducing signals recorded on a magnetic tape, an amplifier 22 for amplifying the reproduced signal, a waveform shaping circuit 23, and an A/C converting the waveform-shaped audio analog signal into a 10-bit digital signal. A D converter 24, a demodulation circuit 25 that demodulates a 10-bit audio digital signal into an 8-bit digital signal in response to the output signal SO from the frame synchronization circuit 30, an error correction circuit 26, and an error-corrected digital signal. and a D/A converter 27 that converts the signal into an analog signal. A reproduced audio signal is obtained from the D/A converter 27.

As a conventional example of the frame synchronization circuit 30,
A circuit disclosed in Japanese Patent No. 161045 is known, and this circuit is shown in FIG.

FIG. 3 is a circuit block diagram showing a conventional frame synchronization circuit. Referring to FIG. 3, this frame synchronization circuit includes a frame synchronization detection circuit 2, a gate circuit 4, a counter 5, a window generation circuit 7, an OR gate 12, an error detection circuit 13, and an OR gate 15. , a selector 16 , a counter 8 , and a comparison circuit 17 . A digital signal is applied via input terminal 1. The counter 5 outputs an output signal So.

FIG. 4 is a data configuration diagram showing the configuration of a digital signal applied to the frame synchronization circuit shown in FIG. 3. Fourth
Referring to the figure, the digital signal consists of a frame synchronization signal S, an error detection code P, and necessary data DATA. One frame is composed of the signal S, the code P, and the data DATA.

Next, the operation of the frame synchronization circuit shown in FIG. 3 will be explained. First, the frame synchronization detection circuit 2 detects a frame synchronization signal from a digital signal applied through the input terminal 1, and in response, the frame synchronization detection circuit 2 detects a frame synchronization signal 5Y.
Output NC. Initial state (frame synchronization detection signal 5Y
(in a state where NC is not yet applied), both counters 5 and 8 are running independently of the frame synchronization signal. Since the window generating circuit 7 operates according to the timing signal from the counter 5, the window signal WINDt+signal 5YNC is outputted at a position unrelated to the window signal WINDt+signal 5YNC outputted from the circuit 7. Further, at this time, since the count output of the counter 8 is smaller than the set value No, the signal ws from the comparison circuit 17 is at L level.

The OR gate 12 receives the L level signal WS from the comparison circuit 17 and the window signal WIND from the window generation circuit 7.
Take the logical sum of Therefore, the window signal WIND from the window generating circuit 7 is applied to the gate circuit 4 as is. As a result, in this state, the gate circuit 4 does not pass the synchronization detection signal 5YNC, and the gate extraction frame synchronization detection signal GSYNC is not output.

On the other hand, since the error detection circuit 13 operates in response to the timing signal from the counter 5, the output signal ERR indicating the error determination result naturally indicates an "error". While the output signal WS from the comparison circuit 17 is at L level, the selector 16 selectively outputs the output of the OR gate 15. The OR gate 15 detects that the error judgment result ERR of the error detection circuit 13 is "correct" and the gate extraction frame synchronization detection signal GSYN.
The logical sum with the appearance of C is outputted and given to the counter 8. Therefore, in the initial state, the count of the counter 8 is not cleared, and the count number of the counter 8 continues to increase. The count value of counter 8 is the set value N
Since the output signal WS from the comparison circuit 17 becomes H level when the value exceeds o, the output of the OR gate 12 also becomes H level, and the selector 16 selectively outputs the error determination result ERR from the error detection circuit 13. As a result, the frame synchronization detection signal 5YNC passes through the gate circuit 4 as it is and becomes the gated frame synchronization detection signal GSYNC.

If the gate extraction frame synchronization signal GSYNC is erroneously detected at this time, the counter 5 is not operating at the normal timing, and the error detection circuit 13 is also not operating at the normal timing, so the error is detected. The error determination result ERR from the circuit 13 indicates "error". Since the output signal WS from the comparison circuit is at H level, the selector 16 selects and outputs only the error determination result ERR from the error detection circuit, so the counter 8 is not reset and continues counting operation.

However, when the gate extraction frame synchronization detection signal GSYNC is detected, the counter 5 operates at normal timing, and in response, the error detection circuit 13 also operates at normal timing. Therefore, the error detection circuit 13 outputs a signal indicating that the error determination result ERRr is correct. In response, the counter 8 is reset, its count value becomes smaller than the set value NO, the output signal WS from the comparison circuit 17 becomes L level, and the selector 16 outputs the OR gate 1.
5, and the gate circuit 4 detects the frame synchronization signal 5YNC in synchronization with the window signal WIND from the window generation circuit 7. As a result, erroneously detected signals other than the original normal frame synchronization signal are eliminated.

That is, the count number in the counter 8 is equal to the set value NO.
In the case where the error determination result ERR from the error detection circuit 13 indicates "error" and the gate extraction frame synchronization detection signal GSYNC is missing (if the frame synchronization detection signal 5YNC does not appear where it should appear) Synchronization is assumed to be maintained unless these occur simultaneously and consecutively. Also, if it happens consecutively,
(Ignoring the window signal WIND from the window generation circuit 7, the comparator circuit 17 outputs an H signal WS), and extracts the frame synchronization detection signal 5YNC as it is from the gate and outputs it as the frame synchronization detection signal GSYNC from the error detection circuit 13. Only the error detection result ERR is brought into synchronization.

[Problems to be Solved by the Invention] Since the conventional frame synchronization circuit is configured as described above, it is possible to prevent the frame synchronization detection signal 5YNC from being erroneously detected even when the quality of the input digital signal deteriorates. It can be reduced as much as possible. however,
When the tape is run at high speed in a rotary head type DAT, for example, in a special mode such as high-speed search, periodic signal disturbances occur in the synchronization signal in the reproduced digital signal. The conventional frame synchronization circuit is configured on the premise that a periodic synchronization signal is input as described above, and therefore cannot cope with a non-periodic human input synchronization signal in high-speed search.

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to obtain a frame synchronization circuit that can appropriately control synchronization protection depending on the mode used.

[Means for Solving the Problems] A frame synchronization circuit according to the present invention includes a synchronization detection means that outputs a synchronization detection signal in response to a frame synchronization signal included in an input digital signal, and a synchronization detection means that outputs a synchronization detection signal in response to a frame synchronization signal included in an input digital signal, and It includes an extracting means for selectively extracting the synchronization detection signal at predetermined time intervals, and a disabling means for disabling the extracting means in an externally designated specific mode.

[Operation] In the frame synchronization circuit according to the present invention, the extraction means is disabled by the disabling means in an externally designated specific mode, so that synchronization protection is canceled only in the specific mode.

[Embodiment of the Invention] FIG. 1 is a circuit block diagram of a frame synchronization circuit showing an embodiment of the invention. Referring to FIG. 1, the difference from the conventional circuit shown in FIG. 3 is that a mode selection switch 18 for specifying a specific mode is provided. OR gate 12 is connected to receive a signal from switch 18. By operating the switch 18, an H level signal is applied to the OR gate 12 in the high speed search mode, and an L level signal is applied to the normal playback mode. The other circuits are the same as the circuit shown in FIG. 3, so their explanation will be omitted.

Next, the operation will be explained. First, in the normal reproduction mode, the switch 18 is connected to the terminal side, and an L level signal is applied to the OR gate 12. Therefore, operation in this mode is similar to the conventional circuit shown in FIG. That is, when synchronization is established, the gate circuit 4 is controlled in response to the window signal WIND output from the window generation circuit 7, and when synchronization is pulled in, the gate circuit 4 is controlled in response to the output signal WS from the comparison circuit 17. Control of circuit 4 is performed.

In the high-speed search mode, the switch 18 is connected to the terminal a side, so the H level signal is sent to the OR gate 12.
given to. As a result, the OR gate 12 always gives an H level signal to the gate circuit 4, so the gate circuit 4 extracts the frame synchronization detection signal 5YNC output from the frame synchronization detection circuit 2 as it is and outputs it as the frame synchronization detection signal GSYNC. . That is, the gate circuit 4 is no longer controlled by the window signal WIND output from the window generation circuit 7 and the signal WS output from the comparison circuit 17. Therefore, counter 5
is controlled in response to the frame synchronization detection signal SYNC, so even if frame synchronization is lost due to intermittent loss of digital signals during high-speed search, synchronization pull-in operation begins as soon as a digital signal appears. Therefore, in the conventional circuit, data loss occurs until the set value No is reached, but in the frame synchronization circuit shown in FIG. 1, this loss can be prevented.

In the above embodiment, the input signal of the OR gate 12 is controlled, but the same effect can be obtained by controlling the set value No given to the comparison circuit 17 according to the mode.

[Effects of the Invention] As described above, according to the present invention, synchronization detection signals are no longer extracted at predetermined time intervals in an externally designated specific mode, so A frame synchronization circuit that can appropriately apply synchronization protection was obtained.

[Brief explanation of the drawing]

FIG. 1 is a circuit block diagram of a frame synchronization circuit showing one embodiment of the present invention. FIG. 2 is a circuit block diagram showing a reproduction system circuit of a conventional DAT. FIG. 3 is a circuit block diagram showing a conventional frame synchronization circuit. Fourth
3 is a data structure diagram showing the structure of a digital signal applied to the frame synchronization circuit shown in FIGS. 1 and 3. FIG. In the figure, 2 is a frame synchronization detection circuit, 4 is a gate circuit, 5 is a counter, 7 is a window generation circuit, and 12 is an OR
The gate 18 is a mode selection switch.

Claims (1)

[Claims] A circuit for synchronizing the frame of a digital signal in which a frame synchronization signal and an error detection code are inserted at predetermined positions, the circuit comprising: synchronization detection means for outputting a synchronization detection signal; extraction means connected to the synchronization detection means and selectively extracting the synchronization detection signal at predetermined time intervals in response to the synchronization detection signal; and disabling means for disabling the extracting means in a specific mode in which the frame synchronization circuit is used.