JPH0729322A - Reproducing device for digital signal - Google Patents

Abstract

PURPOSE:To detect an error of an error correcting circuit even if amplitude of a reproduced signal is decreased. CONSTITUTION:As a reproduced signal from a magnetic tape 1 is decreased, a waveform equalizer 4 receives a signal of a H level from an amplitude detector 5 for a reproduced signal, and outputs a reproduced digital signal in which that part is made a L level. A demodulator 8 receives a L level of the digital signal, generates an error flag, and sends it to an error corrector 9 with demodulated data.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital reproducing apparatus for reproducing a signal recorded by a modulation method having a limitation on the succession of the same symbol.

[0002]

2. Description of the Related Art A conventional digital reproducing apparatus is described in the first document ("New 8-14 modulation system and its compact digital VT system".
Application to R ”Journal of the Television Society, Vol. 46 (1992), N
o. 2, pp. 197-203). According to the first document, 8-14 conversion is 4.7% of 2 ¹⁴ codes.
Since it is used as a modulation code, it is possible to improve the error correction capability by detecting an error when a code other than the modulation code is reproduced and performing erasure error correction by an error correction device in the subsequent stage. Have been described. However, although the error detection by this unused code has no error detection, the detection capability is generally low and is within 30%. Therefore, even if an error continues for a long time due to a decrease in the amplitude of the tape output, not all of them can be detected as an error by the method of the first document. On the other hand, in the error correction device in the latter stage, if all the input data are erroneous, this may not be detected as an error. At this time, these erroneous data are propagated without any treatment. When this digital reproducing apparatus is applied to a VTR, these erroneous data appear as disturbances in the reproduced image.

As a countermeasure against this, the second document ("VTR technology", Japan Broadcasting Corporation, pp123-124, published in April 1969)
It is conceivable to provide a dropout compensating means for an analog VTR in a circuit after the error correction device, as described in the above. However, even with this countermeasure, it is difficult to directly correct the image output in a system in which the time axis on the tape does not correspond to the time axis on the screen by performing a process such as image compression.

The circuit configuration shown in FIG. 4 can be considered there. Recorded magnetic tape 401 to magnetic head 40
2. The signal reproduced by using the preamplifier 403 is supplied to the waveform equalizer 404 and the reproduction signal amplitude detector 405. The waveform equalizer 404 performs waveform shaping of the reproduction signal in the preceding stage,
The signal is supplied to a PLL (phase locked loop) device 406. PL
The L unit 406 generates a clock and supplies it to the subsequent stage of the waveform equalizer 404. In accordance with this clock, the latter stage of the waveform equalizer 404 converts the waveform-shaped reproduced signal into a digital signal and outputs it. The frame sync detector 407 detects the frame sync signal in the output data of the waveform equalizer 404, and accordingly converts the incoming serial data into 14-bit parallel data at the time of recording. The demodulator 408 restores the output parallel data of the frame synchronization detector 407 to the original 8-bit data according to a predetermined conversion table, and at the same time, outputs an 8-bit data output when an unused 14-bit pattern is input. Separately, a demodulation error flag is output.

On the other hand, in the reproduced signal amplitude detector 405, when the reproduced signal amplitude decreases to such an extent that the error rate of the reproduced digital signal exceeds the error detection capability of the error corrector 409, the detected signal is detected. The delay circuit 41
Send to 0. The delay circuit 410 is the next error corrector 409,
According to the output of the reproduction signal amplitude detector 405, when the error flag is added to the output data of the demodulator 408, the data and the output of the reproduction signal amplitude detector 405 are time-aligned.

The error corrector 409 obtains the output of the demodulator 408 and, if necessary, the sync detection signal of the frame sync detector 407 to perform an error correction operation, and the data thus obtained and the reproduction signal amplitude detector. The output of 405 or the error flag obtained by its own error detection function is combined and sent to a circuit in the subsequent stage (not shown), where measures such as reservation of the previous image are carried out to reduce visual disturbance of the reproduced image. However,
The delay circuit 410 often requires a circuit element whose circuit scale becomes large.

The third document (JP-A-61-261873)
However, as described above, the frame synchronization signal is selected and used from among the modulated signals, the frequency of which is low. However, if the error continues for a long period of time, data that is significantly different from the recording modulation signal arrives at the frame synchronization detector 407, so that the frame synchronization signal, which has a low occurrence frequency, frequently occurs in the recording modulation data. As a result, for example, a large number of synchronization detection signals are erroneously output from the frame synchronization detector 407 during the error period, which disturbs the operation of the circuit at the next stage.

[0008]

If, for example, the amplitude drops and the error rate extremely deteriorates during special reproduction, erroneous detection frequently occurs in the frame synchronization detector 407. As a result, the error correction circuit 409 cannot detect the error, and the error is spilled into the circuit of the next stage, and there is a problem that the correction process cannot be performed. On the other hand, even if the reproduction signal amplitude detector 405 is used to send an error flag to the error corrector 409, the erroneous detection of the frame synchronization detector 407 is not solved, and the error flag has a time difference, so that the delay circuit 410 Had to be provided.

According to the present invention, even when a reproduction signal is interrupted for a long time such as a special reproduction of a VTR and exceeds the error correction capability of an error corrector, the disturbance of a reproduced image is corrected without newly installing a large circuit. An object is to provide a digital reproducing device.

[0010]

In a digital reproducing apparatus for reproducing a signal recorded by a modulation method having a limitation on the succession of the same symbol, a reproducing signal amplitude detecting means for detecting the amplitude of the reproducing signal and a reproducing signal amplitude detecting means for detecting the amplitude of the reproducing signal. A waveform equalizing means for performing waveform shaping and converting it into a digital signal, and a reproduced signal after the waveform shaping by the waveform equalizing means are input, and based on this, used for conversion of the waveform equalizing means into a digital signal. A PLL means for generating a clock and an output of the waveform equalizing means are inputted, and a frame synchronization detecting means for detecting a synchronizing signal in a reproduction signal and an output of the frame synchronizing detecting means are demodulated and are not used at the same time for recording. When a modulated signal is input, demodulation means for adding an error flag to the demodulation data, and error detection from the demodulation data and the error flag from the demodulation means. And an error correction means for performing correction, in the means from the output of the waveform equalization means to the input of the demodulation means, according to the output of the reproduction signal amplitude detection means, the reproduction signal is forcibly set with an error flag. Switch to a signal that can be detected.

[0011]

For example, when reproducing the medium recorded by the modulation method in which the upper limit is given to the continuation of 0 symbols such as 8-14 modulation, when the amplitude of the reproduced signal is not obtained as necessary, As described above, the reproduction signal is forcibly for example L (low).
Fix at (0). At this time, in the 14-8 demodulation operation, since these reproduced data are obviously different from the recording modulation signal, they can be surely regarded as error data.

[0012]

1 shows the circuit structure of a digital signal reproducing apparatus according to the present invention. 2 and 3 show the operation of the digital signal reproducing apparatus of the present invention. A signal reproduced from the recorded magnetic tape 1 using the magnetic head 2 and the preamplifier 3 is supplied to the waveform equalizer 4 and the reproduction signal amplitude detector 5. The waveform equalizer 4 performs waveform shaping of the reproduction signal in the preceding stage and supplies it to the PLL device 6. The PLL device 6 generates a clock and supplies it to the subsequent stage of the waveform equalizer 4. On the other hand, in the reproduced signal amplitude detector 5, when the reproduced signal amplitude decreases to such an extent that the error rate of the reproduced digital signal exceeds the correction capability of the error corrector 9, the detected signal is waveformd. It is sent to the latter stage of the equalizer 4. Waveform equalizer 4
In the subsequent stage, the above-mentioned waveform-shaped reproduced signal is converted into a digital signal by the clock from the PLL device 6. At this time, if there is an output from the reproduction signal amplitude detector 5, the waveform equalizer 4 forcibly fixes that portion to L (low) (0). The reproduced digital signal thus obtained is input to the error corrector 9 through the frame synchronization detector 7 and the demodulator 8.

Next, the operation of the digital signal reproducing apparatus of the present invention will be described with reference to FIGS. In Figure 2,
The movement loci of the first and second heads 22 and 23 on the magnetic tape 21 during 3 × speed reproduction are shown. The first of plus azimuth
Head 22 traces the nth track recorded in plus azimuth, the n + 1th track recorded in minus azimuth, and the n + 2th track recorded in plus azimuth. And the second head of minus azimuth 23
Traces the (n + 3) th track recorded in the (n + 1) th, (n + 2) th, and minus azimuth.

FIG. 3 shows the state of the output signal of each part of the circuit at this time. The outputs of the first head 22 and the second head 23 are shown at 31 and 32, respectively. Since signals of tracks with different polarities cannot be reproduced due to the azimuth effect, the output changes according to the width of tracing tracks of the same polarity. The reproduction signal amplitude detector 5 which has obtained this reproduction signal outputs H (high) during a period in which the amplitude of the reproduction signal decreases as indicated by 33. Upon receiving this H (high) signal, the output digital signal of the waveform equalizer 4 is forcibly fixed to L (low) (0). In the frame sync detector 7 which has obtained this output, the sync signal is not detected during the period in which L (low) (0) is forcibly continued at 34, and the synchronization is disabled. However, during this period, the synchronization is stable in the free-running state, and the reproduced digital signal is converted into the original 14-bit parallel signal and output to the demodulator 8.

The demodulator 8 converts incoming 14-bit data into 8-bit data according to a predetermined conversion table. And like the conventional technology, it is not used during recording
When 14-bit data arrives, the demodulation error flag 35 prepared separately from the 8-bit data is set to H (high) to indicate that the data in this period is in error. At this time, in the modulation method described in the related art, the reproduction signal L (low)
The upper limit of the continuation of (0) is 6, there must be two or more H (high) in any 14 bits, and the modulation in which all 14 bits are L (low) (0) is not used. Therefore, as described above, the demodulation error flag becomes H (high) as shown in 35 during the period in which L (low) (0) continues. In this way, since the error flag can be added to the output data of the demodulator 8 when the reproduction signal is attenuated, even if the error correction capability of the error corrector 9 itself is exceeded, the correction circuit in the subsequent stage (not shown) Although the data cannot be corrected according to the error flag, it can be corrected.

In the above embodiment, the reproduced signal is forcibly set to L.
Although the point where (low) (0) is set is in the latter stage of the waveform equalizer 4, the demodulation error flag can be obtained in substantially the same manner even if this is performed at the input part of the demodulator 8. Further, the value to be forcibly output is not limited to L (low) (0), and is not used as a recording modulation signal when returning to a 14-bit parallel signal.
For example, all bit patterns are H (high)
You can

As described above, the digital signal reproducing apparatus of the present invention does not require the delay circuit as in the conventional technique, and the circuit configuration becomes simple. Further, the applicable range of the present invention is wide, such as a so-called run length limited code modulation method, such as 8-14, M2, 8-10, MFM.

[0018]

As described above, according to the present invention, even when the error correction capability of the error corrector is exceeded, the error corrector can detect an error depending on the demodulation flag, and in particular, the signal path and processing circuit for the error flag. The demodulation flag can also be used without newly installing. In addition, instability due to erroneous detection does not occur in the frame synchronization detection unit.

[Brief description of drawings]

FIG. 1 is a block diagram showing a circuit configuration of a digital signal reproducing apparatus of the present invention.

FIG. 2 is a diagram showing a locus along which a magnetic head moves on a magnetic tape during special reproduction.

FIG. 3 is a waveform diagram illustrating the operation of the digital signal reproducing device of the present invention.

FIG. 4 is a block diagram showing a circuit configuration of a conventional digital signal reproducing device.

[Explanation of symbols]

1 ... Magnetic tape, 2 ... Magnetic head, 3 ... Preamplifier, 4
... Waveform equalizer, 5 ... Reproduction signal amplitude detector, 6 ... PLL
7 ... Frame synchronization detector, 8 ... Demodulator, 9 ... Error corrector.

Claims (1)

[Claims] 1. A digital reproducing apparatus for reproducing a signal recorded by a modulation method having a limitation of continuity of the same symbol, and reproducing signal amplitude detection means for detecting the amplitude of the reproduced signal and waveform shaping of the reproduced signal. Waveform equalizing means for converting this into a digital signal, and the reproduced signal after the waveform shaping by the waveform equalizing means is inputted,
Based on this, PLL means for generating a clock used for conversion of the waveform equalization means into a digital signal, and frame synchronization detection means for detecting the synchronization signal in the reproduced signal to which the output of the waveform equalization means is input. The demodulation means for demodulating the output of the frame synchronization detection means and adding an error flag to the demodulation data when a modulation signal not used for recording is input at the same time, and an error from the demodulation data and the error flag from the demodulation means Error correction means for performing detection and correction, and in the means from the output of the waveform equalization means to the input of the demodulation means, the reproduction signal is forcibly flagged with an error according to the output of the reproduction signal amplitude detection means. A digital signal reproducing device characterized in that the signal is switched to a signal capable of detecting.