JP2763454B2 - Data detection device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a magnetic recording / reproducing apparatus for recording / reproducing a digital signal, and more particularly to a data detecting apparatus capable of extracting timing with high precision.

[0002]

2. Description of the Related Art In a conventional digital magnetic recording / reproducing apparatus typified by an R-DAT (rotating head digital audio tape recorder), data of a reproduced signal is detected by integral detection.

The operation of a reproducing system of a conventional digital magnetic recording / reproducing apparatus represented by R-DAT will be described with reference to FIG. FIG. 5 shows a block diagram of a reproducing system employed in the conventional R-DAT. In the figure, 1 is a rotary head for reading a signal from a magnetic tape, 2 is an amplifier for amplifying a read reproduction signal, 3 is an equalizer for shaping waveform distortion, and 4 is an integration process for a reproduction signal after equalization. An integration circuit, a zero-cross comparator circuit for discriminating an integrated waveform into a binary digital signal, a PLL (phase-locked loop) circuit for generating a reproduction clock based on an output of the zero-cross comparator, and a binary level. Is a signal processing circuit that demodulates the reproduced data determined to be a digital signal, stores the demodulated data in a memory, and then performs error correction and deshuffling.

In FIG. 5, audio data recorded on a tape is reproduced by a rotary head 1, and a reproduction signal amplified by an amplifier 2 is input to an equalization circuit 3. Waveform distortion and the like peculiar to the electromagnetic conversion system are shaped by the equalization circuit 3 and the equalized reproduction signal is input to the integration circuit 4. Integration circuit 4
The reproduction signal integrated by the above is input to the zero cross comparator 5. The integrated waveform coincides with the recording data at the time of recording, and this determination data becomes reproduction data as it is. Therefore, the PLL circuit 6 can use the edge information of the reproduced data from the zero-cross comparator 5 to generate a reproduced clock synchronized with the reproduced data. The signal processing circuit 7 demodulates the reproduced data in synchronism with the reproduced clock, temporarily stores the data in a memory, reads the data from the memory with a clock having a crystal precision, and performs signal processing such as deshuffling and error correction.

[0005]

A conventional digital magnetic recording / reproducing apparatus reproduces and decodes data in the above-described manner. In recent years, with the progress of digitalization of video equipment, the development of high-density recording / reproduction technology has become an important issue for recording / reproduction of video signals having a much larger data amount than audio signals. Because of high-density recording, crosstalk noise from adjacent tracks cannot be ignored when reproducing video recording data with a narrow track. For this reason, the partial response CLASSIV (hereinafter referred to as PR
4) The adoption of the method has been considered by each company.

According to the present invention, when the PR4 data detection method advantageous for high-density recording as described above is used, a data detection point and a clock extraction point are made to coincide with each other so that a reproduced clock can be generated with high accuracy. The purpose is to:

[0007]

According to a first aspect of the present invention, there is provided a data detecting apparatus, comprising: a reproducing system of a magnetic recording / reproducing apparatus using a PR4 data detecting method; A means for detecting a zero-cross point by detecting a zero level of the reproduced signal and a signal level before and after the zero level is provided, and means for identifying the two types of detected zero-cross points is provided.

The data detecting apparatus according to the second invention has means for detecting a signal level of a differential component of the reproduced signal in the reproduced signal before the (1 + D) arithmetic processing of the reproduced signal, and the continuous differential signal is provided. Means for generating a control signal for identifying the two types of zero-cross points having different timings by detecting a specific pattern.

[0009]

The data detecting apparatus according to the first invention detects the two types of zero-cross points based on the zero-cross points of the reproduced signal at the data detection points and changes in the signal levels before and after the zero-cross points, and identifies the two types of zero-cross points. A reproduction clock can be generated at the data detection point.

The data detecting device according to the second invention detects the level of the differentiated signal of the reproduced signal before the (1 + D) arithmetic processing, and detects a specific pattern of a signal change of the differentiated signal, thereby obtaining the two types of signals. Can be generated.

[0011]

【Example】

Embodiment 1 FIG. An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a block configuration of a digital magnetic recording / reproducing apparatus according to the present invention. Reference numeral 11 in the figure denotes a selection circuit for selecting different types of data such as video, audio, additional function information, and the like. Reference numeral 12 denotes a signal processing circuit that performs shuffling, addition of an error correction codeword, and the like to the selected and input data, and 13 performs (1-D ² ) processing on the data that has been subjected to the signal processing to PR4. A precoder for creating a recording signal; 14 an amplifier for amplifying the recording signal created by the precoder; 15 a recording / playback switch; 16 a recording signal on a magnetic tape; and a signal recorded on the tape. A rotary head for reproducing the reproduced signal, 17 is an amplifier for amplifying the reproduced signal, 18 is an equalizing circuit for shaping the waveform distortion added to the amplified reproduced signal by an electromagnetic conversion system or the like, and 19 is after the equalization. Is an arithmetic processing circuit that performs a process of (1 + D) on the reproduced signal of FIG.

20 is a comparator for converting the reproduced signal after the arithmetic processing into a binary digital signal, 21 is a signal processing circuit for performing deshuffling and error detection / correction processing on the binary-converted reproduced data, 22 is a differentiating circuit for differentiating the reproduced signal after the equalization, 23 is a delay circuit for generating a 1-bit delayed signal of the differentiated signal, and 24 is performing level detection of the differentiated signal and the 1-bit delayed signal to specify A zero-crossing judgment circuit for detecting a change in the signal of the pattern; 25 is an output of the zero-crossing judgment circuit;
A clock detection circuit that generates an extraction signal of a clock component to be compensated from the output of 27, 26 is a delay circuit that generates a delay signal at a specific time interval of the reproduction signal processed by the arithmetic processing circuit 19, and 27 is the specific circuit. A zero-crossing detection circuit for detecting a zero-crossing point from a delay signal at a time interval;
And a zero-crossing selection circuit 29 including a zero-crossing detection circuit 27. The PL 29 generates a reproduced clock based on the clock component extraction signal generated by the clock detection circuit 26.
This is an L (phase locked loop) circuit.

FIG. 2 is a diagram showing an example of a signal waveform at each processing stage of a signal (PR4 type) subjected to signal processing in the digital magnetic recording / reproducing apparatus according to the present invention. Here, the decoding circuit assumes a level decision having a specific threshold, but soft decision such as Viterbi decoding can also be applied. Each waveform is shown in an ideal form without noise or distortion.

FIG. 3 is a diagram showing the properties of two types of zero-cross points of the PR4 type reproduced waveform (after the arithmetic processing).
FIG. 3 (a) shows a zero crossing point of the "Z1 type" where the zero crossing occurs between the sampling points.
(b) “Z2 type” that crosses zero at the sampling point
Represents the zero crossing point of.

FIG. 4 is a block diagram showing a block configuration of the zero cross selection circuit 28. In the drawing, reference numerals 30 and 31 denote delay circuits for outputting a delay signal of the reproduced signal after the arithmetic processing, reference numeral 32 denotes a -peak detection circuit for detecting a peak of the "-1" level of the delay signal, and reference numeral 33 denotes a delay signal of the delay signal. A zero level detecting circuit 34 for detecting a zero level is a + peak detecting circuit for detecting a "+1" level peak of the delay signal.

First, in order to facilitate understanding of the present invention,
The recording / reproducing signal waveform of the PR4 system will be described with reference to FIG. In the PR4 system, video data ([a]) to which an error correction code or the like is added at the time of recording is converted into 1 /
(1-D ^2): by providing (D 1 bit delay operator) consists intentional intersymbol interference ([b]), by the electromagnetic conversion characteristics during reproduction ([c]) (1- D) ( )) And (1 + D) added by the arithmetic processing circuit ([d]) to cancel the interference, thereby forming an efficient recording / reproducing system ([e]). According to this method, the reproduced signal after the (1 + D) arithmetic processing has three values. However, since the recorded data can be reproduced without performing the integration processing, a soft decision can be made. A high-precision decoding circuit can be configured.

In the case of configuring such a reproducing system, when a clock extraction signal (input signal to a PLL) for generating a reproduction clock uses a conventional integration detection, a clock extraction point and a data detection point are used. Therefore, the reproduction clock cannot be generated. Here, as shown by [e], when clock detection is performed at the data detection point of the reproduction waveform unique to the PR4 system, the peak points of the signal levels are P1 and P2.
Since there are two types of zero-cross points and zero-cross points Z1 and Z2 and a non-signal state in the reproduced signal, there are also zero-cross points due to noise. Therefore, there are three types of zero-cross points, making it difficult to generate a reproduced clock. It is.

The operation of the reproduction data generating means necessary for the PR4 clock reproduction will be described below with reference to FIG. After being quantized, the video, audio and additional function information signals are input to the selection circuit 11, and are selected and output to the signal processing circuit 12 according to each signal processing. In the signal processing circuit 12, the video, audio, and additional function information signals are subjected to shuffling for preventing dropout, addition and modulation of an error correction codeword, and the like, and output to the precoder 13 (FIG. 2). The recording signal (FIG. ² ) subjected to 1 / (1-D ² ) processing by the precoder 13 is recorded on the magnetic tape by the rotary head 16 through the amplifier 14 and the recording / reproduction switch 15.

Next, the operation at the time of reproduction will be described with reference to FIGS. The signal reproduced from the magnetic tape by the rotary head 16 is recorded / reproduced by a switch 15 and an amplifier.
The signal is input to an equalizing circuit 18 through 17. The equalization circuit 18 shapes the waveform distortion peculiar to the electromagnetic conversion system generated in the reproduction signal in the recording / reproduction process, and outputs a reproduction signal that is close to an ideal state to the arithmetic processing circuit 19 and the differentiation circuit 22 (FIG. 2). . The arithmetic processing circuit 19 applies (1 + D) to the equalized reproduced signal.
Signal processing. That is, an analog addition of a signal at a certain time and its 1-bit delay signal is performed (FIG. 2).

At this time, the characteristic of 1 / (1-D ² ) given by the precoder at the time of recording is (1-D) by the differential characteristic at the time of reproduction, and (1+) by the arithmetic processing circuit.
D) Due to the addition of the characteristic, {1 / (1−D ² )} × (1−D) × (1 + D) = 1, which is equivalent to a recording signal before precoding. Therefore, the signal after the arithmetic processing can be decoded without performing the integration detection, and it is easy to apply a soft decision which is more power-efficient than a hard decision. The reproduction signal processed by the arithmetic processing circuit 19 is input to a comparator 20 and converted into a binary digital signal in synchronization with a reproduction clock input from a PLL 29. The converted reproduced digital signal is processed by a signal processing circuit.
The data is demodulated, deshuffled, and error-corrected in synchronization with the reproduction clock, and output as decoded video, audio, and additional function information data.

Next, the operation of generating a clock extraction signal for generating a reproduced clock in the PLL 29 will be described. As described above, the PR4 type data detection does not require integral detection. Therefore, if a clock extraction signal is generated using an integrated waveform as in the related art, the data detection point and the clock extraction point will be different, and the steady phase error And so on, it is not possible to generate an accurate reproduction clock. However, as shown in FIG. 2, the data detection point, that is, the reproduced signal after the arithmetic processing has two types of peak signal levels P1 and P2 due to analog addition by the arithmetic processing circuit 19. P1 is a sampling point, and P2 is a peak point generated between the sampling points.

These two types of peak points are practically indistinguishable because it is difficult to determine the level due to white noise superimposed on the reproduced signal or noise that fluctuates at a low frequency. Further, when peak detection is performed by level slicing both signals, the reproduced signal has timing jitter due to amplitude fluctuation or level fluctuation, so that highly accurate timing extraction is impossible.

On the other hand, the zero-crossing point has a relatively small amount of a jitter component that causes timing extraction by a peak level level slice, but when the reproduced signal is in a non-signal state (zero level continues), the white level is reduced. Due to high frequency noise due to noise or the like, a clock is erroneously detected at a timing other than the correct timing. In addition, as shown in FIG. 2, two types of zero cross points Z1 and Z2 also occur, and it is difficult to identify them as with P1 and P2.

Therefore, zero-cross point detection is performed to avoid timing jitter. At this time, a change in signal level near the zero-cross point is also detected at the same time, so that erroneous detection of a no-signal state is avoided. FIG. 4 is a block diagram showing a block configuration of the zero cross selection circuit. As shown in the figure, the reproduction signal after the arithmetic processing can be simultaneously detected by the delay circuits 30 and 31 at a certain sampling point and a signal at a point in time after the point by a specific time interval (for example, 1/2 of the data rate). It has become. Thus, when the zero-level detection circuit 33 detects the zero-level signal level, it is determined whether or not the signal levels at the detection points before and after the zero-level signal have changed to near the + and-peak levels. By the determination by the detection circuit, a zero-cross point in a no-signal state is avoided, and a zero-cross when the signal level changes from + to a peak during a regular sampling interval (or vice versa), That is, only Z1 and Z2 can be detected.

The discrimination between Z1 and Z2 is performed using the detection results at detection points other than the data detection points where Z1 and Z2 can be identified. As shown in FIGS. 3 (a) and (b), Z1 and Z2
Can be identified by the differential waveform of the reproduced signal before signal processing (analog addition). In the case of the Z1 zero cross point, the points at which the signal change of the reproduced signal is the largest by analog addition are added to become a zero cross point. Therefore, the differential components of the signal points to be added are-(or +) peak points. on the other hand,
In the case of the Z2 zero crossing point, one of the signals to be added is in a non-signal state, so that the differential components of the signal before the analog addition processing do not have the same peak value. Using this, the delay circuit 26 and the zero-cross detection circuit 27
The clock detection circuit 25 selects only the output determined to be Z1 from the output of the zero-cross detection circuit 27 and outputs it to the PLL circuit 29.

Since the input signal of the PLL circuit 29 compensates for only the Z1 zero-cross point as described above, the reproduced clock output from the PLL circuit 29 is correctly a channel clock. This output (channel clock) is input to each circuit as a synchronous clock of the comparator 20 and the signal processing circuit 21. If necessary, the output of the zero-crossing judgment circuit 24 is used to output a signal (ie, Z
2 for compensating for (2).

Embodiment 2 FIG. In the above embodiment, the differential signal before analog addition processing of the reproduced signal is used for identifying the zero-cross point. However, the two signals are identified by the difference in signal level change before and after the zero-cross point at the data detection point. The same applies to the case where the circuit scale is to be reduced.

Embodiment 3 FIG. Further, in the above embodiment, the zero cross point Z1, Z1
Although Z2 was identified, if the two signals can be identified, for example, the difference in the slope of the signal change between the Z1 and Z2 zero-cross points using the differential signal of the reproduced signal at the data detection point after analog addition processing is used. It is the same even if is detected.

[0029]

As described above, according to the present invention, PR4
By performing zero-cross detection at the data detection point and discriminating between the two different zero-cross points with respect to the data detection method, a highly accurate reproduced clock can be extracted.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a block configuration of a recording / reproducing system of a digital magnetic recording / reproducing apparatus according to one embodiment of the present invention.

FIG. 2 is a diagram showing signal waveforms at each stage of a signal processing process during reproduction according to an embodiment of the present invention.

FIG. 3 is a diagram illustrating a signal change at a zero-cross point of different types of reproduced signals according to an embodiment of the present invention.

FIG. 4 is a block diagram showing a block configuration of a zero crossing selection circuit according to one embodiment of the present invention.

FIG. 5 is a block diagram showing a block configuration of a reproducing system of a conventional digital magnetic recording / reproducing apparatus.

Claims (2)

(57) [Claims] 1. A magnetic recording and reproducing apparatus for recording and reproducing a digital signal by using a rotary head, partial response CLASSIV (hereinafter, PR4) when using data detection scheme, the reproduction signal at the data detection point, the two "+1" from the level "in a continuous sampling point -
1 level, or "-1" level to "1" level
At a zero crossing point when changing to the +1 "level and at three consecutive sampling points of the reproduction signal, the level changes from the" +1 "level to the" -1 "level via the" 0 "level, or" -1 ". From level "+" via level "+"
Means are provided for detecting and identifying two types of zero-cross points, ie, zero-cross points at the time of changing to the 1 ”level, and detecting only the zero-cross points at the time of directly changing from the“ +1 ”level to the“ −1 ”level. A data detection device, characterized in that: 2. The identification of the two types of zero-cross points is P
In the signal processing of the reproduction system of the R4 data detection method, (1
+ D) operation on the previous reproduction signal processing performed, differential processing performed, data detection device of the differential signal in the range first claim of that patent claims you wherein performing by the pattern of change of the signal level .