KR100192236B1 - A dvcr - Google Patents

Abstract

A digital magnetic recording and reproducing apparatus is provided. In the related art, the coefficient value adjustment, the slice comparison level, and the delay amount adjustment are made by a user by an external input terminal, so that the adjustment value is complicated, inconvenience in use, and BER (Bit). In order to solve this problem, ECC is added during digital data recording, and the error amount is judged according to the ECC result during playback. Delay amount adjustment and slicing to adjust the coefficients for changing the pulse width or phase of the output waveform of the equalizing means, and adjusting the slice comparison timing of the output waveform, after determining the error by By adjusting the slice level of the means, only the existing coefficient adjusting stage, the comparison level stage, and the delay amount adjusting stage It automatically adjusts even the finest case where BER cannot be lowered, thereby increasing the stability of the system, and automatically adjusting the coefficient, comparison level, and delay amount even if the tape, head, and deck types are different. This is to get a lower BER value.

Description

Digital magnetic recorder

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a magnetic recording and reproducing apparatus, and more particularly, to a digital magnetic recording and reproducing apparatus for reproducing data after determining an error amount to correct an error.

Hereinafter, a digital magnetic recording and reproducing apparatus according to the prior art will be described with reference to the accompanying drawings.

FIG. 1 is a block diagram showing a digital magnetic recording and reproducing apparatus according to the prior art, FIG. 2 is a detailed block diagram for a slice portion in FIG. 1, and FIG. 3 is a detailed block diagram for a PLL in FIG. It is a block diagram.

Referring to FIG. 1, the configuration includes an equalizer 10, a slice 20, a latch 30, a delay 40, and a PLL 50.

First, a signal recorded on a digital raw tape or disc is read by a playhead (not shown).

The signal read by the playhead is amplified to a desired signal by a play amplifier (not shown) and output.

Since the amplified reproduction signal is an analog signal, optimal equalization must be made through the equalizer 10 to restore the original data.

The equalizer 10 is adjusted by the user from the outside according to these changes in order to compensate for the change in the waveform according to the change of the head or tape.

The adjusted signal detects an error and adjusts a coefficient value so that a pulse width becomes Tb in order to remove inter-signal interference between adjacent signals.

Here, Tb means the shortest false width to be recorded.

This optimized signal is applied to the slice unit 20 to perform slicing.

Then, the configuration and operation of the slice unit 20 will be described. As shown in FIG. 2, the slice unit 20 is a three-level comparison unit for converting the signal output from the equalizer 10 into digital data according to an external comparison level input in order to convert the signal output to the original digital data. 21; The OR gate 22 is configured to OR the signal output from the three-level comparison unit 21.

Here, the three-level comparator 21 includes first and second amplifiers 21a and 21b for inverting and non-inverting and outputting the signal output from the equalizer 10; A first fertilizer section 21c for comparing the signal output from the first amplifier section 21a with the comparison level signal input from the outside and outputting the comparison signal to the or gate 22; And a second comparator 21d for comparing the signal output from the second amplifier 21b with the comparison level signal input from the outside and outputting the comparable level signal to the or gate 22.

An operation of the slice unit 20 configured as described above will be described.

The signals output from the equalizer 10 are inverted and non-inverted and amplified by the first and second amplifiers 21a and 21b, respectively, and input to the first and second comparators 21c and 21d, respectively.

The first comparator 21c compares the non-inverted amplified signal input from the first amplifier 21a with a comparison level input from the outside and outputs the comparison level to the or gate 22.

At this time, the first comparator 21c outputs high when the output of the first amplifier 21a is greater than the input comparison level and low when the input comparison level is greater than the amplified output signal. .

Similarly, the second comparator 21d outputs high when the signal output from the second amplifier 21b is greater than the comparison level, and low otherwise. The signals output from the first and second comparators 21c and 21d are ORed at the OR gate 22 to be input to the PLL 50 to recover the original clock, and to restore the original data. It is input to the latch part 30.

Here, the configuration and operation of the PLL 50 will be described with reference to FIG.

First, the configuration thereof includes: a delay unit 51 for delaying a sliced signal output from the slice unit 20 by a predetermined Tb width; An exclusive or gate 52 for exclusively ORing the delayed signal and the sliced signal output from the slice unit 20; A voltage controlled oscillator (VCO) 55 varying an oscillation frequency by an input frequency; A phase detector 53 for detecting a phase error by comparing a phase of a clock output from the VCO 55 and a signal output from the exclusive or gate 52; The filter unit 54 performs low pass filtering on the detected phase error.

Referring to the operation of the above configuration, first, the PLL (50) is a circuit for restoring the original clock by minimizing the phase error by comparing the phase of the signal sliced from the slice section 20 and the signal output from the VCO (55) .

The input signal sliced by the slice unit 20 is delayed by a predetermined Tb in the delay unit 51 to have many clock components.

The signal delayed by the delay unit 51 and the signal sliced by the slice unit 20 are exclusively ORed in the logic circuit exclusive or gate 52 to have a clock component.

At this time, the phase detector 53 detects the phase error by comparing the phase of the signal output from the exclusive or gate 52 and the signal of the clock component output from the VCO 55.

The detected phase error is low-pass filtered by the filter unit 54 to vary the oscillation frequency of the VCO 55.

In this case, when there is no data among the data output from the slice unit 20, that is, 0 or 1 continues, the above configuration is performed even when the exclusive delay is performed with the signal delayed by the exclusive or gate 52. There is no clock component at.

Therefore, the waveform is continuously shaken without reducing the phase error.

Here, the phase detector 53 performs phase comparison only when the output of the exclusive or gate 52 is high to detect phase error.

As described above, the original clock is extracted from the PLL 50 and the extracted clock is input to the latch unit 30 by adjusting the delay amount by the external adjustment terminal in the delay unit 40. The latch unit 30 latches the output of the or gate 22 of the slice unit 20 according to the output clock of the delay unit 40.

All of these processes are performed to obtain playback data and playback clock. These two signals are input to the digital signal processing block to obtain a desired screen.

The digital magnetic recording and reproducing apparatus according to the prior art cannot use error information generated in an error correction code (ECC) circuit of a digital signal processing block, that is, information on how much error correction is occurring by looking at an added error correction code in advance. .

Therefore, by adjusting the coefficient value of the equalizer, the comparison level of the slice, and the delay amount by the user by the external input terminal, the complicated adjustment of the adjustment value and the BER (Bit Error Rate) value are increased to achieve high quality. There is a problem that cannot be displayed on the screen.

Therefore, an object of the present invention for solving the above problems according to the prior art is to automatically adjust the coefficients, comparison level, delay amount adjustment using the number of error correction output from the ECC and the number of 1, 0 of the output data Therefore, the present invention provides a digital magnetic recording and reproducing apparatus for achieving a lower BER.

1 is a block diagram showing a digital magnetic recording and reproducing apparatus according to the prior art.

2 is a detailed block diagram of a slice part in FIG. 1;

FIG. 3 is a detailed block diagram of the PLL unit in FIG.

4 is a block diagram showing a digital magnetic recording and reproducing apparatus according to the present invention.

5A is an operational flowchart showing a coefficient adjusting method of the equalizer of FIG. 4 according to the present invention.

5B is an operational flowchart showing a method of adjusting the slice level of the slice of FIG. 4 according to the present invention.

FIG. 5C is an operational flowchart showing a method of adjusting the delay amount of the FIG. 4 delay unit according to the present invention. FIG.

* Explanation of symbols for main parts of the drawings

10: equalizer 20: slice

30 latch portion 40 delay portion

50: PLL 60: Interface

70: ECC 80: control unit

90: A / V signal processing unit

A feature of the digital magnetic recording and reproducing apparatus according to the present invention is to add and record ECC when recording digital data and to determine the amount of error according to the ECC result during reproduction, and to correct the error by one method according to the result and output the reproduced data. There is a characteristic.

According to another aspect of the present invention, there is provided a method for adjusting a coefficient for changing a pulse width or a phase of an output waveform of an equalizing means, a delay amount adjusting method for adjusting slice comparison timing of an output waveform, and a slice for a slice means. It is characteristic to correct the amount of error by the method of adjusting the level.

Hereinafter, a digital magnetic recording and reproducing field according to the present invention will be described with reference to the accompanying drawings.

4 is a block diagram showing a digital magnetic recording and reproducing apparatus according to the present invention.

Referring to FIG. 4, the configuration of the equalizer 10, the slice 20, the latch 30, the PLL 50, and the delay 40 is configured according to the prior art of FIG. 1. Since the description is the same as that, the description will be omitted.

The interfacing unit converts the serial data of the playback data output from the latch unit 30 and the playback clock output from the delay unit 40 into a parallel signal, and determines and outputs the number of input data 1 and 0. 60; An ECC unit 70 for correcting an error of data output from the interfacing unit 60 and outputting information on the number of errors generated: using the error number information and 1, 0 numbers of data output from the interface unit 60; And the controller 80 which provides coefficient adjustment information to the equalizer 10, slice comparison level adjustment information to the slice unit 20, and delay amount information to the delay unit 40, respectively.

At this time, the playback data corrected by the ECC 70 is displayed through the A / V signal processing unit (9).

Referring to the principle of operation according to the above configuration, first, the operation of the same components that overlap with the first degree will be omitted.

As shown in FIG. 2, the playback data output from the latch unit 30 and the playback clock output from the delay unit 40 are first input to the digital interface unit 60 to obtain information for the original screen. .

The interface unit 60 is applied to the ECC 70 to convert an input serial signal into a parallel signal to correct an error, and detects the number of data 1 and 0 to adjust the comparison level. 80).

The ECC 70 corrects an error according to an error correction code added in advance.

Then, the number of errors generated is applied to the controller 80.

On the other hand, the error-corrected signal is applied to the A / V signal processing unit 90 is displayed.

Based on the number information of 1 and 0 of the data and the error information provided by the ECC 70, the controller 80 adjusts the control signal for adjusting the coefficients of the equalizer 10 and the slice comparison level of the slice unit 20. It is to provide a control signal for adjustment.

In addition, the delay amount control signal for adjusting the delay amount of the delay unit 40 is also provided.

At this time, the comparison level adjustment signal and the delay amount adjustment signal are added to the output of the controller 80 and the external adjustment input value to adjust each of the above.

In other words, the error information received by the controller 80 is inputted to the ECC 70 through the conversion of the serial signal from the interface signal 60 to the reproduction clock other than the playback data.

The number of error corrections extracted by this ECC 70 is used.

In addition, the number information of 1 and 0 obtained by the interface unit 60 is used.

Using these two pieces of information, the above coefficients, comparison levels, and delay amounts are adjusted.

Here, the coefficient adjustment, the comparison level adjustment, and the delay amount adjustment method will be described with reference to the flowcharts of FIGS. 5A, 5B, and 5C.

FIG. 5A is an operational flowchart showing a method of adjusting the coefficients of the equalizer of FIG. 4 according to the present invention. FIG. 5B is an operational flowchart showing a method of adjusting the slice level of the FIG. 4 slice in accordance with the present invention. 4 is a flowchart illustrating a method of adjusting the delay amount of the delay unit of FIG. 4 according to the present invention.

First, referring to FIG. 5A, the coefficient adjusting method of the equalizer 10 is received by the controller 80 receiving the number of 1s and 0s from the interface unit 60 and the error correction number from the ECC 70 ( S101) The comparison level of the slice unit 20 is adjusted (S102).

When the reproduction data and the reproduction clock output by adjusting the comparison level are applied to the control unit 80 through the interface unit 60, the control unit 80 determines whether the number of 1s and 0s is substantially the same (S103). When the number of 1s and 0s does not match, the first coefficient adjustment process is performed again, and when the number of 1s and 0s is almost identical, the coefficients are adjusted again according to the coincidence value (S104).

If the coefficient adjustment of the equalizing unit 10 is adjusted as described above (S104), and the control unit 80 determines whether the error correction number provided by the ECC 70 is increased or decreased (S105), it is determined that the error correction number is not reduced. Then, the equalization unit 10 is adjusted again using this information.

However, if the controller 80 determines that the error correction number applied by the ECC 70 decreases, it is determined again that the error correction number is no longer changed, and if it is determined that no further error correction number is changed (S106). The coefficient adjustment of the unit 10 is completed.

Next, referring to FIG. 5B, a method of adjusting the comparison level of the slice unit 20 receives the number of 1s and 0s from the interface unit 60 and the number of error corrections from the ECC 70 from the controller 80. (S201) The comparison level of the slice unit 20 is adjusted (S202).

When the reproduction data and the reproduction clock output by adjusting the comparison level of the slice unit 20 are applied to the control unit 80 through the interface unit 60, the control unit 80 almost matches the number of 1, 0. If the number of 1s and 0s does not coincide with each other (S203), the first comparison level adjustment process is performed again, and if almost equal, the comparison level is adjusted again according to the coincidence value (S204).

As described above, the comparison level of the slice unit 20 is adjusted (S104), and the controller 80 determines whether the error correction number provided by the ECC 70 is increased or decreased (S202) and determines that the error correction number is not reduced. In this case, the comparison level of the slice unit 20 is adjusted again using this information.

However, if it is determined that the error correction number applied by the ECC 70 decreases, the controller 80 determines whether the error correction number changes further or not and determines that there is no change in the error correction number (S206). Comparing level adjustment of the slice part 20 is completed.

Next, referring to FIG. 5C, a delay adjustment method of the delay unit 40 will be described. The controller 80 receives the number of 1s and 0s and the error correction number of the ECC 70 from the interface unit 60. (S201) The comparison level of the slice unit 20 is adjusted (S302).

When the reproduction clock output by adjusting the comparison level of the slice unit 20 is applied to the control unit 80 through the interface unit 60, the control unit 80 determines whether the number of 1s and 0s is almost identical. (S303) If the number of 1s and 0s does not match, the first delay amount adjustment process is performed again, and if almost equal, the delay amount of the delay unit 40 is adjusted again according to the match value (S304).

As described above, the delay amount of the delay unit 40 is adjusted (S104), and the control unit 80 determines whether the error correction number provided by the ECC 70 is increased or decreased (S305) and determines that the error correction number is not reduced. If so, the delay amount of the delay unit 40 is adjusted again using this information.

However, if it is determined that the error correction number applied by the ECC 70 decreases, the controller 80 determines whether the error correction number is changed further and determines that there is no change in the error correction number (S306). The delay amount adjustment of the delay unit 40 is completed.

The digital magnetic recording and reproducing apparatus according to the present invention uses the number information of 1 and 0 for the reproduction data and the reproduction clock and the error correction number information of the ECC. Only the coefficient adjustment stage, the comparison level stage, and the delay amount adjustment stage automatically adjust the fine case where the BER cannot be lowered, thereby increasing the stability of the system.

In addition, even if the tape, the head, the deck, etc. are different, there is an advantage that the lower BER value can be obtained by automatically adjusting the coefficient, the comparison level and the delay amount.

Claims (4)

A digital magnetic recording and reproducing apparatus, comprising: reproducing means for reproducing recorded A / V data; ECC for calculating error correction and error amount of the reproduced data and outputting information of the number of error correction numbers: coefficients for changing the pulse width or phase of the output waveform according to the information output from the ECC, and slices of the output waveform Delay means for adjusting the comparative timing and control means for adjusting the slice level; And means for correcting the generated error and outputting reproduction data according to the control of the control means. A digital magnetic recording and reproducing apparatus, comprising: reproducing means for reproducing recorded A / V data; Means for performing optimal equalization to restore the reproduced reproduced signal to original data; Means for slicing the optimized equalized signal according to one slice level adjustment signal; Means for correcting errors in the sliced outputted data and calculating and outputting an error amount; And a coefficient for changing the pulse width or phase of the output waveform according to the calculated error amount, a delay amount for adjusting slice comparison timing of the output waveform, and a control means for adjusting slice level. Digital magnetic recording and playback device. A digital magnetic recording and reproducing apparatus, comprising: reproducing means for reproducing recorded A / V data; Interfacing means for converting the serial data of the reproduced data and the reproduced clock to be reproduced into a parallel signal and outputting the same, and determining and outputting the number of 1s and 0s of the inputted data; And means for correcting an error of data output from the interfacing means and outputting error number information; And control means for providing coefficient adjustment information, slice comparison level adjustment information, and delay amount information by using the error number information and the number 1 and 0 of the data output from the interfacing means, respectively. Device. A digital magnetic recording and reproducing apparatus, comprising: a reproducing unit for reproducing recorded data; An equalization unit performing optimal equalization according to one control signal to restore the reproduced reproduced signal to original data; A slice unit for slicing the optimized equalized signal according to one slice level adjustment signal; A latch unit for latching a slicing signal output from the slice unit according to a signal provided to output reproduction data; A PLL for extracting and outputting an original clock from the sliced signals output from the slice unit; A delay unit adjusting the delay amount of the extracted clock according to a control signal to provide a signal to the latch unit and output a reproduction clock; An interface unit for converting and outputting a serial signal of a reproduction clock output from the latch unit and a reproduction clock output from the delay unit into a parallel signal, and determining and outputting the number of input data 1 and 0; An ECC correcting an error of data output from the interface unit and outputting information on the number of errors generated; The controller 80 provides coefficient adjustment information to the equalizer, slice comparison level adjustment information to the slice unit, and delay amount information to the delay unit using the error number information and the number 1 and 0 of data output from the interface unit. Digital magnetic recording and reproducing apparatus, characterized in that consisting of).