KR19980014888A - Digital magnetic recording and reproducing apparatus - Google Patents

Abstract

A digital magnetic recording and reproducing apparatus has been conventionally provided in which a coefficient adjustment, a slice comparison level and a delay amount adjustment are made by user's adjustment by an external input terminal, thereby complicated adjustment of the adjustment value, inconvenience in use, and BER In order to solve this problem, an error correction code (ECC) is added to the digital data for recording, and an error amount is determined according to the ECC result at the time of reproduction, To adjust the coefficient for changing the pulse width or phase of the output waveform of the equalizing means by the control means and to adjust the delay amount adjustment for adjusting the slice comparison timing of the output waveform And adjusting the slice level of the slice means so that the existing coefficient adjustment stage, the comparison level stage, the delay amount adjustment It is possible to increase the stability of the system by automatically adjusting to the minute where the BER can not be lowered only by the user, and the coefficient, the comparison level and the delay amount are automatically adjusted even if the types of the tape, So that a low BER value can be obtained.

Description

Digital magnetic recording and reproducing apparatus

The present invention relates to a magnetic recording and reproducing apparatus and, more particularly, to a digital magnetic recording and reproducing apparatus for correcting an error by judging an error amount and reproducing data.

Hereinafter, a digital magnetic recording and reproducing apparatus according to the related art will be described with reference to the accompanying drawings.

FIG. 1 is a block diagram showing a conventional digital magnetic recording and reproducing apparatus, FIG. 2 is a detailed block diagram of a slice unit in FIG. 1, FIG. 3 is a detailed block diagram of a PLL in FIG. to be.

Referring to FIG. 1, the PLL 50 includes an equalizer 10, a slice 20, a latch 30, a delay unit 40, and a PLL 50.

First, a signal recorded on a tape or a disc by digital signals is read using a reproducing head (not shown).

The signal read by the reproducing head is amplified to a desired signal size by a reproducing amplifier (not shown) and output.

Since the amplified reproduced signal is an analog signal, optimal equalization must be performed through the equalizer 10 in order to restore the original data.

In order to compensate for the change in the waveform according to the change of the head or the tape, the equalizer 10 performs adjustment by the user from the outside in accordance with these changes.

The adjusted signal detects an error so that the pulse width becomes Tb in order to eliminate intersymbol interference between adjacent signals, and adjusts the count value.

Here, Tb means the shortest pulse width to be recorded.

The optimum equalized signal is applied to the slice portion 20 to perform slicing.

Hereinafter, the detailed configuration and operation of the slice unit 20 will be described.

2, the slice unit 20 includes a 3-level comparator (not shown) for converting a signal output from the equalizer 10 into digital data according to an external comparison level input to convert the signal output from the equalizer 10 into original digital data 21); And an orgate 22 for performing a logical OR of the signals output from the three-level comparator 21.

The 3-level comparator 21 includes first and second amplifiers 21a and 21b for inverting and non-inverting the signal output from the equalizer 10 and outputting the amplified signal. A first comparator 21c for comparing the signal output from the first amplifier 21a with the comparison signal input from the outside and outputting the compared signal to the orgate 22; And a second comparing unit 21d comparing the signal output from the second amplifying unit 21b with the externally inputted comparison level signal and outputting the compared signal to the orgate 22.

Hereinafter, the operation of the slice unit 20 constructed as described above will be described.

The signals output from the moving picture unit 10 are respectively inversed and non-inverted amplified by the first and second amplification units 21a and 21b and input to the first and second comparison units 21c and 21d, respectively.

The first comparing unit 21c compares the non-inverted amplified signal inputted from the first amplifying unit 21a with the externally inputted comparison level and outputs the comparison result to the orgate 22. [

At this time, the first comparator 21c outputs a high if the output of the first amplifier 21a is higher than the input comparative level, and outputs a low if the input comparator is higher than the amplified output signal.

Similarly, the second comparator 21d outputs a high signal if the signal output from the second amplifier 21b is higher than the comparison level, and outputs a low signal if the signal is higher than the comparison level.

Signals output from the first and second comparing units 21c and 21d are ORed in the OR gate 22 and input to the PLL 50 to restore the original clock and are also used to recover the original data And is input to the latch unit 30.

Here, the configuration and operation of the PLL 50 will be described with reference to FIG.

First, a delay unit 51 for delaying the sliced signal output from the slice unit 20 by a predetermined Tb width will be described. An exclusive OR gate 52 for exclusive ORing the delayed signal and the sliced signal output from the slice unit 20; A VCO (Voltage Controlled Oscilator) 55 for varying the oscillation frequency according to the input frequency; A phase detector 53 for detecting a phase error by comparing a phase of a clock output from the VCO 55 with a phase of a signal output from the external clock 52; And a filter unit 54 for performing low pass filtering on the detected phase error.

The PLL 50 includes a circuit for restoring an original clock by minimizing a phase error by comparing phases of a signal sliced by the slice unit 20 and a signal output from the VCO 55, to be.

The input signal sliced by the slice unit 20 is delayed by a predetermined Tb in the delay unit 51 so as to have a large amount of clock components.

The signal delayed by the delay unit 51 and the signal sliced by the slice unit 20 are exclusive-ORed by the logic circuit exclusive OR gate 52 to have a clock component.

At this time, the phase detector 53 detects the phase error by comparing the phase of the signal outputted from the exclusive OR gate 52 and the signal of the clock component outputted from the VCO 55.

The detected phase error is low-pass filtered by the filter unit 54 to vary the oscillation frequency of the VCO 55. [

At this time, when there is no data among the data output from the slice unit 20, that is, when 0 or 1 is continued, even if the exclusive ORing is performed with the signal delayed by the exclusive OR gate 52, There is no clock component.

Therefore, the phase error is not reduced, and the waveform is continuously shaken.

Here, the phase detector 53 detects the phase error by performing phase comparison only when the output of the alternating-current gate 52 is high.

As described above, the original clock is extracted from the PLL 50, and the extracted clock is input to the latch unit 30 by adjusting the delay amount by the external control terminal in the delay unit 40.

The latch unit 30 latches the output of the OR gate 22 of the slice unit 20 according to the output clock of the delay unit 40.

All of these processes are performed to obtain reproduction data and reproduction clock.

These two signals are input to a digital signal processing block to obtain a desired image.

The digital magnetic recording and reproducing apparatus according to the prior art can not use information on how much error correction is taking place in view of error information generated in an ECC (Error Correction Code) circuit of a digital signal processing block, that is, an error correction code added in advance.

Therefore, the adjustment of the coefficient value of the equalizing section, the comparison level of the slice section, and the adjustment of the delay amount of the delay section are performed by the user's adjustment by the external input terminal, so that the adjustment of the adjustment value and the bit error rate (BER) There is a problem that it can not be displayed on the screen.

SUMMARY OF THE INVENTION Accordingly, the present invention has been made to solve the above problems occurring in the prior art, and it is an object of the present invention to automatically adjust the coefficient, the comparison level, and the delay amount adjustment using the number of error corrections outputted from the ECC and the number of 1, And to provide a digital magnetic recording and / or reproducing apparatus capable of obtaining a lower BER.

1 is a block diagram showing a digital magnetic recording and reproducing apparatus according to the prior art;

Fig. 2 is a detailed block diagram of the slice portion in Fig. 1

3 is a detailed block diagram of the PLL in FIG.

4 is a block diagram showing a digital magnetic recording and reproducing apparatus according to the present invention.

FIG. 5A is a flowchart showing a method of adjusting a coefficient of the equalization unit of FIG. 4 according to the present invention.

FIG. 5B is a flowchart illustrating a method of adjusting a slice level of the FIG. 4 slice according to the present invention.

FIG. 5C is a flow chart showing a method of adjusting the delay amount of the delay unit of FIG. 4 according to the present invention.

Description of the Related Art [0002]

10: equalizer 20: slice

30: latch unit 40: delay unit

50: PLL60:

70: ECC80:

90: A / V signal processor

A digital magnetic recording and reproducing apparatus according to the present invention is characterized in that an ECC is added for recording digital data and an error amount is determined according to an ECC result upon reproduction, and an error is corrected by a predetermined method according to the result, .

According to another aspect of the present invention, there is provided a method of adjusting a coefficient for changing a pulse width or phase of an output waveform of an equalizing means, a delay amount adjusting method for adjusting a slice comparing timing of an output waveform, There is a characteristic in that the amount of error is corrected by the method of adjusting the level.

Hereinafter, a digital magnetic recording and reproducing apparatus according to the present invention will be described with reference to the accompanying drawings.

4 is a block diagram showing a digital magnetic recording and reproducing apparatus according to the present invention.

The configuration of the equalizer 10, the slice 20, the latch 30, the PLL 50, and the delay unit 40 will be described with reference to FIG. The description will be omitted.

An interface unit for converting the reproduction data output from the latch unit 30 and the serial signal of the reproduction clock output from the delay unit 40 into a parallel signal and outputting the serial data to determine the number of 1's and 0's of input data, (60); An ECC unit 70 for correcting an error of data output from the interfacing unit 60 and outputting the number of generated errors; Count adjustment information is supplied to the equalizer 10 using the number of error information and the number of 1's and 0's of data output from the interface unit 60 and slice comparison level adjustment information is supplied to the slice unit 20, And a control unit 80 for providing the delay amount information to the control unit 80, respectively.

At this time, the error-corrected reproduction data in the ECC 70 is displayed through the A / V signal processor 9.

Referring to the operation principle according to the above configuration, the description of the operation of the same components as those of FIG. 1 will be omitted.

2, the reproduction data output from the latch unit 30 and the reproduction clock output from the delay unit 40 are first input to the digital interface unit 60 in order to obtain information for the original screen.

The interface unit 60 is applied to the ECC 70 in order to convert an input serial signal into a parallel signal and correct the error. The interface unit 60 detects the number of the data 1, 0 and supplies information for adjusting the comparison level to the control unit (80).

The ECC 70 corrects an error according to an error correction code added in advance.

Then, the number of generated errors is applied to the control unit 80.

On the other hand, the error corrected signal is applied to the A / V signal processing unit 90 and displayed.

The control unit 80 adjusts the control signal for adjusting the coefficient of the equalizer 10 and the slice comparison level of the slice unit 20 based on the information on the number of 1's and 0's of the data and the error information provided in the ECC 70 To provide a control signal for performing the above operation.

It also provides a delay amount control signal for adjusting the delay amount of the delay unit 40. [

At this time, the comparison level adjustment signal and the delay amount adjustment signal are added to the output of the controller 80 and the external adjustment input value, respectively, to adjust the comparison level adjustment signal and the delay amount adjustment signal.

In other words, the error information received by the control unit 80 is input to the ECC 70 through the interface unit 60 through the conversion of the serial signal to the parallel signal.

The error correction number extracted from the ECC 70 is used.

In addition, the information of the number of 1's and 0's obtained from the interface section 60 is used.

By using these two pieces of information, the coefficient, the comparison level and the delay amount are adjusted.

Here, the coefficient adjustment, the comparison level adjustment, and the delay amount adjustment method will be described with reference to the flow charts of FIGS. 5A, 5B, and 5C.

FIG. 5A is an operation flow chart showing a method of adjusting a coefficient of the FIG. 4 equalization unit according to the present invention, FIG. 5B is an operation flow chart showing a method of adjusting a slice level of the FIG. 4 slice unit according to the present invention, Fig. 4 is a flowchart showing a method of adjusting the delay amount of the delay unit according to the embodiment of the present invention.

First, referring to FIG. 5A, a method of adjusting a coefficient of the equalizer 10 will be described. The controller 80 receives the number of 1's and 0's and the number of error corrections in the ECC 70 in the interface unit 60 (S101 ) The comparison level of the slice section 20 is adjusted (S102).

When the reproduction data and the reproduction clock outputted by adjusting the comparison level are applied to the control unit 80 through the interface unit 60, the control unit 80 determines whether the number of 1's and 0's are almost identical to each other (S103) If the number of 1's and 0's do not coincide with each other, the first coefficient adjustment process is performed again, and if the numbers coincide with each other, the coefficient is adjusted again according to the matching value (S104).

The control unit 80 determines whether the number of error correction provided by the ECC 70 is increased or decreased (S105). If it is determined that the number of error correction is not decreased , And the coefficient of the equalizer 10 is adjusted again using this information.

However, if it is determined that the number of error correction numbers applied by the ECC 70 is decreasing, the control unit 80 determines whether the number of error correction is further changed (S106) And the coefficient adjustment of the equalizer 10 is completed.

Next, referring to FIG. 5B, a method of adjusting the comparison level of the slice unit 20 will be described. The control unit 80 receives the number of 1's and 0's and the number of error corrections in the ECC 70 in the interface unit 60 S201) The comparison level of the slice section 20 is adjusted (S202).

When the reproduction data and the reproduction clock output from the comparison level adjustment of the slice unit 20 are applied to the control unit 80 through the interface unit 60, the control unit 80 determines whether the number of 1's and 0's are almost the same If it is determined that the number of 1's and 0's do not coincide with each other, the first comparison level adjustment process is performed again, and if the number of 1's and 0's match each other, the comparison level is adjusted again according to the matching value (S204).

The control section 80 determines whether the number of error corrections provided by the ECC 70 is increased or decreased (S205), and determines that the number of error corrections is not decreased The comparative level of the slice section 20 is adjusted again using this information.

However, when it is determined that the number of error corrections applied by the ECC 70 is decreasing, the control unit 80 determines whether the number of error corrections further changes (S206) The comparison level adjustment of the slice section 20 is completed.

Next, referring to FIG. 5C, a method of adjusting the delay amount of the delay unit 40 will be described. The control unit 80 receives the number of 1's and 0's in the interface unit 60 and the number of error corrections in the ECC 70 S301) The comparison level of the slice section 20 is adjusted (S302).

When the control unit 80 receives the reproduction clock output from the slice unit 20 through the interface unit 60, the control unit 80 determines whether the number of the 1's and 0's are substantially the same S303) If the number of 1's and 0's do not coincide with each other, the first delay amount adjustment process is performed again, and if it is substantially coincident, the delay amount of the delay unit 40 is adjusted again according to the matching value (S304).

The control unit 80 determines whether the number of error correction provided by the ECC 70 is increased or decreased (S305), and determines that the number of error correction is not decreased The delay amount of the delay unit 40 is adjusted again by using this information.

If it is determined in step S306 that there is no further change in the number of error corrections, the control unit 80 determines whether the number of error corrections applied to the ECC 70 has decreased. The delay amount adjustment of the delay unit 40 is completed.

The digital magnetic recording and reproducing apparatus according to the present invention can adjust the coefficient of the equalizing unit, the comparison level of the slicing unit, and the delay amount of the delay unit using the information of the number of 1's and 0's of the reproduced data and the reproduced clocks and the error correction number information of the ECC, It is advantageous that the stability of the system can be improved by automatically adjusting to the fine case where the BER can not be lowered only by the coefficient adjustment stage, the comparison level stage, and the delay amount adjustment stage alone.

Further, even when the types of the tape, the head, and the deck are different, there is an advantage that a lower BER value can be obtained because the coefficient, the comparison level and the delay amount are automatically adjusted.

Claims (4)

In a digital magnetic recording and reproducing apparatus, Reproduction means for reproducing the recorded A / V data; An ECC for calculating an error correction amount and an error amount of the reproduced data and outputting information of the number of error correction; Control means for adjusting a coefficient for changing the pulse width or phase of the output waveform to be output in accordance with the information output from the ECC, a delay amount for adjusting the slice comparison timing of the output waveform, and a slice level; And means for correcting the generated error under control of the control means and outputting reproduction data. In a digital magnetic recording and reproducing apparatus, Reproduction means for reproducing the recorded A / V data; Means for performing an optimum equalization to restore the reproduced reproduction signal to original data; Means for slicing the optimal equalized signal according to a one-slice level adjustment signal; Means for correcting an error of the sliced and outputted reproduction data and calculating and outputting an error amount; A coefficient for changing the pulse width or phase of the output waveform to be output in accordance with the calculated error amount, a delay amount for adjusting the slice comparison timing of the output waveform, and a slice level. Digital magnetic recording and reproducing apparatus. In a digital magnetic recording and reproducing apparatus, Reproduction means for reproducing the recorded A / V data; An interfacing means for converting the reproduced reproduction data and the reproduced clock serial signal into a parallel signal, outputting the result, determining the number of 1's and 0's of input data, and outputting the result; Means for correcting an error of data output from the interfacing means and outputting information on the number of errors generated; And control means for providing count adjustment information, slice comparison level adjustment information, and delay amount information, respectively, by using the error number information and the number of 1's and 0's of data output from the interfacing means. Device. In a digital magnetic recording and reproducing apparatus, A reproducing unit for reproducing the recorded data; An equalizer for performing optimal equalization according to one control signal to restore the reproduced reproduction signal to original data; A slice unit for slicing the optimal equalized signal according to a one-slice level adjustment signal; A latch unit for latching the slicing signal output from the slicing unit according to a provided signal and outputting reproduction data; A PLL for extracting and outputting an original clock among the sliced signals output from the slice unit; A delay unit for adjusting a delay amount of the extracted clock according to a control signal to provide a signal to the latch unit and outputting a reproduction clock; An interface unit for converting the reproduction data output from the latch unit and the serial data of the reproduction clock output from the delay unit into a parallel signal and outputting the data, determining the number of 1's and 0's of input data, and outputting the parallel data; An ECC for correcting an error of data outputted from the interface and outputting information on the number of generated errors; A controller 80 for providing coefficient adjustment information to the equalizer, slice comparison level adjustment information to the slice section, and delay amount information to the delay section using the number of error information and the number of data 0 and 0 outputted from the interface section, respectively And a magnetic recording and / or reproducing apparatus.