JPH09102172A - Magnetic reproducing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a magnetic reproducing device capable of reproducing data from a recording medium with good precision. SOLUTION: An A/D converter 7 samples signal 10 in synchronism with SCL 130 and outputs the signal 130. A comparator 101 detects '1' of PR(1, 0, -1) from (signal 13)>(threshold: signal level S3), and outputs '1' of the signal 120. A delayed signal 121 delayed from the signal 120 by one clock and the signal 120 are inputted to an AND circuit 103, and when its output is '1', an amplitude comparator 104 outputs '1' of a signal 123 indicating that SCL 130 is phase-advanced. Here, a signal level S5 is a reference value of a signal 10 corresponding to '1' of PR(1, 0, -1). A phase control circuit 111 corrects a phase error of SCL 130 according to a phase control signal 129 obtained from smoothing the signal 123 in an integration circuit 110.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a magnetic reproducing apparatus for reproducing digital data recorded on a magnetic recording medium such as a magnetic tape or a magnetic disk.

[0002]

2. Description of the Related Art In recent years, a digital VTR (video tape recorder) for recording and reproducing digital data such as image information and audio information on a magnetic recording medium has been put into practical use. Generally, data recorded on a recording medium is subjected to a recording process so that the data can be reproduced from the recording medium with high accuracy. Specifically, the recorded data is
First, it is modulated into an intermediate code sequence belonging to a modulation method suitable for the characteristics of the recording medium. The modulated data is subjected to coding processing such as compression coding and recorded on a recording medium.

Further, the data recorded on the recording medium is reproduced as an analog signal while being subjected to the recording process, while being subjected to the reproducing process according to the characteristics of the recording medium and the reproducing apparatus. . The reproduced analog signal is converted into a digital signal, and the intermediate code sequence is identified from the digital signal. The intermediate code sequence is
After demodulation and decoding, the data is taken out as data that can be processed only after further error correction processing.

FIG. 10 is a block diagram showing the structure of a conventional magnetic reproducing apparatus 20 for reproducing digital information recorded on the magnetic tape 1. The magnetic reproduction device 20 includes a magnetic tape 1, a reproduction head 2, a reproduction amplifier 3, a partial response equalization circuit 4, and a PLL (phase lock loop).
A circuit 5, a delay adjuster 6, an A / D converter 7 and a Viterbi decoder 8 are provided.

On the magnetic tape 1, as the recording process,
Interleaved NRZI (non return to zero-inver
The data modulated into the intermediate code sequence (channel code) such as se) is recorded. Interleaved NRZI
Is an intermediate code sequence developed in the field of data communication and is classified into partial response class 4 (hereinafter referred to as “PR4”). The interleaved NRZI
Is an intermediate code sequence in which the code sequence composed of even-numbered codes and the code sequence composed of odd-numbered codes are NRZI, and take three values of (1, 0, -1) in the reproducing system.

The reproducing head 2 reproduces a reproduced signal, which is an analog signal having information indicating individual code values in the intermediate code sequence recorded on the magnetic tape 1 at a signal level of its voltage waveform at regular time intervals. To do. The reproduction amplifier 3 is
The reproduction signal reproduced from the magnetic tape 1 is amplified. The partial response equalization circuit 4 equalizes the waveform of the amplified reproduction signal and outputs a signal 10. Waveform equalization will be described below. In the case of a digital VTR or the like, the frequency characteristic of the reproducing system is deteriorated due to the material of the magnetic tape 1 which is a recording medium, the gap between the reproducing head 2 and the magnetic tape 1 generated during reproduction, and the like. To do. For example, as a result, in the reproduced signal, the signal level corresponding to "0" of two consecutive codes "10" of the intermediate code sequence does not become the signal level exactly corresponding to "0", and the immediately preceding code " The phenomenon of being biased toward the side corresponding to "1" occurs. Similarly, a phenomenon occurs in which the signal level of the reproduced signal corresponding to "1" of two consecutive codes "01" of the intermediate code sequence is biased to the side corresponding to the immediately preceding code "0". This is called "intersymbol interference".

Generally, in the A / D converter 7, the signal level of the sampled reproduced signal is compared with a predetermined threshold value and converted into a corresponding digital value. Therefore, due to the influence of such inter-code interference, an identification error of the intermediate code sequence is likely to occur between two adjacent codes having different code values. For example, even if "... 010 ..." is recorded on the magnetic tape 1, "... 111 ..." may be identified. In order to reduce the intersymbol interference, the partial response equalization circuit 4 performs the reproduction processing by changing the reproduction signal to (1, 0) for each signal detection (sampling) reference point in the A / D converter 7 described later. ,
Waveform equalization processing is performed so as to take a predetermined signal level corresponding to any of the three values of -1). When this waveform equalization processing is sufficiently performed, the signal level of the reproduced signal to be sampled is not affected by the intersymbol interference.

FIG. 11A is a waveform diagram showing an eye pattern of the signal 10 output from the partial response equalization circuit 4. In FIG. 11A, the signal level S5,
The signal level S2 and the signal level S4 are PR4 and
The signal level of the signal 10 that is predetermined corresponding to the three values (1, 0, −1) of In addition, the eye pattern shown in FIG. 11A is an interleaved NRZI eye pattern, and in the continuous signal 10, the interval from the signal detection reference point 30 to the next signal detection reference point 30 is one cycle. It is shown that the signal 10 takes only the waveform in the eye pattern even if two cycles are taken out. The signal detection reference point 30 is an ideal sampling point in the A / D converter 7, and is a point at which the phase margin with respect to the phase error of the sampling clock 12 based on this point is maximized. The signal level S1 and the signal level S3 are A
In the D / D converter 7, three values of PR4 (1, 0, -1)
Is a threshold level of digitization for identifying. The signal level S6 and the signal level S7 are respectively A / D
The minimum level and the maximum level of the input signal allowed as the input of the converter 7 are shown. Signal 1 by the above waveform equalization
At the signal detection reference point 30, the eye pattern of 0 takes three values of the signal level S5, the signal level S2, and the signal level S4.

The PLL circuit 5 extracts the clock signal 11 synchronized with the reproduction signal from the signal 10 output from the partial response equalization circuit 4. The delay adjuster 6 delays the phase of the clock signal 11 (including the case of advancing the phase) and outputs the sampling clock 12. At this time, the delay adjuster 6 controls the signal detection reference point 3 in FIG.
The phase of the clock signal 11 is delayed by a fixed amount so that 0 and the rising edge of the sampling clock 12 (falling edge when sampling is performed at the falling edge timing) match. FIG. 11B is a waveform diagram showing the sampling clock 12 which is the output of the delay adjuster 6. FIG. 11B shows a state in which the signal detection reference point 30 and the rising edge of the sampling clock 12 coincide with each other.

The A / D converter 7 samples the signal 10 which is the output of the partial response equalization circuit 4 for each bit period given at the rising timing of the sampling clock 12 shown in FIG. 6
A signal 13 representing the value of the signal level of the signal 10 at the time of sampling is output with the digital value of the bit. A
From the / D converter 7, the signal level of the signal 10 at the rising edge of the sampling clock 12 is the signal level S1.
If smaller, the signal level S4 in the upper 2 bits
If the signal 13 representing the signal level of the signal 10 at the rising edge of the sampling clock 12 is higher than the signal level S3, the signal 13 representing the signal level S5 in the upper 2 bits is output. The signal level of the signal 10 at the rising edge of the sampling clock 12 is
If the signal level is S1 or more and the signal level S3 or less, the signal 1 representing the signal level S2 in the upper 2 bits.
3 is output.

The Viterbi decoder 8 identifies an intermediate code sequence from the signal 13 output from the A / D converter 7, demodulates and decodes the identified intermediate code sequence, and outputs a decoded value 14. Partial response maximum likelihood decoding (P) by the combination of the partial response equalization circuit 4 and the Viterbi decoder 8
An example of applying RML) to a VTR is Yamamitsu et al .: “Study on high-density recording of home digital VTR”, Technical Report of Television Society, Vol. 12, No. 30, pp. 2
5-30 (Aug, 1988).

However, in the above magnetic reproducing device 20, the signal detection reference point 30 in the delay adjuster 6 is used.
The phase adjustment of the sampling clock 12 with respect to is fixed. Therefore, when the sampling clock 12 has a non-uniform phase variation due to the temperature characteristics of the PLL circuit 5 or the like, the phase adjustment by the delay adjuster 6 cannot be followed and the sampling clock 12 rises (or A deviation of the sampling point given at the fall) from the signal detection reference point 30, that is, a phase error of the sampling clock 12 occurs. In such a case, for example, if the intermediate code sequence is a binary code string, the intermediate code sequence can be easily identified by ± (plus or minus) of the signal level of the signal 10 or both poles, which is not preferable. However, even if the sampling clock 12 has some phase error, it does not have a great adverse effect on the identification of the intermediate code sequence. On the other hand, for example, an interleaved NRZI-like intermediate code sequence consisting of three values (1, 0, -1) takes "0" which is an intermediate value between "1" and "-1". However, the phase error of the sampling clock 12 easily causes deterioration of the code error rate in the identification of the intermediate code sequence.

FIG. 12A is a waveform diagram showing an eye pattern when the amplitude value of the signal 10 is larger than the reference amplitude value. Further, as shown in FIG. 12A, when the amplitude value of the signal 10 exceeds the allowable level of the A / D converter 7 due to a change in the usage environment of the magnetic reproducing apparatus 20, A / Cause malfunction of the D converter 7,
The output value of the A / D converter 7 is not guaranteed. Conversely, signal 1
The same applies when the amplitude value of 0 becomes very small.

FIG. 12B is a waveform diagram showing an eye pattern when a DC offset is generated in the signal 10 which is the input of the A / D converter 7. The DC offset is
It is the deviation of the signal level corresponding to "0" of the intermediate code sequence from the reference level. In FIG. 12B, the reference level is shown as the signal level S2. As shown in FIG. 12B, when a DC offset occurs in the signal 10,
At the signal detection reference point 30, the accurate amplitude value as shown in FIG. 11A cannot be obtained. Therefore, even if the phase of the sampling clock 12 exactly matches the signal detection reference point 30, there is a problem in that the error rate is deteriorated in the identification of the intermediate code sequence.

Among the above problems, as a solution to the problem due to the phase error of the sampling clock, Japanese Patent Laid-Open No. 2-252174 discloses a digital equalizer provided in the latter stage of the A / D converter. Based on the output value of the instrument, by the arithmetic processing circuit and the phase control circuit,
A digital signal detection circuit in which the phase of a sampling clock is controlled is disclosed. In this, the arithmetic processing circuit calculates whether or not the phase of the sampling clock is deviated by calculating the least square error of the output value of the digital equalizer and comparing it with the previous value of the least square error. It detects and outputs the phase control signal PC. The phase control circuit delays the phase of the sampling clock according to the phase control signal PC. Thereby, the phase of the sampling clock is controlled so that the phase margin at the sampling point becomes maximum, that is, the sampling point by the sampling clock becomes the signal detection reference point 30.

[0016]

However, in the digital signal detection circuit disclosed in Japanese Patent Laid-Open No. 2-252174, the arithmetic processing circuit calculates the least square error of the output value of the digital equalizer. There must be. Whether or not the phase of the sampling clock is deviated is first detected by actually shifting the phase of the sampling clock little by little to obtain the least square error and comparing it with the previous value of the least square error. . For this reason,
The calculation amount of the arithmetic processing circuit is large, and the method described in Japanese Patent Application Laid-Open No. 25217/1990 is used.
In 4 ”, it is assumed that one general-purpose signal processor is used, but the configuration of the arithmetic processing circuit remains complicated. Further, since the above-described calculation is performed, it takes time to detect the phase error of the sampling clock, and there is a problem that the responsiveness after the phase of the sampling clock is shifted is not so good.

In view of the above-mentioned problems, the present invention has a simpler configuration and is more responsive to correct the phase error of the sampling clock, the amplitude error of the reproduction signal and the DC offset error, and the data is recorded on the magnetic recording medium. It is an object of the present invention to provide a magnetic reproducing device capable of reproducing digital data with high accuracy.

[0018]

According to a first aspect of the present invention, there is provided a magnetic reproducing apparatus for reproducing the analog signal corresponding to the ternary code string from a recording medium and outputting the reproduced analog signal as a reproduced signal. A clock generation means for generating the sampling clock, an A / D conversion means for sampling the reproduction signal in synchronization with the sampling clock, and converting the reproduction signal into a multilevel digital signal;
The D conversion means detects that a value corresponding to the predetermined value of the maximum continuous number is output, and outputs a maximum number detection signal indicating that, and a predetermined value at either end of the maximum continuous number. Comparing means for comparing the amplitude of the reproduction signal represented by the output of the A / D converting means corresponding to the value with the amplitude reference value and outputting an amplitude comparison signal indicating whether or not the phase of the sampling clock is advanced. And phase control means for controlling the phase of the sampling clock based on the amplitude comparison signal.

According to a second aspect of the present invention, there is provided a magnetic reproducing apparatus according to the first aspect.
In the magnetic reproducing apparatus described in the above, the ternary code string is an intermediate code sequence belonging to the partial response class 4, and the reproducing means corresponds to the ternary value of the intermediate code sequence. In addition, the magnetic reproducing device further includes an equalizing unit that equalizes an amplitude value equal to a predetermined amplitude reference value for each of the three values and outputs an equalized analog signal as a reproduction signal. Decoding means for identifying each code value of the intermediate code sequence from the multi-valued digital signal output from the A / D conversion means, and decoding the information recorded on the recording medium by Viterbi decoding from the identified intermediate code sequence. Equipped with.

A magnetic reproducing apparatus according to a third aspect is the first aspect.
Alternatively, in the magnetic reproducing apparatus according to claim 2, the phase control means smoothes the amplitude comparison signal and generates a phase control signal which is an analog signal, and a phase control signal generation means according to a magnitude of the phase control signal. And a phase delay means for delaying the phase of the sampling clock. The magnetic reproducing apparatus according to claim 4 is the magnetic reproducing apparatus according to any one of claims 1 to 3, wherein the maximum consecutive number of the predetermined value in the ternary code string is 2. The detection means compares the output value of the A / D conversion means with a predetermined threshold value, detects that the A / D conversion means outputs a value corresponding to the predetermined value, and outputs the detection result. A predetermined value detecting means for outputting a predetermined value detecting signal, and the predetermined value detecting signal for the sampling clock 1
A delay unit that delays by the clock and outputs a delay detection signal, and a logical product calculation unit that calculates a logical product of the predetermined value detection signal and the delay detection signal and outputs the calculation result as the maximum number detection signal.

According to a fifth aspect of the present invention, there is provided a magnetic reproducing apparatus according to the first aspect.
5. The magnetic reproducing apparatus according to claim 4, further comprising: an amplitude control signal generation unit that smoothes the amplitude comparison signal and generates an amplitude control signal that is an analog signal, and a preceding stage of the A / D conversion unit. And an amplitude adjusting means for adjusting the amplitude of the reproduction signal according to the magnitude of the amplitude control signal, and the clock generating means generates a sampling clock from the reproduction signal whose amplitude is adjusted by the amplitude adjusting means. The A / D conversion means generates and samples the reproduction signal whose amplitude is adjusted by the amplitude adjustment means.

According to a sixth aspect of the present invention, there is provided a magnetic reproducing apparatus according to the fifth aspect.
In the magnetic reproducing apparatus described above, the amplitude adjustment of the reproduction signal by the amplitude adjusting means has a faster response to an error than the phase correction of the sampling clock by the phase controlling means. The magnetic reproducing apparatus according to claim 7 is the magnetic reproducing apparatus according to any one of claims 1 to 4, further comprising: an output value of the A / D conversion means and the code value represented by the output value. DC offset detection means for comparing with a corresponding predetermined reference value to detect whether or not the DC level of the reproduction signal is higher than a predetermined DC level reference value, and outputting a DC offset detection signal indicating the detection result. And a direct current level adjusting means for adjusting the direct current level of the reproduction signal on the basis of a direct current offset detection signal, the clock generating means for direct current level adjustment by the direct current level adjusting means. Generate a sampling clock from the level adjusted playback signal,
The A / D converting means samples the reproduction signal whose DC level is adjusted by the DC level adjusting means.

The magnetic reproducing apparatus according to claim 8 is the magnetic reproducing apparatus according to claim 7.
In the magnetic reproducing apparatus described above, the DC level adjustment of the reproduction signal by the DC level adjusting means has a faster response to an error than the phase correction of the sampling clock by the phase controlling means. The magnetic reproducing apparatus according to claim 9 is the magnetic reproducing apparatus according to claim 5 or 6, further comprising a predetermined value corresponding to the output value of the A / D conversion means and the code value represented by the output value. DC offset detecting means for detecting whether or not the DC level of the reproduction signal is larger than a predetermined DC level reference value by comparing with a reference value, and outputting a DC offset detection signal indicating the detection result; and the amplitude adjustment. Means for adjusting the direct current level of the reproduction signal on the basis of a direct current offset detection signal, and the amplitude adjusting means reproduces the direct current level adjusted by the direct current level adjusting means. Adjust the signal amplitude.

A magnetic reproducing apparatus according to a tenth aspect is the magnetic reproducing apparatus according to the ninth aspect, wherein the direct current level adjustment of the reproduction signal by the direct current level adjusting means and the amplitude adjustment of the reproduction signal by the amplitude adjusting means are performed. , The phase correction of the sampling clock by the phase control means,
The response to the error is quick in this order. The magnetic reproducing device according to claim 11 is the magnetic reproducing device according to any one of claims 7 to 10, wherein the DC offset detecting means is an output value of the A / D converting means and a predetermined threshold value. And a DC level detecting means for detecting that the output value of the A / D converting means represents the code value associated with the DC level of the reproduction signal, and the detected code value. Is compared with the output value of the A / D conversion means at the time when the code value is detected, and whether or not the DC level of the reproduction signal is larger than the reference value of the code value associated therewith. And a DC offset detection signal generating means for generating the DC offset detection signal, wherein the DC level adjusting means smoothes the DC offset detection signal and is an analog signal. Comprises an offset control signal generating means for generating a offset control signal, said DC level adjusting means, depending on the magnitude of the offset control signal, adjusts the DC level of the reproduced signal.

[0025]

In the magnetic reproducing apparatus according to the present invention, the reproducing means reproduces the analog signal corresponding to the ternary code string from the recording medium and outputs it as a reproduced signal. The clock generation means generates the sampling clock from the reproduction signal. The A / D conversion means samples the reproduction signal in synchronization with the sampling clock and converts the reproduction signal into a multilevel digital signal. The maximum number detecting means detects that the A / D converting means outputs a value corresponding to a predetermined value of the maximum continuous number, and outputs a maximum number detecting signal indicating the value. The comparing means compares the amplitude of the reproduction signal represented by the output of the A / D converting means corresponding to one of the predetermined values at either end of the maximum continuous number with the amplitude reference value, and the phase of the sampling clock is An amplitude comparison signal indicating whether the vehicle is advancing is output. The phase control means is
The phase of the sampling clock is controlled based on the amplitude comparison signal.

Therefore, according to the present invention as set forth in claim 1,
By making good use of the regularity of the analog signal reproduced from the recording medium, the phase shift of the sampling clock can be easily performed only by comparing the output value of the A / D conversion means and the corresponding amplitude reference value. Can be detected. As a result, the phase control means can correct the phase error of the sampling clock with good responsiveness without performing complicated calculations and with a simple configuration. Also,
Since the phase error is detected for each maximum continuous section of the predetermined value included in the ternary code string, the phase error can always be detected and corrected without any temporal bias in a certain time range. it can.

According to a second aspect of the present invention, there is provided the magnetic reproducing apparatus according to the first aspect, wherein the ternary code string is an intermediate code sequence belonging to the partial response class 4, and is stored in the reproducing means. The equalizing means equalizes the reproduced analog signal so as to have an amplitude value equal to a predetermined amplitude reference value for each of the three values of the intermediate code sequence, and is equalized. An analog signal is output as a reproduction signal. Further, the decoding means in the magnetic reproducing device identifies each code value of the intermediate code sequence from the multi-valued digital signal output from the A / D conversion means, and records by Viterbi decoding from the identified intermediate code sequence. Decode the information recorded on the medium.

Therefore, according to the present invention as set forth in claim 2,
A magnetic reproducing apparatus that performs partial response maximum likelihood decoding using an intermediate code sequence belonging to PR4 also claims 1.
It is possible to obtain the same effect as that of the magnetic reproducing apparatus described, and it is possible to prevent deterioration of the code error rate in the decoding means with good responsiveness. In the magnetic reproducing apparatus according to claim 3, in the phase controlling means in the magnetic reproducing apparatus according to claim 1 or 2, the phase control signal generating means smoothes the amplitude comparison signal to obtain a phase which is an analog signal. Generate a control signal. The phase delay means delays the phase of the sampling clock according to the magnitude of the phase control signal.

Therefore, according to the present invention of claim 3,
In addition to the above effect, the phase control means delays the phase of the sampling clock according to the magnitude of the phase control signal, which is obtained by smoothing the amplitude comparison signal which is a binary signal. Can be smoothly corrected, and the phase error can be corrected with good responsiveness to the detection of the phase error.

According to a fourth aspect of the magnetic reproducing apparatus of the present invention, in the magnetic reproducing apparatus according to any of the first to third aspects, the maximum number of consecutive predetermined values in the ternary code string is two. In the maximum number detecting means, the predetermined value detecting means compares the output value of the A / D converting means with a predetermined threshold value and outputs a value corresponding to the predetermined value from the A / D converting means. It is detected that the predetermined value has been detected, and a predetermined value detection signal indicating the detection result is output. The delay means delays the predetermined value detection signal by one clock of the sampling clock and outputs the delay detection signal. The logical product operation means is
The logical product of the predetermined value detection signal and the delay detection signal is calculated, and the calculation result is output as the maximum number detection signal.

Therefore, according to the present invention as set forth in claim 4,
In addition to the above effects, comparison means for comparing the output value of the A / D converting means and the amplitude reference value with each other and detection of a predetermined value for comparing the output value of the A / D converting means with a predetermined threshold value The phase error of the sampling clock can be easily detected with a simple configuration that is a combination of the means, the delay means, and the AND operation means.

According to a fifth aspect of the present invention, there is provided the magnetic reproducing apparatus according to any one of the first to fourth aspects, wherein the amplitude control signal generating means smoothes the amplitude comparison signal to obtain an analog signal. To generate an amplitude control signal. The amplitude adjusting means is provided in the preceding stage of the A / D converting means, and adjusts the amplitude of the reproduction signal according to the magnitude of the amplitude control signal. The clock generation unit generates a sampling clock from the reproduction signal whose amplitude is adjusted by the amplitude adjustment unit, and the A / D conversion unit samples the reproduction signal whose amplitude is adjusted by the amplitude adjustment unit.

Therefore, according to the present invention of claim 5,
Taking advantage of the fact that the amplitude comparison signal indicating the detection result of the phase error simultaneously indicates the detection result of the amplitude error of the reproduction signal, the same amplitude comparison signal is used to correct the phase error of the sampling clock. It is possible to simultaneously correct the amplitude error of the reproduction signal. Therefore, according to the present invention, in addition to the effect of the present invention according to any one of claims 1 to 4, even when a phase error of the sampling clock and an amplitude error of the reproduced signal occur, Without separately providing a means for detecting the amplitude error,
Both can be corrected with good responsiveness with a simple configuration, and deterioration of the code error rate in the magnetic reproducing apparatus can be prevented more accurately.

According to a sixth aspect of the magnetic reproducing apparatus of the present invention, in the magnetic reproducing apparatus of the fifth aspect, the amplitude adjustment of the reproduction signal by the amplitude adjusting means is more than the phase correction of the sampling clock by the phase control means. Fast response to error. Therefore, according to the present invention of claim 6, in addition to the above effects, the amplitude adjusting means adversely affects the phase correction by the phase controlling means, and the A / D
It is possible to reduce the amplitude error of the reproduction signal, which reduces the reliability of the output value of the conversion means, more quickly than the phase correction by the phase control means. Therefore,
The phase control unit can correct the phase error of the sampling clock more accurately, and can more accurately prevent the deterioration of the code error rate in the magnetic reproducing apparatus.

According to a seventh aspect of the present invention, there is provided the magnetic reproducing apparatus according to any one of the first to fourth aspects, wherein the DC offset detecting means is the A / D.
An output value of the converting means and a predetermined reference value corresponding to the code value represented by the output value are compared to detect whether or not the DC level of the reproduction signal is higher than a predetermined DC level reference value, A DC offset detection signal indicating the detection result is output. The DC level adjusting means is provided in the preceding stage of the A / D converting means, and adjusts the DC level of the reproduction signal based on the DC offset detection signal. The clock generation means generates a sampling clock from the reproduction signal whose DC level is adjusted by the DC level adjustment means, and the A / D conversion means samples the reproduction signal whose DC level is adjusted by the DC level adjustment means. .

Therefore, according to the present invention of claim 7,
In addition to the effect according to the present invention as set forth in any one of claims 1 to 4, by comparing the reference value corresponding to each code value with the output value of the A / D conversion means, the DC offset error can be easily corrected. Can be detected. As a result, the DC level adjusting means can adjust the DC level of the reproduction signal with a simple configuration and good responsiveness to the offset error of the DC level of the reproduction signal. As a result, the magnetic reproducing apparatus more accurately degrades the code error rate even when a phase error of the sampling clock or a DC level offset error of the reproduced signal occurs due to a change in the usage environment of the magnetic reproducing apparatus. Can be prevented.

In the magnetic reproducing apparatus according to claim 8, in the magnetic reproducing apparatus according to claim 7, the DC level adjustment of the reproduction signal by the DC level adjusting means is performed by the phase correction of the sampling clock by the phase control means. However, the response to the error is fast. Therefore, according to the present invention of claim 8, in addition to the above effects, the direct current level adjusting means causes the direct current offset error, which has a large adverse effect on the phase error correction of the sampling clock by the phase controlling means, to the phase by the phase controlling means. It can be reduced more quickly than the correction is performed. Therefore, the phase control means can correct the phase error of the sampling clock more accurately, and can more accurately prevent the deterioration of the code error rate in the magnetic reproducing apparatus.

According to a ninth aspect of the present invention, there is provided the magnetic reproducing apparatus according to the fifth or sixth aspect, wherein the DC offset detecting means has the output value of the A / D converting means and the output value thereof. By comparing with a predetermined reference value corresponding to the code value, it is detected whether or not the DC level of the reproduction signal is higher than a predetermined DC level reference value, and a DC offset detection signal indicating the detection result is output. . The DC level adjusting means is provided in the preceding stage of the amplitude adjusting means,
The DC level of the reproduction signal is adjusted based on the DC offset detection signal. The amplitude adjusting means adjusts the amplitude of the reproduction signal whose direct current level is adjusted by the direct current level adjusting means.

Therefore, according to the present invention of claim 9,
In addition to the effect of the present invention according to claim 5 or claim 6, the error of the DC offset can be easily detected by comparing the reference value corresponding to each code value with the output value of the A / D conversion means. be able to. As a result, the DC level adjusting means can adjust the DC level of the reproduction signal with a simple configuration and good responsiveness to the offset error of the DC level of the reproduction signal. As a result, the magnetic reproducing device
Even when the phase error of the sampling clock, the amplitude error of the reproduction signal, and the DC level offset error occur due to changes in the usage environment of the magnetic reproducing apparatus, the deterioration of the code error rate can be prevented more accurately. .

According to a tenth aspect of the present invention, there is provided a magnetic reproducing apparatus according to the ninth aspect, wherein the direct current level adjusting means adjusts the direct current level of the reproduction signal and the amplitude adjusting means adjusts the reproduction signal amplitude. The phase correction of the sampling clock by the phase control means has a quick response to an error in this order. Therefore, according to the present invention of claim 10, in addition to the above effects, the DC level adjusting means adversely affects the amplitude adjustment of the reproduction signal by the amplitude adjusting means and the phase correction of the sampling clock by the phase controlling means. The resulting DC offset error of the reproduction signal can be reduced more quickly than the amplitude adjustment and the phase correction. Therefore, the amplitude adjusting means can correct the amplitude error of the reproduction signal with higher accuracy, and the phase controlling means can correct the phase error of the sampling clock with higher accuracy by this amplitude adjustment. As a result, the magnetic reproducing apparatus causes deterioration of the code error rate even when a phase error of the sampling clock, an amplitude error of the reproduction signal, and a DC level offset error occur due to changes in the usage environment of the magnetic reproducing apparatus. It can be prevented more accurately.

In the magnetic reproducing apparatus according to claim 11, in the magnetic reproducing apparatus according to any one of claims 7 to 10, in the DC offset detecting means, the DC level detecting means is the A / D converter. The output value of the means is compared with a predetermined threshold value, and it is detected that the output value of the A / D conversion means represents the code value associated with the DC level of the reproduction signal. The DC offset detection signal generation means compares the reference value corresponding to the detected code value with the output value of the A / D conversion means at the time when the code value is detected, and the DC level of the reproduction signal is The DC offset detection signal indicating whether or not the associated code value is larger than the reference value is generated. In the DC level adjusting means, the offset control signal generating means smoothes the DC offset detection signal and generates an offset control signal which is an analog signal. The DC level adjusting means adjusts the DC level of the reproduction signal according to the magnitude of the offset control signal.

Therefore, according to the present invention as defined in claim 11, assuming that there is no phase error of the sampling clock, the timing at which only the DC level offset error can be detected is set as the output value of the A / D conversion means. It can be detected by a simple method of comparison with a threshold value, that is, by a simple structure of a DC level detecting means. Also A at that time
The DC offset error can be easily detected by comparing the output value of the / D converting means with the reference value corresponding to the detected code value. Further, the DC level of the reproduction signal can be adjusted according to the magnitude of the offset control signal, which is obtained by smoothing the binary DC offset detection signal. Therefore, according to the present invention, the effect according to the present invention according to any one of claims 7 to 10 can be obtained efficiently and with good response by such a simple configuration.

[0043]

【Example】

(Embodiment 1) FIG. 1 is a block diagram showing the configuration of a magnetic reproducing apparatus 100 according to the first embodiment of the present invention. Since the same components as those of the magnetic reproducing device 20 shown in FIG. 10 have already been described, the same reference numerals are given,
Description is omitted.

The magnetic reproducing apparatus 100 includes a magnetic tape 1, a reproducing head 2, a reproducing amplifier 3, a partial response equalizing circuit 4, a PLL circuit 5, an A / D converter 7, a Viterbi decoder 8, a comparator 101 and a delay device. 102, AND circuit 103,
Amplitude comparator 104, comparator 105, delay device 106, AN
A D circuit 107, an amplitude comparator 108, an OR circuit 109, an integrating circuit 110, and a phase control circuit 111 are provided.

The comparator 101 compares the signal level represented by the signal 13 output from the A / D converter 7 with the signal level S3, and outputs a signal 120 representing the comparison result. FIG.
FIG. 3A is a block diagram showing the configuration of the comparator 101. As shown in FIG. 2A, the comparator 101 has A /
The signal 13 output from the D converter 7 is input to the input terminal X, and the signal level S3 is input to the input terminal Y. Comparator 101
Compares the input X and the input Y and outputs "1" as the signal 120 when X> Y is satisfied, and "0" otherwise. That is, the output of "1" as the signal 120 indicates that the A / D converter 7 has output the digital value corresponding to "1" of the intermediate code sequence.

There are various methods for the comparator 101 to compare the input X and the input Y and determine whether X> Y holds. As one of them, when the A / D converter 7 converts the signal 10 into a 6-bit digital signal, for example, the comparator 101 corresponds to 6 bits representing the signal level S3, and the upper predetermined bits of the signal 13 Just check X
It may be determined whether or not> Y. In particular,
When the signal level S3 is 6 bits, the comparator 101 outputs “101
111 ”, the upper 2 of the signal 13
Check the bit and if the upper 2 bits are “11”,
“1” may be output as the signal 120. Further, as another example, the comparator 101 outputs the signal 13 to the signal 1
The voltage value X of the signal level represented by 6 bits of 3 or the voltage value X of the signal 10 at the time of sampling and the voltage value Y of the signal level S3 are compared, and X> Y
When the above holds, “1” may be output as the signal 120. The same applies to the comparator 105 described below. Also, the amplitude comparator 10
4 and the amplitude comparator 108, when examining only the upper predetermined bits of the signal 13, at least the upper 3 bits of the signal 13 must be examined.
Similar to 1, the amplitude of the signal 13 can be compared.

The delay unit 102 delays the signal 120 by one clock of the sampling clock 130 and outputs a delayed signal 121. The AND circuit 103 includes a comparator 10
The logical product of the signal 120 which is the output of 1 and the delayed signal 121 which is the output of the delay device 102 is obtained, and the signal 122 is output. That is, by outputting “1” as the signal 122, the A / D converter 7 outputs “1” of the intermediate code sequence.
It is shown that the digital value corresponding to "1" has been output.

The amplitude comparator 104 outputs an A / A signal only when the signal 122 output from the AND circuit 103 is "1".
The signal level represented by the signal 13 which is the output of the D converter 7 is compared with the signal level S5 shown in FIG. 11A, and the signal level represented by the signal 13 is the signal level S5.
If it is larger than that, “1” is output as the signal 123. In other cases, that is, when the signal 122 is "1" and the signal level represented by the signal 13 is equal to or lower than the signal level S5, and when the signal 122 is "0", "0". Is output as the signal 123. That is, the fact that the signal 123 is “1” indicates that the phase of the sampling clock 130 is advanced with respect to the signal detection reference point 30. Nothing is shown that the signal 123 is “0”, or the sampling clock 13
It indicates that the phase of 0 is (correct or) delayed.

In the amplitude comparator 104, the signal level represented by the signal 13 is compared with the signal level S5 by the same configuration as the comparator 101, and the signal level represented by the signal 13 is the signal level S5. Can be determined to be greater than or equal to. For example, the signal level S5 is 6
If the upper 3 bits of the signal 13 are "111" when the bit is defined as "110111", it can be determined that the signal level represented by the signal 13 is higher than the signal level S5. Further, the amplitude comparator 104 may check only the upper third bit.

The comparator 105 compares the signal level of the signal 13 output from the A / D converter 7 with the signal level S1 and outputs a signal 124 representing the comparison result. FIG. 2 (b)
FIG. 3 is a block diagram showing a configuration of a comparator 105. FIG.
As shown in (b), the comparator 105 has a signal level S
1 is input to the input terminal X, and the signal level represented by the signal 13 is input to the input terminal Y. Therefore, the comparator 105 compares the input X and the input Y, and when X> Y is satisfied, “1” is set,
In other cases, “0” is output as the signal 124.
That is, the output of "1" as the signal 124 indicates that the digital value corresponding to "-1" of the intermediate code sequence is output from the A / D converter 7.

In the comparator 105 as well, the comparator 1
Similar to 01, the input X and the input Y can be compared to determine whether or not X> Y holds. However, when only the upper predetermined bits of the signal 13 are examined, for example, the signal level S1
Is 6 bits and is defined as “010000”, and if the upper 2 bits of the signal 13 are “00”, X>
It can be determined that Y holds.

The delay unit 106 delays the signal 124 by one clock of the sampling clock 130 and outputs a delayed signal 125. The AND circuit 107 includes a comparator 10
5 is output and the signal 125 output from the delay circuit 110 is logically ANDed and output as a signal 126. That is, by outputting “1” as the signal 126, the A / D converter 7 outputs “−” of the intermediate code sequence.
It is shown that the digital value corresponding to "1-1" has been output.

The amplitude comparator 108 outputs the A / A signal only when the signal 126 output from the AND circuit 107 is "1".
A signal level represented by the signal 13 which is the output of the D converter 7,
The signal level S4 shown in FIG. 11A is compared, and if the signal level S4 or less, “1” is output as the signal 127. Further, the amplitude comparator 108 outputs “0” when the signal 126 is “1” and the signal level represented by the signal 13 is higher than the signal level S4 and when the signal 126 is “0”. The signal 127 is output. That is, when the signal 127 is “1”, it indicates that the phase of the sampling clock 130 is (correct or) advanced with respect to the signal detection reference point 30, and when the signal 127 is “0”, nothing is indicated. Or the phase of the sampling clock 130 is delayed.

Also in the amplitude comparator 108, the signal level S4 is compared with the signal level represented by the signal 13 by the same configuration as the comparator 101, and the signal level S
It is possible to determine whether or not 4 is larger than the signal level represented by the signal 13. For example, when the signal level S4 is 6 bits and is defined as "001000", the signal 1
If the upper 3 bits of 3 are "000", the signal level S
It can be determined that 4 is larger than the signal level represented by the signal 13. Further, also in the amplitude comparator 108, similarly to the amplitude comparator 104, by checking only the upper third bit of the signal 13, the signal level S4 becomes
It is possible to determine whether or not the signal level is higher than the signal level represented by 3.

The OR circuit 109 has a signal 123 and a signal 12
The logical sum of 7 and 7 is obtained and a signal 128 is output. Signal 12
3 or signal 127 becomes "1",
That is, when the phase of the sampling clock 130 is advanced, “1” is output as the signal 128, and “0” is output in other cases. The integrating circuit 110 outputs a phase control signal 129 obtained by smoothing the signal 128. FIG. 5 is a block diagram showing the configuration of the integrating circuit 110. As shown in FIG. 5, the integrating circuit 110 includes a resistor 45 and a capacitor 4
6 is a first-order integrator circuit. 6A is a waveform diagram showing the signal 128 which is the input of the integrating circuit 110, and FIG. 6B is the signal 1 which is the output of the integrating circuit 110.
FIG. 29 is a waveform diagram showing 29. As shown in FIG. 6B, the integration circuit 110 converts the binary digital signal into a smoothed analog signal and outputs it as a phase control signal 129.

The phase control circuit 111 generates the clock signal 1 according to the voltage value of the phase control signal 129 which exceeds a predetermined voltage value.
The phase control signal 12 that delays the phase of 1 and is equal to or less than a predetermined voltage value.
Advance the phase of the clock signal 11 according to the voltage value of 9,
For example, delay line or voltage controlled oscillator (VC
O) and the like. Hereinafter, a signal flow in the magnetic reproducing apparatus 100 of FIG. 1 will be described.

The data recorded on the magnetic tape 1 is
It is reproduced as a reproduction signal by the reproduction head 2 and input to the partial response equalization circuit 4 via the reproduction amplifier 3. The reproduction signal input to the partial response equalization circuit 4 is waveform equalized so that the signal waveform takes a signal level corresponding to any of (1, 0, -1) of the intermediate code sequence for each bit period. It As a result, the eye pattern of the signal 10 has the waveform shown in FIG.

Next, the signal 10 which is the output of the partial response equalization circuit 4 is input to the PLL circuit 5, and the clock signal 11 synchronized with the reproduction signal is extracted. The clock signal 11 extracted by the PLL circuit 5 is input to the phase control circuit 111, and according to the voltage value of the phase control signal 129 so that sampling is performed at the signal detection reference point 30 shown in FIG. Be delayed. As a result, the sampling clock 130 shown in FIG. 11B is output.

At the same time, the partial response equalization circuit 4
The signal 10 which is the output of is input to the A / D converter 7,
In the / D converter 7, sampling is performed at the timing of the sampling clock 130. The signal level of the sampled signal 10 is converted into a signal 13 which is, for example, a 6-bit digital signal. The main threshold level of A / D conversion in the A / D converter 7 is shown in FIG.
Identical to that shown in (a), but with a more intermediate threshold level. Signal 1 output from A / D converter 7
3 is input to the Viterbi decoder 17. Viterbi decoder 1
In FIG. 7, the intermediate code sequence represented by the ternary value of (1, 0, −1) is identified from the signal 13 and the identified intermediate code sequence is binarized, demodulated and decoded to obtain a decoded value 14. Is output. At the same time, the signal 13 which is the output of the A / D converter 7 is input to the comparator 101, the amplitude comparator 104, the comparator 105 and the amplitude comparator 108, and the phase control process described later is performed.

In the following, the sampling clock 1 will be used by utilizing the regular nature of the waveform change of the signal 10 belonging to PR4.
The principle of detecting the phase error of 30 will be described with reference to FIGS. 3 and 4. In the magnetic reproducing apparatus 100 of the present embodiment, the phase error of the sampling clock 130 is detected based on the signal 13 representing a 6-bit digital value, for example. However, the signal 10 and the signal 13 are phases that indicate whether the signal level at each sampling point is an analog signal representing an intermediate code sequence, or whether the signal level at each sampling point is represented by a 6-bit digital value. Only the difference indicates that the signals have substantially the same contents, and the signal 13 is set to the time between sampling points,
Since the drawing becomes complicated when it is illustrated with a waveform on a staircase having a signal level represented by the signal 13, an analog signal of the signal 10 will be described below.

FIG. 3 is a waveform diagram showing a part of the waveform of the signal 10 in which two consecutive signal levels S5 are obtained at each signal detection reference point 30. As shown in FIG. 3, signal 1
0 indicates that the signal level S5 is 2 at the signal detection reference point 30.
At the next succeeding signal detection reference point 30, either the signal level S2 as the waveform 41 or the signal level S4 as the waveform 42 is obtained.

The reason for this is that every other adjacent "1" in the original data is an interleaved NRZI of the reproduction system.
In the above, the sign of "1" on one side is inverted with respect to "1" on the other side. That is, the interleaved NRZI of the reproduction system obtained for "111" in the original data is "11-1", "-1-11",
There is only one of "1-1-1" and "-111", and "111" does not appear in the signal 10 which is the interleaved NRZI of the reproduction system. That is, FIG.
Assuming that the signal level S5 in 1 (a) is "1", the signal level S2 is "0", and the signal level S4 is "-1", three or more consecutive signals "10" at the signal detection reference point 30 are shown. It does not take a signal level corresponding to "1". Similarly, the signal 10 does not take the signal level corresponding to “−1” continuously at three or more at the signal detection reference point 30. That is, in the signal 10, the signal detection reference point 30 has two consecutive signal levels S4, and
The signal level becomes either the signal level S2 or the signal level S5.

Further, the signal 10 is the signal detection reference point 30.
, The signal level is any one of the signal level S5, the signal level S2, and the signal level S4. Therefore, at the time between the signal detection reference point 30 and the next signal detection reference point 30, the signal level between Takes a value. That is, until the next signal detection reference point 30 after two signal levels S5 continue at each signal detection reference point 30, the signal 10 is not detected.
Signal level becomes lower than the signal level S5. Further, the signal level of the signal 10 becomes higher than the signal level S4 until the next signal detection reference point 30 after two signal levels S4 continue.

On the other hand, as a characteristic of the analog waveform, the signal level of the signal 10 between the two consecutive signal levels S5 is larger than the signal level S5, and the signal 10 between the two consecutive signal levels S4. Signal level is lower than the signal level S4. FIG. 4 shows sampling points 8 by the sampling clock 130 having a phase error.
It is a waveform diagram which shows the waveform of the signal 10 which has a relative phase error with respect to 0, 81, and 82. In FIG. 4A, the waveform 43 shows the waveform 41 of FIG. 3 when the phase of the sampling clock is delayed with respect to the signal detection reference point 30, and the waveform 44 is sampled with respect to the signal detection reference point 30. Figure 3 when the clock phase is advanced
The waveform 42 is shown. FIG. 4B shows a signal detection reference point 30.
Sampling clock 130 having a phase error with respect to
FIG.

As shown by the waveform 43 in FIG. 4A, when the phase of the sampling clock 130 is delayed with respect to the signal detection reference point 30, the second continuous signal level S is obtained.
At the sampling point 81, which corresponds to the signal detection reference point 30 where 5 should be sampled, the signal level of the waveform 43 becomes lower than the signal level S5. FIG.
As shown in the waveform 44 of (a), when the phase of the sampling clock 130 is ahead of the signal detection reference point 30, the signal detection reference point 30 at which the second consecutive signal level S5 should be sampled. At the sampling point 81 corresponding to, the signal level of the waveform 44 becomes higher than the signal level S5. Although not shown, when two signal levels S4 are continuous at each signal detection reference point 30, similarly, when the phase of the sampling clock 130 is delayed with respect to the signal detection reference point 30, the second consecutive signal level S4 is delayed. At the sampling point 81, which corresponds to the signal detection reference point 30 at which the signal level S4 is to be sampled, the signal level of the signal 10 becomes higher than the signal level S4.

When the phase of the sampling clock 130 is advanced with respect to the signal detection reference point 30, the sampling point 81 corresponding to the signal detection reference point 30 at which the second continuous signal level S4 is to be sampled. In, the signal level of the signal 10 becomes lower than the signal level S4. Using the characteristics of the signal 10 as described above, a discriminator for discriminating the signal level S3 as the threshold level for the signal 10 and determining the signal level S5 when the signal level of the signal 10 is higher than the signal level S3 is provided. If provided, the waveform 43 will have sampling points 80 and 81.
Then, it is determined that the signal level is S5. However, the signal level of the waveform 43 at the sampling point 81 is smaller than the signal level S5. Therefore, it can be seen that the phase of the sampling clock 130 is delayed with respect to the signal detection reference point 30.

Similarly, the waveform 44 shows the sampling point 8
It is determined that the signal level is S5 at 0 and the sampling point 81, but the waveform 44 at the sampling point 81 is
Is higher than the signal level S5. Therefore, it can be seen that the phase of the sampling clock 130 leads the signal detection reference point 30. Similarly to the above, with respect to the signal 10, the signal level S1 shown in FIG. 11A is used as a threshold level, and when the signal level of the signal 10 is smaller than the signal level S1, a determiner for determining the signal level S4 is used. If provided, the sampling point 81 is applied to the signal 10 determined to be the signal level S4 at the sampling point 80 and the sampling point 81 by the determiner.
It is possible to detect whether the phase of the sampling clock 130 is delayed or advanced with respect to the signal detection reference point 30 by comparing the signal level of the signal 10 in FIG.

That is, the sampling point 8
When the signal level of the signal 10 at the sampling point 81 is higher than the signal level S4 with respect to the signal 10 determined to be 0 and the signal level S4 at the sampling point 81, the phase of the sampling clock 130 is delayed and the signal at the sampling point 81 is delayed. When the signal level of 10 is lower than the signal level S4, it is possible to detect that the phase of the sampling clock 130 is advanced.

In the following, based on the above properties of the signal 10,
A method of detecting the phase error of the sampling clock 130 from the signal value of the signal 13 in the magnetic reproducing device 100 will be described. As shown in FIG. 1, the signal 13 output from the A / D converter 7 is output to the comparator 101 and the comparator 10.
5 is input. The comparator 101 is the one shown in FIG. 2A, and the signal 13 is input to the input terminal X and the signal level S3 is input to the input terminal Y. The comparator 101 compares the input X and the input Y, and when X> Y is satisfied, “1” is set,
In other cases, “0” is output as the signal 120. When the signal 120 becomes “1”, the signal 1 at that time
It is shown that 3 is the signal level corresponding to "1" of the intermediate code sequence.

The signal 120 output from the comparator 101 is
It is output to the AND circuit 103 and the delay device 102. The delay device 102 delays the input signal 120 by one clock of the sampling clock 130 and outputs a delayed signal 121. The AND circuit 103 is a comparator 101.
Of the output of the signal 120 and the output of the delay device 102 from the delayed signal 121 are ANDed and output as a signal 122. Thus, when the signal 122 output from the AND circuit 103 becomes “1”, the A / D converter 7 outputs the signal 13 corresponding to the second “1” of the intermediate code sequence “11”. It is shown that it is being output.

Next, the amplitude comparator 104 receives the signal 122 output from the AND circuit 103 and the signal 13 output from the A / D converter 7. Amplitude comparator 104
Indicates that the signal 122 output from the AND circuit 103 is “1”.
The signal level represented by the signal 13 is compared with the signal level S5 only in the case where the signal level S5 is higher than the signal level S5. In the case of “0”, the signal 123
Output as

Similarly, the comparator 105 compares the signal level of the signal 13 with the signal level S1. When (signal level S1)> (signal level of the signal 13) is satisfied, "1" is set, and other signals are set. In that case, “0” is output as the signal 124. The signal 124 being “1” indicates that the signal 13 at that time has a signal level corresponding to “−1” of the intermediate code sequence.

The signal 124 output from the comparator 105 is
It is output to the AND circuit 107 and the delay device 106. The delay device 106 delays the input signal 124 by one clock and outputs a delayed signal 125. AND circuit 10
7 obtains the logical product of the signal 124 which is the output of the comparator 105 and the signal 125 which is the output of the delay circuit 110, and outputs it as a signal 126. Since the signal 126 output from the AND circuit 107 becomes "1", A /
It is shown that the D converter 7 outputs the signal 13 corresponding to the second "-1" of the intermediate code sequence "-1-1".

Next, the amplitude comparator 108 receives the signal 126 output from the AND circuit 107 and the signal 13 output from the A / D converter 7. Amplitude comparator 108
Indicates that the signal 126 output from the AND circuit 107 is "1".
Only in the case of, the signal level represented by the signal 13 at that time is compared with the signal level S4, and when the signal level represented by the signal 13 is larger than the signal level S4, “0” is set. When it is S4 or less, “1” is output as the signal 127.

Now, the signal 123 and the signal 127 are input to the OR circuit 109, and the OR circuit 109 outputs the signal 123.
And a signal 127 are calculated, and a signal 128 indicating the calculation result is output. Further, the signal 128 is the integration circuit 1
10 is input. The integrating circuit 110 is a primary integrating circuit including a resistor 45 and a capacitor 46 as shown in FIG. The input signal 12 of the integrating circuit 110 is shown in FIG.
8 shows the signal waveform, and FIG. 6B shows the signal waveform of the phase control signal 129 output from the integrating circuit 110. As shown in FIG. 6, the integration circuit 110 converts the binary digital signal into an analog signal and outputs it as the phase control signal 129, and the phase control circuit 111 outputs the clock signal according to the voltage value of the phase control signal 129. 11 delay time is controlled.
Here, the phase control circuit 111 delays the clock signal 11 when the voltage value of the phase control signal 129 exceeds a predetermined value and becomes larger, and when the voltage value of the phase control signal 129 becomes smaller than the predetermined value. Advances the phase of the clock signal 11.

With the above structure, in the magnetic reproducing apparatus 100 of the present embodiment, the signal level represented by the signal 13 is compared with the predetermined threshold level based on the regular property of the signal 10 after waveform equalization. The phase error of the clock signal 11 is corrected based on the detection result based on the detection result. Therefore, the sampling clock 130 has a simpler configuration and higher responsiveness than the case where the phase error is corrected based on the calculation. It is possible to correct the phase error of. Therefore, even when the data transfer rate from the reproducing head 2 to the Viterbi decoder 8 is further increased, the phase error of the sampling clock 130 can be corrected with good response, and the deterioration of the code error rate can be prevented ( The Viterbi decoder 8 can accurately identify the intermediate code sequence). Further, since the phase error is detected and corrected for each "11" or "-1-1" included in the intermediate code sequence, the phase error is always detected without any temporal bias in a certain time range. Can be corrected.

In the phase error detection in this embodiment, the judgment results of the comparator 101 and the comparator 105 are as follows.
The phase difference is detected by comparing the signal levels of the signal 13 at that time both in the case where the two signal levels S5 shown in FIG. 11A continue and in the case where the two signal levels S4 continue two. Is not limited to this, and detects only when two signal levels of either one continue,
The phase error of the sampling clock 130 can also be detected by comparing the signal level with the value of the signal 13 at that time. As described above, in the case of the signal level S4, even if the phase error is detected only when two signal levels S4 are consecutive, the response may be slightly inferior to the case where the phase error is detected for both of them. Compared with the case where the phase error is calculated based on the calculated value of, the phase error of the sampling clock 130 can be corrected with sufficient responsiveness.

Further, in the phase error detection in this embodiment, the signal level S shown in FIG. 11A in the signal 13 is determined as the determination result of the comparator 101 or the comparator 105.
5 or two consecutive signal levels S4, the actual signal 1 corresponding to the latter signal level of the two consecutive signal levels
Signal level 3 and signal level S5 or signal level S
4 was compared, the phase error was detected, and the phase error was corrected. However, the present invention is not limited to this,
The phase error may be detected and the phase error may be corrected with respect to the previous signal level of the two continuous signal levels or both of the continuous two signal levels.

For example, as the judgment result of the comparator 101,
The previous signal level S of the two consecutive signal levels S5
5, when the phase error of the sampling clock 130 is detected, the A / D converter 7 and the amplitude comparator 104
A holding circuit such as a latch for holding the digital value of the signal 13 by using "1" of the signal 120 as a latch enable is provided between the input X and the input X of the signal 120. An inverter for inverting the output of the amplitude comparator 104 or a switching circuit for switching between the input X and the input Y of the amplitude comparator 104 may be provided depending on whether or not it is present. Further, also in the case of detecting the phase error of the sampling clock 130 with respect to the previous signal level S4 of the two continuous signal levels S4, similarly, it is sufficient to provide the corresponding holding circuit and inverter. .

As the determination result of the comparator 101, the previous signal level S5 of the two consecutive signal levels S5 is obtained.
As another example of detecting the phase error of the sampling clock 130, the amplitude comparator 104 constantly compares the signal level of the signal 13 with the signal level S5 with respect to “1” of the signal 120, and compares the two. The resulting signal 123 is held for only one clock, and the held value is inverted by "1" of the signal 122, and the OR circuit 10
You may make it output to 9. The same applies when the phase error of the sampling clock 130 is detected for the previous signal level S4 of the two consecutive signal levels S4.

Further, the comparator 101 (or the comparator 10)
As a result of the determination in 5), when the phase error of the sampling clock 130 is detected for each of two continuous signal levels, the previous signal level of the two continuous signal levels is detected as described above. And the signal indicating the phase error and the signal 123 (or the signal 127) detected in this embodiment are ANDed and OR
It may be output to the circuit 109.

Further, in the magnetic reproducing apparatus 100, the set of the delay device 102 and the AND circuit 103, or the delay device 1
By connecting a plurality of sets of 06 and the AND circuit 107, it is possible to detect a desired continuous number for a predetermined value that can be determined by the comparator 101 or the comparator 105. Therefore, the reproduction signal is always different between immediately before and immediately after the signal detection reference point 30 with the signal detection reference point 30 corresponding to the predetermined value at the end of the sequence of the predetermined number of consecutive maximum values in the intermediate code sequence as a boundary. The present invention can be applied regardless of the maximum number of consecutive predetermined values in the intermediate code sequence and the predetermined value. it can. Specifically, in the present embodiment, the interleaved NRZI in which the maximum number of consecutive "1" s or "-1" s is 2 has been described, but the intermediate code sequence and the reproduced signal have the above-described properties. If
The phase of the sampling clock can be controlled for the reproduced signal corresponding to the intermediate code sequence which is another multi-level code sequence in the same manner as in the present embodiment.

(Second Embodiment) A second embodiment of the present invention will be described below with reference to the drawings. FIG. 7 is a block diagram showing the configuration of the magnetic reproducing apparatus 700 according to the second embodiment of the present invention. In FIG. 7, the first shown in FIG.
Since the constituent elements having the same functions as those of the magnetic reproducing apparatus 100 of the embodiment have already been described, the same reference numerals are given and the description thereof will be omitted.

The magnetic reproducing apparatus 700 includes a magnetic tape 1, a reproducing head 2, a reproducing amplifier 3, a partial response equalizing circuit 4, a PLL circuit 5, an A / D converter 7, a Viterbi decoder 8, a comparator 101 and a delay device. 102, AND circuit 103,
Amplitude comparator 104, comparator 105, delay device 106, AN
D circuit 107, amplitude comparator 108, OR circuit 109, integration circuit 110, phase control circuit 111, amplitude adjustment circuit 70
1 and an integrating circuit 702.

The magnetic reproducing apparatus 700 of the present embodiment differs from the magnetic reproducing apparatus 100 of the first embodiment in that the phase control circuit 1
11, the phase error of the sampling clock 130 is corrected based on the signal 128, and the amplitude adjustment circuit 701 further corrects the amplitude error of the signal 10 based on the same signal 128. The amplitude adjusting circuit 701 outputs the amplitude control signal 7 output from the integrating circuit 702.
The amplitude error of the signal 10 is corrected according to the voltage value of 12, and the signal 711 with the corrected amplitude error is output to the A / D converter 7. That is, when the voltage value of the amplitude control signal 712 becomes larger than the predetermined voltage value, the amplitude adjusting circuit 701 reduces the amplitude of the signal 10 by that amount, and the voltage value of the amplitude control signal 712 becomes smaller than the predetermined value. Then, the amplitude of the signal 10 is increased correspondingly.

The integrating circuit 702 is a primary integrating circuit similar to the integrating circuit 110, and is composed of a resistor and a capacitor as shown in FIG. However, the resistance value of the resistor and the electrostatic capacitance of the capacitor are set to appropriate values in the integrating circuit 702 and the integrating circuit 110, respectively. The integrating circuit 702 outputs the signal 12 which is a binary digital signal.
8 is smoothed, and an amplitude control signal 712, which is an analog signal indicating the amplitude error of the signal 10, is output to the amplitude adjustment circuit 701.

In the following, as shown in FIG.
The amplitude of the signal 10 which is the input of the A / D converter 7 is A / D
The case where the signal level S6 or the signal level S7, which is the maximum amplitude level allowed for the converter 7, is exceeded will be described. In this case, the signal 10 has a signal level higher than the signal level S5 as the signal level corresponding to "1" of the intermediate code sequence at the signal detection reference point 30, and the signal level corresponding to "-1" of the intermediate code sequence. , A signal level smaller than the signal level S4 is taken. Therefore, in this case, the signal level of the signal 10 is "1" of the intermediate code sequence.
The signal level is higher than the signal level S5 in the vicinity of the signal detection reference point 30 having the signal level corresponding to
In the vicinity of the signal detection reference point 30 having a signal level corresponding to "1", the signal level is smaller than the signal level S4. Therefore, it is possible that the amplitude comparator 104 outputs "1" as the signal 123 although the phase of the sampling clock 130 is delayed. Also, the amplitude comparator 10
The same thing happens in 8.

Furthermore, the amplitude of the signal 10 is the signal level S3.
Alternatively, when the signal level is lower than the signal level S1, the amplitude comparator 104 or the amplitude comparator 108 outputs the signal even though the phase of the sampling clock 130 is advanced.
It is possible that "0" is output as the signal 123 or the signal 127. As a result, the phase control circuit 11
No. 1 cannot correct the phase error of the sampling clock 130, which causes deterioration of the error rate in identifying the intermediate code sequence.

Therefore, in the magnetic reproducing apparatus 700, the signal 1 indicating the phase error or the amplitude error is used to output the signal 1
Controls an amplitude value of zero. However, the magnetic reproducing device 700
Is configured so that the amplitude error correction by the amplitude adjustment circuit 701 has a faster error correction response than the phase error correction by the phase control circuit 111. Hereinafter, the amplitude control operation of the signal 10 in the magnetic reproducing apparatus 700 will be described with reference to FIG. 7. First, the signal 128 output from the OR circuit 109
Are input to the integrating circuit 110 and the integrating circuit 702. This signal 128 is the signal 1 at the sampling point.
Although it is a signal indicating a phase error of 0, it is also a signal indicating an amplitude error of the signal 10 at the sampling point.
That is, the signal 128 is the sampling clock 130.
When the phase of the sampling clock 130 is advanced, it becomes "1", and when the phase of the sampling clock 130 is delayed, it becomes "0". Further, when the phase of the sampling clock 130 is correct, it becomes “1” when the amplitude of the signal 10 at the signal detection reference point 30 exceeds the signal level S3 or the signal level S4, and the signal 10 at the signal detection reference point 30 is detected.
When the amplitude of the signal becomes equal to or lower than the signal level S3 or the signal level S4, it becomes "0".

The signal 128 input to the integrating circuit 702
Is smoothed in the integrating circuit 702 and is output to the amplitude adjusting circuit 701 as an analog signal amplitude control signal 712. The amplitude adjusting circuit 701 amplifies the signal 10 according to the voltage value of the input amplitude control signal 712 (signal 10
Including the case of reducing the amplitude of. Then, the amplitude of the signal 10 is adjusted so that the maximum amplitude value of the signal 10 becomes a predetermined constant amplitude value. That is, when the voltage value of the input amplitude control signal 712 exceeds the predetermined voltage value and becomes large, the amplitude adjusting circuit 701 reduces the amplitude of the signal 10 according to the magnitude of the difference, and performs the amplitude control. When the voltage value of the signal 712 becomes smaller than a predetermined voltage value, the amplitude of the signal 10 is increased according to the magnitude of the difference.

As described above, the magnetic reproducing device 70 of the present embodiment.
According to 0, even if the phase of the sampling clock 130 deviates from the signal detection reference point 30, as in the magnetic reproducing apparatus 100 of the first embodiment, only the comparison of the signal levels is performed based on the regular property of the signal 10. The phase error is detected and corrected. Therefore, the sampling clock 13
It is possible to prevent the deterioration of the error rate in the discrimination of the intermediate code sequence due to the phase error of 0 with a simple configuration and good responsiveness, and to prevent the deterioration of the code error rate due to the amplitude fluctuation of the signal 10. .

In the detection of the phase / amplitude error in this embodiment, the signal 10 is detected at consecutive sampling points.
When two signal levels S5 shown in FIG.
And two consecutive signal levels S4 were detected, and the phase / amplitude error was detected for each case. However, the present invention is not limited to this, and the phase / amplitude error of the sampling clock 130 can be detected by detecting only the case where two signal levels of either one continue, and detecting the phase / amplitude error in that case. Amplitude error can be corrected with good response.

In the detection of the phase / amplitude error in this embodiment, the signal 10 is detected at consecutive sampling points.
When the signal level S5 or the signal level S4 of 2 continues, the phase / amplitude error is detected by detecting the phase / amplitude error of the signal 13 at the time of taking the signal level of the latter two signal levels of the signal 10. Although the correction is performed, the present invention is not limited to this, and both the signal 13 at the time of taking the previous signal level of the two signal levels of the signal 10 or the signal level of the two signal 10 continuing. It is also possible to detect the phase / amplitude error and correct the phase / amplitude error for each of the signals 13 when the signal level of 1 is taken.

Further, although the response speed of the amplitude error correction in this embodiment is faster than that of the phase error correction, the present invention is not limited to this, and the amplitude error correction and the phase error correction are not limited to this. An adjustment control circuit may be provided to control the adjustment degree of the correction. For example, only the amplitude error correction may be performed first, and the phase error correction may be started when the error correction subsides.

(Third Embodiment) Next, a third embodiment of the present invention will be described with reference to the drawings. FIG. 8 is a block diagram showing the configuration of the magnetic reproducing apparatus 800 according to the third embodiment of the present invention. In FIG. 8, constituent elements having the same functions as those of the magnetic reproducing apparatus 100 of the first embodiment and the magnetic reproducing apparatus 700 of the second embodiment shown in FIGS. 1 and 7 have already been described. Therefore, the same reference numerals are given and description thereof is omitted.

The magnetic reproducing apparatus 800 includes a magnetic tape 1, a reproducing head 2, a reproducing amplifier 3, a partial response equalizing circuit 4, a PLL circuit 5, an A / D converter 7, a Viterbi decoder 8, a comparator 101 and a delay device. 102, AND circuit 103,
Amplitude comparator 104, comparator 105, delay device 106, AN
D circuit 107, amplitude comparator 108, OR circuit 109, integration circuit 110, phase control circuit 111, amplitude adjustment circuit 70
1, integrating circuit 702, DC level adjusting circuit 801, DC
A level control circuit 802 and an integrating circuit 803 are provided.

The magnetic reproducing apparatus 800 of this embodiment is different from the magnetic reproducing apparatus 100 of the first embodiment and the magnetic reproducing apparatus 700 of the second embodiment in that the DC level control circuit 802 determines the DC offset value of the signal 13. Deviation is detected and D
Controlling the DC offset value of the signal 10 according to the C control signal 813. The DC level adjusting circuit 801 is
When the signal level of the DC control signal 813 becomes higher than a predetermined voltage value, the DC offset value of the signal 10 is reduced accordingly, and when the signal level of the DC control signal 813 becomes lower than the predetermined voltage value, the DC level of the signal 10 is reduced accordingly. The offset value is increased to operate so that the signal level of the signal 13 representing "0" in the intermediate code sequence becomes exactly the signal level S2. As a result, the DC level adjusting circuit 801 causes the signal 1
Signal 811 obtained by correcting the DC offset value of 0
Is output to the amplitude adjusting circuit 701. However, the response of the error correction in the DC level adjusting circuit 801, the amplitude adjusting circuit 701, and the phase controlling circuit 111 is the DC level adjusting circuit 801 and the amplitude adjusting circuit 70 in order of the response speed.
1, the phase control circuit 111.

The DC level control circuit 802 is connected to the comparator 10
The signal level of the signal 13 at the time when the signal level of the signal 13 is determined to be equal to or lower than the signal level S3 by 1 is compared with the signal level S2, and if the DC offset of the signal 10 exceeds the signal level S2. “1” is output to the integrating circuit 803 otherwise “0” is output. The DC level control circuit 802 will be described below in more detail with reference to FIG. 9 and its operation.

FIG. 9 is a block diagram showing the structure of the DC level control circuit 802. DC level control circuit 802
Includes a comparator 901, a comparator 902, and a calculator 903. As shown in FIG. 8, the DC level control circuit 80
The signal 120 which is the output of the comparator 101 and the signal 13 which is the output of the A / D converter 7 are input to 2. The signal 13 input to the DC level control circuit 802 is the comparator 901.
And to the respective inputs X of the comparator 902.
In addition, the signal 12 input to the DC level control circuit 802
0 is inverted and input to the arithmetic unit 903.

The input Y of the comparator 901 is shown in FIG.
The signal level S1 shown in is input. Comparator 901
Outputs "1" as a signal 911 when X> Y is satisfied, and otherwise outputs "0". That is, the comparator 901 determines that the signal level represented by the signal 13 is the signal level S1.
When it is larger, "1" is output. The calculator 903 is a two-input AND circuit, and one input of the calculator 903 is “0” if the signal 120 is “1”, and is “0”.
If so, the inverted signal of the signal 120, which is “1”, is input, and the signal 911 that is the output of the comparator 901 is input to the other input of the arithmetic unit 903. The arithmetic unit 903 obtains the logical product of these two inputs and outputs it as a signal 912. That is, the computing unit 903 outputs “1” as the signal 912 when the signal 13 is higher than the signal level S1 and lower than or equal to the signal level S3. This indicates that the signal 13 at this time represents “0” of the intermediate code sequence.

As described above, the signal 13 is input to the input X of the comparator 902, and the input Y is input to the input Y of FIG.
The signal level S2 shown in is input. Further, the signal 912 is input to the comparator 902. Comparator 9
02 is input X and input Y when the signal 912 is “1”.
And when X> Y is satisfied, the signal 812
"1" is output as. In other cases, the comparator 902 outputs “0” as the signal 812. That is,
The signal 812 becomes “1” because the intermediate code sequence is “0”.
This is the case where the signal level of the signal 13 that represents is higher than the signal level S2. Further, the signal 812 becomes “0” when the signal level of the signal 13 representing “0” in the intermediate code sequence is equal to or lower than the signal level S2, and when the signal 13 is a code other than “0” in the intermediate code sequence. This is the case of expressing a value.

As for the signal 10, if there is no phase error of the sampling clock 130 and no DC offset error of the signal 10, the signal 13 indicating the signal level of the sampled signal 10 is "0" in the intermediate code sequence. "
The signal level of the signal 10 at the point of time when is expressed should be exactly the signal level S2. Therefore, assuming that there is no phase error in the sampling clock 130, the signal 8
The fact that 12 is "1" indicates that the DC offset of the signal 10 is larger than the signal level S2 that is its reference value. Further, the signal 13 is the intermediate code sequence “0”.
Assuming that there is no phase error of the sampling clock 130, the signal 812 becomes “0”, which indicates that the DC offset of the signal 10 is equal to or lower than the reference level signal level S2.

The integrating circuit 803 is a primary integrating circuit similar to the integrating circuit 110 and the integrating circuit 702, and is composed of the resistors and capacitors shown in FIG. However,
The resistance value of the resistor and the capacitance of the capacitor are set to appropriate values in the integrating circuit 110, the integrating circuit 702, and the integrating circuit 803, respectively. The signal 812 output from the comparator 902 shown in FIG.
03 is input. Signal 8 input to integrating circuit 803
12 is smoothed by the integrating circuit 803 and input to the DC level adjusting circuit 801 as a DC control signal 813.

As described above, the magnetic reproducing device 8 according to the present embodiment.
According to 00, as in the magnetic reproducing apparatus 100 of the first embodiment, the phase error of the sampling clock 130 is detected only by comparing the signal levels of the signal 13 based on the regular property of the signal 10. Clock 13
Even if the phase of 0 deviates from the signal detection reference point 30, the phase error can be corrected with a simple configuration and good responsiveness. As a result, the magnetic reproducing device 800 is set to the sampling clock 1 depending on the usage environment of the magnetic reproducing device 800.
Even when the phase error of 30 occurs, the deterioration of the code error rate of the identified intermediate code sequence can be prevented.

Further, the magnetic reproducing apparatus 800, like the magnetic reproducing apparatus 700 of the second embodiment, has the same signal 128 indicating the detection result of the phase error of the sampling clock 130.
, The amplitude error of the signal 10 is detected at the same time as the phase error of the sampling clock 130, and the phase error and the amplitude error are corrected with a simple configuration and with good responsiveness. Even if an amplitude error occurs, the deterioration of the code error rate of the identified intermediate code sequence can be prevented more accurately.

In addition to the above effects, the magnetic reproducing apparatus 800 has a simple structure even when the DC offset value at the signal detection reference point 30 of the signal 10 is deviated as shown in FIG. 12B. Of the DC offset value of the sampling clock 130, the amplitude error of the signal 10, and the signal 1
Even if a DC offset error of 0 occurs, it is possible to prevent the code error rate of the identified intermediate code sequence from degrading more accurately.

In the phase error detection according to the present embodiment, in the signal 10, the signal level S5 shown in FIG.
However, the present invention is not limited to this, and the phase error is detected even if only one of the signal levels of two continues. it can.

Further, in the phase error detection in this embodiment, when two signal levels S5 and S4 shown in FIG. 11A continue, the amplitude error of the latter signal of the following two signals is detected. Although the phase error correction is performed, the present invention is not limited to this. The phase error correction is performed by detecting the amplitude error from the previous signal of the following two signals or using both of the following two signals. It may be done.

Further, although the response speed of the error correction of the DC offset value in this embodiment is faster than that of the amplitude and phase error correction, the present invention is not limited to this, and the DC offset value, An adjustment control circuit for controlling the adjustment value of the amplitude value and the phase error correction may be provided. For example, only the DC offset value may be corrected first, and the amplitude error correction and the phase error correction may be sequentially started.

[0110]

As described above, according to the present invention as set forth in claim 1, the output value of the A / D conversion means and the The phase shift of the sampling clock can be easily detected only by comparing the corresponding amplitude reference value. As a result, the phase control means can correct the phase error of the sampling clock with good responsiveness without performing complicated calculations and with a simple configuration. Further, since the phase error is detected for each maximum continuous section of the predetermined value included in the ternary code string, the phase error should always be detected and corrected without any temporal bias in a certain time range. You can

According to the present invention described in claim 2, also in the magnetic reproducing apparatus for performing partial response maximum likelihood decoding using the intermediate code sequence belonging to PR4, the same effect as that of the magnetic reproducing apparatus described in claim 1 can be obtained. Therefore, it is possible to prevent deterioration of the code error rate in the decoding means with good responsiveness. According to the third aspect of the present invention, in addition to the above effects, the phase control means obtains the sampling clock according to the magnitude of the phase control signal obtained by smoothing the amplitude comparison signal which is a binary signal. Since the phase is delayed, the phase error of the sampling clock can be smoothly corrected, and the phase error can be corrected with good responsiveness to the detection of the phase error.

According to the fourth aspect of the present invention, in addition to the above effects, a comparing means for comparing the output value of the A / D converting means and the amplitude reference value with each other, and an output value of the A / D converting means. The phase error of the sampling clock can be easily detected with a simple configuration, which is a combination of a predetermined value detecting means for comparing the magnitude of the predetermined threshold value with a predetermined threshold value, a delay means, and a logical product calculating means.

According to the fifth aspect of the present invention, the fact that the amplitude comparison signal indicating the detection result of the phase error simultaneously indicates the detection result of the amplitude error of the reproduction signal is utilized to obtain the same amplitude. By using the comparison signal, it is possible to simultaneously correct the phase error of the sampling clock and the amplitude error of the reproduction signal. Therefore, in addition to the effect of the present invention according to any one of claims 1 to 4, in order to detect the amplitude error of the reproduced signal even when the phase error of the sampling clock and the amplitude error of the reproduced signal occur. It is possible to correct both of them with good responsiveness with a simple configuration without separately providing the above means, and it is possible to more accurately prevent the deterioration of the code error rate in the magnetic reproducing apparatus.

According to the sixth aspect of the present invention, in addition to the above effects, the amplitude adjusting means adversely affects the phase correction by the phase controlling means and the reliability of the output value of the A / D converting means. It is possible to reduce the amplitude error of the reproduction signal, which lowers the frequency, more quickly than the phase correction by the phase control means. Therefore, the phase control means can correct the phase error of the sampling clock more accurately, and can more accurately prevent the deterioration of the code error rate in the magnetic reproducing apparatus.

According to the present invention of claim 7, claim 1
In addition to the effect of the present invention according to any one of claims 4 to 4, it is possible to easily detect a DC offset error by comparing a reference value corresponding to each code value and an output value of the A / D conversion means. You can As a result, the DC level adjusting means, with respect to the DC level offset error of the reproduction signal,
With a simple structure, it is possible to adjust the DC level of the reproduction signal with good responsiveness. As a result, the magnetic reproducing apparatus more accurately degrades the code error rate even when a phase error of the sampling clock or a DC level offset error of the reproduced signal occurs due to a change in the usage environment of the magnetic reproducing apparatus. Can be prevented.

According to the eighth aspect of the present invention, in addition to the above effects, the DC level adjusting means causes the DC offset error, which has a great adverse effect on the phase error correction of the sampling clock by the phase controlling means, by the phase controlling means. It can be reduced more quickly than the phase correction is performed. Therefore, the phase control means can correct the phase error of the sampling clock more accurately, and can more accurately prevent the deterioration of the code error rate in the magnetic reproducing apparatus.

According to the present invention of claim 9, claim 5
Alternatively, in addition to the effect of the present invention as set forth in claim 6, the DC offset error can be easily detected by comparing the reference value corresponding to each code value with the output value of the A / D conversion means. . As a result, the DC level adjusting means can adjust the DC level of the reproduction signal with a simple configuration and good responsiveness to the offset error of the DC level of the reproduction signal. As a result, the magnetic reproduction apparatus can more accurately perform the code error rate even when the phase error of the sampling clock, the amplitude error of the reproduction signal, and the DC level offset error occur due to changes in the usage environment of the magnetic reproduction apparatus. Can be prevented from deteriorating.

According to the tenth aspect of the present invention, in addition to the above effects, the DC level adjusting means adversely affects both the amplitude adjustment of the reproduction signal by the amplitude adjusting means and the phase correction of the sampling clock by the phase controlling means. It is possible to reduce the DC offset error of the reproduction signal that causes the error more quickly than the amplitude adjustment and the phase correction. Therefore, the amplitude adjusting means can correct the amplitude error of the reproduction signal with higher accuracy, and the phase controlling means can correct the phase error of the sampling clock with higher accuracy by this amplitude adjustment. As a result, the magnetic reproducing apparatus causes deterioration of the code error rate even when a phase error of the sampling clock, an amplitude error of the reproduction signal, and a DC level offset error occur due to changes in the usage environment of the magnetic reproducing apparatus. It can be prevented more accurately.

According to the eleventh aspect of the present invention, assuming that there is no phase error of the sampling clock, the timing at which only the DC level offset error can be detected is determined by the output value of the A / D conversion means and the threshold value. Can be detected by a simple method, ie, by a simple structure of the DC level detecting means. Further, the DC offset error can be easily detected by comparing the output value of the A / D conversion means at that time with the reference value corresponding to the detected code value. Further, the DC level of the reproduction signal can be adjusted according to the magnitude of the offset control signal, which is obtained by smoothing the binary DC offset detection signal. Therefore, according to the present invention, the effect according to the present invention according to any one of claims 7 to 10 can be obtained efficiently and with good response by such a simple configuration.

[Brief description of the drawings]

FIG. 1 is a magnetic reproducing device 100 according to a first embodiment of the present invention.
FIG. 3 is a block diagram showing the configuration of FIG.

FIG. 2A is a block diagram showing a configuration of a comparator 101. FIG. 2B is a block diagram showing the configuration of the comparator 105.

FIG. 3 is a waveform diagram showing a part of a waveform of the signal 10 in which two consecutive signal levels S5 are obtained at each signal detection reference point 30.

FIG. 4 is a sampling clock 130 having a phase error.
9 is a waveform diagram showing a waveform of a signal 10 having a relative phase error with respect to sampling points 80, 81, 82 according to FIG.

5 is a block diagram showing the configuration of an integrating circuit 110. FIG.

FIG. 6A is a waveform diagram showing a signal 128 which is an input of the integrating circuit 110. FIG. 6B is a waveform diagram showing the signal 129 which is the output of the integrating circuit 110.

FIG. 7 is a magnetic reproducing device 700 according to a second embodiment of the present invention.
FIG. 3 is a block diagram showing the configuration of FIG.

FIG. 8 is a magnetic reproducing device 800 according to a third embodiment of the present invention.
FIG. 3 is a block diagram showing the configuration of FIG.

9 is a block diagram showing the configuration of a DC level control circuit 802. FIG.

FIG. 10 is a block diagram showing a configuration of a conventional magnetic reproducing device 20 for reproducing digital information recorded on a magnetic tape 1.

11A is a waveform diagram showing an eye pattern of a signal 10 output from the partial response equalization circuit 4. FIG. FIG. 11B is a waveform diagram showing the sampling clock 12 which is the output of the delay adjuster 6.

FIG. 12A is a waveform diagram showing an eye pattern when the amplitude value of the signal 10 is larger than the reference amplitude value. FIG. 12B is a waveform diagram showing an eye pattern when a DC offset is generated in the signal 10 which is the input of the A / D converter 7.

[Explanation of symbols]

 1 magnetic tape 2 reproducing head 3 reproducing amplifier 4 partial response equalizing circuit 5 PLL circuit 7 A / D converter 8 Viterbi decoder 6 phase control circuit 101 comparator 102 delay device 103 AND circuit 104 amplitude comparator 105 comparator 106 106 delay Unit 107 AND circuit 108 amplitude comparator 109 OR circuit 110 integrating circuit 111 phase control circuit

Claims (11)

[Claims] 1. An analog signal reproduced from a recording medium in correspondence with a ternary code string having three values, the maximum number of consecutive predetermined values of the three values is limited, and the amplitude of the analog signal. The absolute value of exceeds the predetermined amplitude reference value in the continuous section of the predetermined value in the ternary code string, and the amplitude reference value in the section corresponding to the middle of the maximum continuous number section and the code values before and after it. A phase control means for controlling the phase of the sampling clock so that an analog signal having an amplitude equal to the amplitude reference value corresponding to a predetermined value at the end of the maximum continuous section is sampled by utilizing the property below. A magnetic reproducing apparatus comprising: reproducing means for reproducing the analog signal corresponding to the ternary code string from a recording medium and outputting the reproduced analog signal as a reproduced signal; Clock generating means for generating a lock; A / D converting means for sampling the reproduced signal in synchronization with a sampling clock and converting the reproduced signal into a multi-valued digital signal; and a maximum continuous number from the A / D converting means. A maximum number detecting means for detecting that a value corresponding to the predetermined value is output and outputting a maximum number detection signal indicating the output, and an A / D conversion corresponding to a predetermined value at either end of the maximum continuous number. The amplitude of the reproduced signal represented by the output of the means,
Comparison means for comparing the amplitude reference value and outputting an amplitude comparison signal indicating whether or not the phase of the sampling clock is advanced; and phase control means for controlling the phase of the sampling clock based on the amplitude comparison signal. A magnetic reproducing apparatus comprising: 2. The magnetic reproducing apparatus according to claim 1,
The ternary code string is an intermediate code sequence belonging to the partial response class 4, and the reproducing means corresponds to each of the ternary values of the intermediate code sequence of the reproduced analog signal. The magnetic reproduction apparatus further includes an equalization unit that equalizes an amplitude value equal to a predetermined amplitude reference value and outputs an equalized analog signal as a reproduction signal. It is characterized by comprising decoding means for identifying each code value of the intermediate code sequence from the multi-valued digital signal which is the output of, and decoding the information recorded on the recording medium by Viterbi decoding from the identified intermediate code sequence. Magnetic reproducing device. 3. The magnetic reproducing apparatus according to claim 1 or 2, wherein the phase control means smoothes the amplitude comparison signal and generates a phase control signal which is an analog signal, A magnetic reproducing apparatus comprising: a phase delay unit that delays the phase of a sampling clock according to the magnitude of a phase control signal. 4. The magnetic reproducing device according to claim 1, wherein the maximum number of consecutive predetermined values in the ternary code string is 2, and the maximum number detecting means is A predetermined value detection signal indicating the detection result by comparing the output value of the A / D conversion means with a predetermined threshold value to detect that the value corresponding to the predetermined value is output from the A / D conversion means. A predetermined value detecting means for outputting the predetermined value detecting signal, a delay means for delaying the predetermined value detecting signal by one clock of the sampling clock, and outputting a delay detecting signal, and a logical product of the predetermined value detecting signal and the delay detecting signal, And a logical product calculating means for outputting the calculation result as a maximum number detection signal. 5. The magnetic reproducing apparatus according to claim 1, further comprising: an amplitude control signal generating unit that smoothes the amplitude comparison signal and generates an amplitude control signal that is an analog signal. An amplitude adjusting unit is provided in the preceding stage of the A / D converting unit and adjusts the amplitude of the reproduction signal according to the magnitude of the amplitude control signal. The clock generating unit adjusts the amplitude by the amplitude adjusting unit. A magnetic reproducing apparatus, wherein a sampling clock is generated from the reproduced signal thus generated, and the A / D conversion means samples the reproduced signal whose amplitude is adjusted by the amplitude adjusting means. 6. The magnetic reproducing apparatus according to claim 5, wherein the amplitude adjustment of the reproduction signal by the amplitude adjusting means has a faster response to an error than the phase correction of the sampling clock by the phase controlling means. And a magnetic reproducing device. 7. The magnetic reproducing apparatus according to claim 1, further comprising a predetermined reference value corresponding to the output value of the A / D conversion means and the code value represented by the output value. DC offset detection means for comparing the value with a value to detect whether the DC level of the reproduction signal is higher than a predetermined DC level reference value, and outputting a DC offset detection signal indicating a detection result; And a direct current level adjusting means for adjusting the direct current level of the reproduction signal based on a direct current offset detection signal, the clock generating means having the direct current level adjusted by the direct current level adjusting means. A sampling clock is generated from the reproduced signal, and the A / D conversion unit samples the reproduced signal whose DC level is adjusted by the DC level adjusting unit. Magnetic reproducing apparatus according to claim and. 8. The magnetic reproducing apparatus according to claim 7, wherein the DC level adjustment of the reproduction signal by the DC level adjusting means has a faster response to an error than the phase correction of the sampling clock by the phase control means. Magnetic reproducing apparatus characterized by. 9. The magnetic reproducing apparatus according to claim 5, further comprising: comparing an output value of the A / D conversion means with a predetermined reference value corresponding to the code value represented by the output value. Then, a DC offset detection means for detecting whether or not the DC level of the reproduction signal is larger than a predetermined DC level reference value, and outputting a DC offset detection signal indicating the detection result, and a front stage of the amplitude adjustment means. And a DC level adjusting means for adjusting the DC level of the reproduction signal based on the DC offset detection signal, wherein the amplitude adjusting means adjusts the amplitude of the reproduction signal whose DC level is adjusted by the DC level adjusting means. A magnetic reproducing device characterized by: 10. The magnetic reproduction apparatus according to claim 9, wherein the direct current level adjustment of the reproduction signal by the direct current level adjustment means, the amplitude adjustment of the reproduction signal by the amplitude adjustment means, and the sampling by the phase control means. Clock phase correction is a magnetic reproducing device characterized by quick response to errors in this order. 11. The magnetic reproducing apparatus according to claim 7, wherein the DC offset detecting means compares the output value of the A / D converting means with a predetermined threshold value. DC level detection means for detecting that the output value of the A / D conversion means represents the code value associated with the DC level of the reproduction signal, and a reference value corresponding to the detected code value. And an output value of the A / D conversion means at the time when the code value is detected, and indicates whether or not the DC level of the reproduction signal is larger than the reference value of the code value associated therewith. A direct current offset detection signal generating means for generating a direct current offset detection signal, wherein the direct current level adjusting means smoothes the direct current offset detection signal and performs offset control which is an analog signal. No. comprises an offset control signal generating means for generating said DC level adjusting means, depending on the magnitude of the offset control signal, a magnetic reproducing apparatus characterized by adjusting the DC level of the reproduced signal.