JP3347536B2 - Playback device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reproducing apparatus, and more particularly, to an apparatus for reproducing a clock from a digital signal reproduced from a recording medium.

[0002]

2. Description of the Related Art It has been known that a device for transmitting (recording / reproducing) data at high speed, such as a digital VTR, uses a phase locked loop (hereinafter, PLL) when extracting a clock from a received data sequence. I have.

FIG. 13 shows the configuration of such a PLL circuit.

In FIG. 13, a signal reproduced from a tape (not shown) is input to a phase comparator 102, and a phase difference from a clock output from a voltage controlled oscillator (hereinafter, VCO) 106 is detected. The output of the phase comparator 102 is input to the VCO 106 via the loop filter 103, and outputs a signal having a frequency corresponding to the output voltage of the loop filter as a clock.

That is, when the phase of a reproduced digital signal changes due to uneven rotation of a rotating head (not shown) or expansion and contraction of a tape, the phase difference between the generated clock and the phase comparator
At the VCO 106 via the loop filter 103.
By controlling the oscillating frequency by feeding back the clock, a clock that follows the phase fluctuation of the reproduced digital signal can be generated.

[0006]

Here, consider a case where high-speed reproduction, that is, a so-called picture search is performed.

In a digital VTR, guard bandless recording is usually performed by heads having different azimuth angles in order to perform high-density recording.

Although this does not pose a problem during normal reproduction, the speed component in the direction orthogonal to azimuth during picture search differs depending on the azimuth angle. One of the frequencies of the reproduced signal reproduced from the head is separated to a higher frequency and the other to a lower frequency in accordance with the search speed.

Therefore, conventionally, in the case of two kinds of azimuths, the frequency of the reproduction signal is normally reproduced by controlling the number of rotations of the drum so that the average value of the relative speed of the two heads with the tape is constant. I was trying to approach the frequency of the time.

However, even if the control is performed in this manner, even if the search is performed at a higher speed, the difference in the frequency of the reproduced signal due to the difference between the two azimuths becomes ± 1% of the oscillation frequency in, for example, a 100-fold search, and the PLL lock is performed. There was a problem that it was out of range.

Therefore, an accurate clock cannot be generated during a high-speed search, and a good reproduced signal cannot be obtained.

Further, only a low-speed search could be performed to obtain a good reproduced signal.

In view of the above problems, an object of the present invention is to provide a device which can obtain a clock that accurately follows the reproduction signal frequency even in the case of a high-speed search or the like.

[0014]

SUMMARY OF THE INVENTION In order to solve the conventional problems and to achieve the above object, the present invention provides a reproducing means for reproducing a signal from a recording medium by a plurality of heads having different azimuth angles; Generating means for generating a clock synchronized with the reproduction signal; counting means for counting the clock generated by the generating means; comparing means for comparing the count value of the counting means with a value of reference data; Control means for controlling the generating operation of the generating means using the output of the means; and setting means for setting the value of the reference data according to the azimuth angle of the head.

[0015]

Embodiments of the present invention will be described below in detail with reference to the drawings.

In this embodiment, a case where the present invention is applied to a digital VTR will be described. FIG. 1 is a block diagram showing a configuration of a reproduction system of such a digital VTR.

In FIG. 1, a magnetic tape 1 is alternately traced by magnetic heads 3a and 3b mounted on a rotating drum 2 with a phase difference of about 180 ° to reproduce a digital signal, and a digital signal is reproduced via a switch SW. The signal is output to the amplifier 4, where it is amplified and output to the reproduction equalization circuit 5. In the digital VTR according to the present embodiment, a video signal for one frame is recorded on ten tracks, but it is needless to say that other video signals may be used.

The reproduction equalization circuit 5 is an equalization circuit for compensating for a change in signal characteristics in the magnetic recording / reproduction system, and performs so-called integral equalization. The equalized reproduction signal is output to the A / D converter 6.

Sampled by the A / D converter 6,
The signal converted into the digital signal is supplied to the clock generation circuit 1
4 and delayed by two clocks by a delay circuit 7 and subtracted from the original signal by a subtractor 8. Here, the conversion of the reproduced digital signal into a digital signal by the A / D converter 6 means that even if the reproduced signal supplied from the switch SW is a digital signal, the amplitude of the signal is varied in an analog manner. The A / D converter 6 converts the signal having such an analog amplitude into a digital signal of a plurality of bits of one sample again, and the Viterbi decoding circuit 9 at the subsequent stage converts the signals into "1" and "0". It is restored to a binary signal.

By such a subtraction operation, the integral equalized waveform is converted into a waveform having a PR (1, 0, -1) characteristic, and is subjected to maximum likelihood decoding by the Viterbi decoding circuit 9. PR (1,0,
-1) The combination of the method and Viterbi decoding is often used in digital VTRs and the like that use high-density magnetic recording, avoiding poor low-frequency characteristics (S / N, waveform distortion, etc.) of the magnetic recording system and preventing transmission errors. Can be kept to a minimum.

The clock generation circuit 14 generates an operation clock for each part of the apparatus in addition to the clock used in the A / D converter 6, and its detailed operation will be described later.

The reproduced data restored by the Viterbi decoding circuit 9 is corrected by an error correction circuit (ECC circuit) 10 using a parity data added at the time of recording to correct an error occurring in a transmission path, and output to an image decoding circuit 11. You. The image decoding circuit 10 expands the information amount of the reproduced data compressed at the time of recording, and outputs it to the D / A converter 12. D / A converter 12
Converts the input digital data into analog data and outputs it via the output terminal 13.

A head switching signal generation circuit 15 generates a switching signal (hereinafter SWP) for the heads 3a and 3b based on a signal (PG) indicating the rotation phase of the rotating drum (rotating head). Output to the clock generation circuit 14.

Here, the relationship between the head and the tape during the search and the change in the frequency of the reproduced signal will be described.

When performing azimuth recording in which the gaps of the heads 3a and 3b in FIG. 1 are inclined at different angles with respect to the head scanning direction, the following specific phenomena are observed.

FIG. 2 is a view of the tape 1 as viewed from the surface of the magnetic medium.
It is assumed that the azimuth angle of a is −α °, the azimuth angle of the magnetic head 3b is + α °, and the track inclination angle is θ °, as shown in the figure.

At the time of normal reproduction (reproduction is performed by running a tape at the same speed as at the time of recording) on a track recorded at a track inclination angle θ ° at the time of recording, the head 3a scans the track 1A of minus azimuth. The traveling speed of the tape 1 and the number of rotations of the rotary drum 2 are controlled so that the head 3b scans the plus azimuth track 1B.

Next, when a search in the forward direction is performed, the trajectory scanned by the heads 3a and 3b is as shown by a broken line in FIG. In this case, since the scanning direction of the heads 3a and 3b and the running direction of the tape 1 are forward, the heads 3a and 3b
The relative speed between b and the tape 1 becomes smaller than during normal playback. Therefore, the frequency of the reproduction signal becomes lower.

FIGS. 4 and 5 are enlarged views of the head and track at this time.

In FIGS. 4 and 5, lines in each track indicate each bit of recorded data, and Pa, Pb
Indicates the pitch of the bit interval in tracks 1A and 1B, respectively.

As shown in FIG. 4, during normal reproduction, the pitch Pa of the reproduction bit interval of the head 3a, which is minus azimuth, and the pitch Pb of the reproduction bit interval of the head 3b, which is plus azimuth, were equal. At the time of the search, as shown in FIG.
A difference occurs between a and Pb, and a phenomenon occurs in which the frequency of the reproduction signal from the minus azimuth head 3a is higher than the frequency of the reproduction signal from the plus azimuth head 3b.

FIG. 6 shows the state of the frequency of the reproduced signal with respect to the change in the double speed of the search when the rotation speed of the drum is fixed.

In FIG. 6, in the forward search, as the double speed number increases, the frequency of the reproduction signal of the minus azimuth head increases at a steeper angle than the frequency of the frequency of the reproduction signal of the plus azimuth head. Also, the search in the negative direction shows almost the opposite tendency.

In this embodiment, an apparatus for generating an optimal clock that follows the frequency of the reproduction signal from each head even when there is a difference in the frequency of the reproduction signal due to the difference in azimuth of the head will be described.

FIG. 7 shows the clock generation circuit 14 shown in FIG.
FIG. 3 is a block diagram illustrating a configuration example of FIG.

In FIG. 7, the phase error between the reproduced signal input to the input terminal 101 and the VCO 106 is input to the loop filter 103, averaged, and the reproduced signal and the VCO 1
The PLL loop in which a signal having such a voltage as to cancel the phase error with the output of 06 is input to the VCO 106 is the same as the above-described conventional example.

Hereinafter, the features of this embodiment will be described.

The output of the VCO 106 oscillated as described above is input to the count circuit 118. Counting circuit 1
Reference numeral 18 denotes a certain period, for example, a period corresponding to a period during which the above-mentioned rotary head traces one track (hereinafter referred to as Ttr, which is 1/300 second here: shown in FIG. 8A).
, And outputs the result to the positive input terminal of the digital subtractor 119. The output of the register 121 or 122 supplied via the switch 123 is input to the negative input terminal of the subtractor 119.

A register 121 is a register for plus azimuth, and a register 122 is a register for minus azimuth. The register 121 is output to a subtractor 119 via a switch 123 which is switched according to a head reproducing a signal.

Here, reference numeral 124 denotes a timing generation circuit which receives a head switching signal (hereinafter referred to as SWP) output from the head switching signal generation circuit 15 in FIG.
Each of the timing signals shown in (b) to (e) is generated.
FIG. 8A is a diagram showing a state of an envelope of a reproduction signal.

The count circuit 118 is reset at the timing shown in FIG. 8B, and counts the number of clocks during a trace of one track.

The switch 123 switches according to the signal shown in FIG. In other words, the circuit is connected to the register 121 during the high level in FIG. 8C, and is connected to the register 122 during the low level.

First, during normal reproduction, the speed setting circuit 12
3, a signal indicating this is sent to the register rewriting circuit 12
6 is output. During normal reproduction, the register rewriting circuit 126 sets fce to the center frequency of the clock extracted from the reproduced digital signal containing jitter.
The same value of nt × Ttr is written to each of the registers 121 and 122. Therefore, if the VCO 106 oscillates at fcent, the output of the subtractor 119 becomes 0.

At the time of search reproduction, a signal indicating the running speed of the tape is similarly output from the speed setting circuit 125 to the register rewriting circuit 126. Then, the register rewriting circuit 126 determines a value corresponding to the change of the frequency shown in FIG. 6 for each head according to the input tape running speed, and writes the value into the registers 121 and 122.

Accordingly, the difference between the frequency of the reproduced signal and the frequency of the generated clock is output to the subtractor 119 in consideration of the azimuth angle of the reproducing head even during search reproduction.

The output of the subtractor 119 is adjusted in level by the coefficient unit 120 as described later, and is output to the negative input terminal of the digital subtractor 110.

On the other hand, the output of the loop filter 103 is output to the adder 104 and the low-pass filter (hereinafter, LPF) 108 as described above. LPF10
Reference numeral 8 denotes a filter serving as a pre-filter for sampling by the register 109. The output of the register 109 is output to the positive input terminal of the subtractor 110. Here, the register 109 stores the timing of FIG.
The output of the LPF 108 is sampled at the timing of t.

The subtracter 110 subtracts the output of the coefficient unit 120 from the output of the LPF 108 and outputs the result to the integrator 111.

The integrator 111 includes an adder 112 and a limiter 1
13, registers 115 and 116 and switches 114 and 1
17. Unless the upper and lower limit values are reached, each time a clock is input to the registers 115 and 116, the value input from the subtractor 113 is added.

Here, the register 115 is a register for plus azimuth, and the register 116 is a register for minus azimuth. The values output from the switch 114 in accordance with the clocks shown in FIGS. Written.

The switches 114 and 117 are switched according to the signal shown in FIG. That is, when the signal in FIG. 8C is at a high level, the signal is connected to the register 115, and when the signal is at a low level, the signal is connected to the register 116.

As described above, by controlling the rewriting operation of the register according to the head reproducing the signal,
The registers 115 and 116 perform the rewriting operation only when the reproduction signal from the corresponding azimuth head is obtained, and hold the value in other periods.

The output of the integrator 111 is output to the adder 104.

Next, the operation of clock generation in this embodiment will be described.

First, in the portion where the reproduction envelope is obtained in FIG. 8, the phase of the reproduction signal and the output clock of the VCO 106 is determined by the phase comparator (Phase Comparator: P).
C) A PLL is configured to be compared by 102, averaged by the loop filter 103 and output to the VCO 106 via the adder 104, and the oscillation output signal of the VCO 106 is output from the output terminal 107 to the A / D converter 6 Is output as a clock used in.

Next, a reproduction envelope is obtained,
That is, a case will be described in which the oscillation frequency of the VCO is about to decrease due to some external factor while the phase comparison circuit 102, the loop filter 103, and the PLL of the VCO 106 are in phase lock during the Ttr period. In this case, since a phase difference occurs between the input signals of the phase comparison circuit 102 during the period in which the reproduction envelope is obtained, the output voltage of the input signal decreases, and the output voltage of the loop filter 103 increases. Then, control is performed so that the output clock of the VCO 106 and the clock of the reproduction signal have the correct phases.

As described above, the phase error with the reproduced clock due to the error of the oscillation frequency of the VCO 106 is corrected.
In this state, the output of the loop filter 103 has also risen and is off the center of the PLL lock range. Therefore, if it is attempted to further correct the phase error with the reproduced clock from this state, the PLL is likely to be unlocked with respect to a change in phase.

Therefore, in the present embodiment, the phase error is detected with a time constant slower than that of the PLL loop and the tendency of the output of the loop filter 103 is detected through the path from the LPF 108 to the integrator 111 to the adder 104. , Loop filter 1
03 to the loop filter 10
The output of the loop filter 103 is always controlled by the PLL by making the bias of the output of the
Is held at the center of the lock range. Hereinafter, this operation will be described.

As described above, the register 109 operates at the timing of Ttr, that is, at 300 Hz.
Has a cutoff frequency of 150 Hz, and the response speed is very low. Therefore, the output of the LPF 108 does not change so much even during the period without the reproduction envelope, and when the output voltage of the loop filter 103 increases as described above due to the phase error between the VCO 106 and the reproduction signal, the output of the register 109 also increases accordingly. .

Therefore, the register 11 in the integrator 111
The value of 5,116 changes in the positive direction, resulting in integrator 1
The output from 11 to the adder 104 increases. Integrator 1
11 is equal to the error signal output from the loop filter 103 during the period Ttr.
The integrator 111 can make an error signal corresponding to the number of signals output from. That is, the loop filter 10
3 is controlled by the rise of the output of the integrator 111.
Of the loop filter 103
Can always be held at the center of the lock range of the PLL.

When the output of the adder 104 increases, VC
The oscillation frequency of O106 increases as described above, and the registers 115 and 116 do not change when the phase difference between the reproduced signal and the clock is eliminated. During this time, VCO
Since the oscillation frequency of the signal 106 does not change, no error signal is output from the subtractor 119. Therefore, the output of the register 109 is directly output as the output of the subtractor 110.

Here, the count circuit 118 and the register 1
The operation clock of 09 is set to the Ttr period, that is, 300 Hz. This is because the output of the integrator 111 is added to the adder 104 in the portion without the reproduction envelope, so that the portion with the envelope, that is, the reproduction signal is obtained. This is to prevent the disturbance of the PLL based on the instantaneous change of the input voltage of the VCO 106 in the portion where the signal is present. Also, in the case where the envelope is always obtained, if the operation is performed while a signal that is not a valid signal (for example, a video signal or an audio signal) is reproduced, the image or the audio based on the fluctuation of the frequency can be obtained. Disturbance can be minimized.

Next, frequency control by the count circuit 118 and the registers 121 and 122 will be described. Note that, as described above, when the frequency of a signal that will be reproduced from the magnetic tape 1 changes due to a search or the like, the value of the registers 121 and 122 is changed to change the V.
It is used to change the center frequency of the CO 106.

As described above, in the Ttr period, the count circuit 118 counts the clock output from the VCO 106 and outputs the count value at the timing when the timing signal Ttr is input. The register 12 supplied by the subtractor 119 via the switch 123
1,122 outputs are subtracted. The output of the subtractor 119 is averaged by the integrator 111 via the coefficient unit 120 and the subtractor 110, and is output to the VCO 106 via the adder 104 to form a feedback loop. That is, the feedback loop performs automatic control of the oscillation frequency of the VCO 106, so-called AFC operation.

In this embodiment, the value to be written into the register is changed according to the two heads having different azimuths as described above, and the value is selectively supplied to the subtractor 119 in accordance with the timing at which each head traces the tape. With the supply, the center frequency of the VCO 106 can be automatically controlled to a frequency corresponding to each head in consideration of the azimuth angle.

Here, the gain of the coefficient unit 120 is set so that the same gain is obtained between the start and the goal when the exit of the loop filter 103 is started and the subtractor 110 is the goal. It is possible to prevent the influence of the phase variation and the frequency variation from affecting the integrator 111.

That is, the gain of the path from the loop filter 103 to the adder 104 to the D / A converter 105 to the VCO 106, the count circuit 118, the subtractor 119, and the coefficient unit 120 is equal to the gain of the path from the loop filter 103 to the LPF 108 to the register 109. Set to be equal to the gain.

As described above, in the present embodiment, the phase comparison circuit 102
~ Loop filter 103 ~ Adder 104 ~ VCO 106
The PLL is configured to perform a normal phase control to obtain a clock, and operate a feedback loop of the LPF 108, the register 109, the integrator 111, the adder 104, and the VCO 106 at the timing of each clock Ttr, thereby forming a loop filter. The output tendency of the loop filter 103 is detected, and the loop filter 10 based on the phase error between Ttr
By compensating for the deviation of the output voltage (input voltage of the VCO 106), the PLL loop can always be maintained at the center of the lock range. Therefore, it is possible to prevent the PLL from easily coming off in response to a change in the oscillation frequency of the VCO 106.

The VCO 106 is controlled by the counter 118.
Is counted, and the output of the registers 121 and 122 is subtracted to detect an error in the oscillation frequency of the VCO 106 during the period Ttr.
The oscillation frequency of the VCO 106 is controlled by controlling the oscillation frequency of the VCO 106 by integrating the output subtracted from the output of No. 3 and calculating the average value of the frequency error, thereby preventing the oscillation frequency of the VCO from changing due to a temperature change or a temporal change. it can.

Further, as described above, the register for setting the oscillation target frequency and the register for integration are provided in accordance with the azimuth of the head. Is P
It is possible to generate an appropriate clock according to the difference in the frequency of the reproduction signal between the heads without deviating from the LL lock range.

In this embodiment, the output of the loop filter 103 is averaged by the LPF 108 and integrated by the integrator 111 to detect a tendency in the output of the loop filter 103. Can be detected by counting up by an up-down counter, and another method can be used.

Next, as a second embodiment of the present invention, Ttr
A case in which the operation performed by the clock of FIG.

FIG. 9 is a diagram showing a configuration of a clock generation circuit as a second embodiment of the present invention.

In FIG. 9, the output of the LPF 108 is output to the input port of the microcomputer 202.
The output of the CO 106 is divided by the prescaler 201 and output to the built-in counter of the microcomputer 202. In this case, the counter can be externally mounted, but the number of components can be further reduced by using a microcomputer with a built-in counter.

Here, the operation of the microcomputer 202 will be described with reference to the flowchart of FIG. Note that registers A and B in FIG. 9 have the same functions as registers 121 and 122 in FIG. 7, respectively, and registers C and D have the same functions as registers 115 and 116, respectively.

First, Ttr is input from the timing generation circuit 124 at the timing of the break of the envelope.
The operation of the microcomputer 202 starts when tr is input.
When Ttr is input, first, the value of the counter is read (step S1), and the azimuth of the head that is currently reproducing the signal is determined by the SWP supplied from the timing generation circuit 124.
(Step S2). Then, the value of the register A is subtracted from the count value for the plus azimuth head, ie, the head 3b (step S3), and the value of the register B is subtracted from the count value for the minus azimuth head, ie, the head 3a. (Step S
4). Next, a coefficient corresponding to the coefficient unit 120 in FIG. 7 is multiplied (step S5), further multiplied by -1 (step S6), and a loop filter output also output from the LPF 109 at the timing of Ttr is added (step S5).
7).

Then, as in step S2, the azimuth of the head is checked (step S8). In the case of plus azimuth, this value and the value of register C are added (step S6), and the minus azimuth is added. In this case, the value of the register D is added (step S10).

Then, it is determined whether or not the result of addition exceeds the limit range (step S11). If the result exceeds the limit range, the result is replaced with the limit value and stored in registers C and D (steps S12, S13 and S14). , S1
5, S16), and outputs this limit value.

If the value does not exceed the limit value, the value is stored in the register A and output (steps S13, S14, S15, S16).

As described above, in this embodiment, Ttr
Since the microcomputer is configured to compensate for the bias of the output voltage of the loop filter 103 due to the phase error between the components, the number of components can be further reduced.

Since the operation of compensating the bias of the input voltage of the VCO 106 due to the phase error between Ttr as described above has a low operation speed of 300 Hz, the operation is performed during the idle time of other operations of the microcomputer. As a result, the number of parts is hardly increased.

In the digital VTR shown in FIG. 1, the processing of PR (1, 0, -1) is performed after A / D conversion. However, the present invention is not limited to this. Alternatively, it may be performed together with the equalization processing in the reproduction equalization circuit.

In the above-described embodiment, an apparatus for reproducing a signal by alternately tracing a tape by two heads having different azimuth angles mounted on a drum with a phase difference of 180 ° has been described. In addition to the simple configuration, two heads having different azimuth angles are provided close to each other,
A digital VTR that records and reproduces a signal by simultaneously tracing a tape with these two heads is known.

Hereinafter, a case where the present invention is applied to such a VTR will be described.

FIG. 11 is a block diagram showing the configuration of the present embodiment. The same components as those in FIG. 1 are denoted by the same reference numerals.

In FIG. 11, the drum 2 is provided with heads 3a, 3b and 3c, 3d having different azimuth angles close to each other. The heads 3a, 3b
And 3c, 3d are arranged with a phase difference of 180 ° from each other. The heads 3c and 3d have the same azimuth angle as the heads 3a and 3b, respectively.

The signals reproduced by the heads 3a and 3c are supplied to an amplifier 4a via a switch SW1 and amplified, and then subjected to an equalization process by a reproduction equalization circuit 5a. The A / D converter 6a uses the clock from the clock generation circuit 14 to convert it again into a digital signal of one sample and a plurality of bits, and supplies the digital signal to the clock generation circuit 14, the delay circuit 7a, and the subtractor 8a.

On the other hand, the signals reproduced by the heads 3b and 3d are supplied to the amplifier 4b via the switch SW2, amplified, and then subjected to equalization by the reproduction equalizing circuit 5b. The A / D converter 6b uses the clock from the clock generation circuit 14 to convert it again into a digital signal of one sample and a plurality of bits, and supplies the digital signal to the clock generation circuit 14, the delay circuit 7b, and the subtractor 8b.

The reproduction equalizing circuit 4a to the amplifiers 5a to 5A
The system of the / D converter 6a to the delay circuit 7a to the subtractor 8a and the system of the reproduction equalizer 4b to the amplifier 5b to the A / D converter 6b to the delay circuit 7b to the subtractor 8b have different azimuth angles. This is a system that processes signals reproduced from the head, and can be designed with optimal equalization characteristics and signal processing characteristics according to each azimuth head.

The PR (1,1) output from the delay circuit 8b
The signals having the (0, -1) characteristic are restored by the Viterbi decoding circuits 9a, 9b to signals of 1, 0, that is, signals of 1 bit per sample.

Here, the output of the Viterbi decoding circuit 9b is delayed by the delay circuit 17 by a time corresponding to the time for reproducing one track, and is output to the switch SW3.

The switch SW3 switches according to the SWP output from the head switching signal generation circuit 15, and selectively outputs the output signal from the Viterbi decoding circuit 9a and the output signal from the delay circuit 17 to the ECC circuit 10. I do.

The following operation is the same as in the above-described embodiment.

Next, the clock generation circuit 1 shown in FIG.
4 will be described.

In this embodiment, in order to generate a clock synchronized with the signal reproduced from the head of each azimuth, two clock generation circuits shown in FIG. 7 are provided for each azimuth.

That is, in FIG. 12, the overall operation of each system is substantially the same as in FIG. 7, but in FIG. 12, the signal output from the A / D converter 6a is input to the terminal 101, A clock phase-synchronized with the reproduction signal from the minus azimuth head is output from a terminal 107. Also, a signal output from the A / D converter 6b is input to the terminal 101 ', and a clock phase-synchronized with the reproduction signal from the plus azimuth head is output from the terminal 107'.

Therefore, in FIG.
21 and 122 are provided in separate systems.
And 116 were provided in separate systems.

That is, in FIG. 12, the register rewriting circuit 126 writes a value corresponding to the change in frequency with respect to the reproduction speed of the reproduction signal by the minus azimuth head, as shown in FIG. The register 122 is written with a value corresponding to a change in frequency with respect to the reproduction speed of the reproduction signal by the plus azimuth head.

At this time, the timing generation circuit 124
After that, the signal shown in FIG. 8E is output to the register 115, and the output signal of the limiter 113 is written into the register 115 at this timing. The signal shown in FIG. 8D is output to the register 116, and the register 116 outputs the limiter 1 at this timing.
The output signal of 13 'is written.

As described above, in this embodiment, a plurality of clock generation circuits are provided for heads of different azimuths, and a register for setting an oscillation target frequency and a register for integration in each system as described above. Even when the tape is traced by a plurality of heads having different azimuth angles at the same time to reproduce the signal, the frequency of the reproduction clock may be locked due to the difference in the azimuth angle during a search. An appropriate clock corresponding to the difference in the frequency of the reproduced signal between the heads can be generated without deviating from the range.

In the above-described embodiment, the reproduction signal and the VC
Although a digital phase comparison circuit is used to detect the phase error with the output of O, any means for detecting the phase error between the reproduced signal and the output of the VCO may be used.

Further, in the above-described embodiment, the case where the present invention is applied to a digital VTR has been described. However, the present invention is not limited to this, and a system for transmitting and recording / reproducing a digital signal, for example, radio waves or optical signals The present invention can also be applied to communication by optical communication and the like, an optical disk, and the like, and has the same function and effect.

[0103]

As is apparent from the above description, according to the present invention, when the clock generation operation is controlled using the result of comparing the count value of the clock with the value of the reference data, the reference data of the reference data is controlled. Since the value is set according to the azimuth angle of the head, the frequency of the reproduction clock does not deviate from the PLL lock range due to the difference in the azimuth angle during a search or the like. An appropriate clock according to the difference can be generated.

According to another aspect of the present invention, the oscillation frequency error of the output clock is detected in accordance with the azimuth angle of the head, and the detection result of the oscillation frequency error is added to the output of the loop filter for integration. Since the result and the output of the loop filter are added and input to the voltage-controlled oscillating means, the oscillation frequency of the voltage-controlled oscillating means can be kept stable without being affected by a temperature change or a change over time.

Further, it is possible to always keep the PLL loop at the center of the lock range, and to generate a clock having a frequency corresponding to the reproduced signal from each head regardless of the difference in the azimuth angle of the head.

[0106]

[0107]

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a digital VTR as an embodiment of the present invention.

FIG. 2 is a diagram illustrating a relationship between a track and a head according to the embodiment of the present invention.

FIG. 3 is a diagram showing a relationship between a track and a head at the time of a search in the embodiment of the present invention.

FIG. 4 is a diagram showing a relationship between recording data and a head during normal reproduction.

FIG. 5 is a diagram showing a relationship between recording data and a head during a search.

FIG. 6 is a diagram illustrating a change in frequency of a reproduction signal with respect to a tape transport speed.

FIG. 7 is a diagram showing a configuration of a clock generation circuit in FIG. 1;

FIG. 8 is a timing chart for explaining the operation of the circuit of FIG. 7;

FIG. 9 is a diagram illustrating another configuration of the clock generation circuit in FIG. 1;

FIG. 10 is a flowchart for explaining the operation of the circuit shown in FIG. 9;

FIG. 11 is a block diagram showing another configuration of the digital VTR as an embodiment of the present invention.

FIG. 12 is a diagram showing a configuration of a clock generation circuit of FIG. 11;

FIG. 13 is a diagram showing a configuration of a conventional PLL circuit.

[Explanation of symbols]

 Reference Signs List 102 Phase comparison circuit 103 Loop filter 106 Voltage controlled oscillation circuit 118 Count circuit 111 Integrator 125 Speed setting circuit 126 Register rewriting circuit 202 Microcomputer

Claims (13)

(57) [Claims] A reproducing means for reproducing a signal from a recording medium by a plurality of heads having different azimuth angles from each other; a generating means for generating a clock phase-synchronized with the signal reproduced by the reproducing means; Counting means for counting the counted clock; comparing means for comparing the count value of the counting means with the value of the reference data; control means for controlling the generating operation of the generating means using the output of the comparing means; A reproducing device, comprising: setting means for setting a value of the reference data according to an azimuth angle of the head. 2. The apparatus according to claim 1, wherein the generating unit detects a phase difference between the clock and the signal reproduced by the reproducing unit, a loop filter receiving an output of the phase difference detecting unit, and the loop. 2. The reproducing apparatus according to claim 1, further comprising an oscillation unit to which an output of the filter is supplied and which outputs the clock. 3. The control means includes: first adding means for adding an output of the comparing means and an output of the loop filter; integrating means for integrating an output of the first adding means;
3. The reproducing apparatus according to claim 2, further comprising second adding means for adding an output of the loop filter and an output of the integrating means, and outputting a result of the addition to the oscillating means. 4. The integration means holds a plurality of holding means provided respectively corresponding to the azimuth angles, each holding an output of the first adding means, and an output of the plurality of holding means and the first holding means. 4. The reproducing apparatus according to claim 3, further comprising third adding means for adding the output of the adding means and outputting the result to the second adding means. 5. The reproducing apparatus according to claim 1, wherein the setting unit changes the value of the reference data between a normal reproduction mode and a high-speed reproduction mode. 6. A reproducing means for reproducing a signal from a recording medium by a plurality of heads having different azimuth angles from each other, a generating means for generating a clock phase-synchronized with the reproduced signal, a frequency of the clock generated by the generating means Frequency detecting means for detecting an error between the frequency and the target frequency, and controlling the generating operation of the generating means based on the error detection result; and controlling the detecting operation of the frequency detecting means according to the azimuth angle of the head. A playback device comprising: 7. The apparatus according to claim 6, wherein said frequency detecting means has an integrating means for integrating the detection result, and controls a generating operation of said generating means in accordance with an output of said integrating means. Playback device. 8. The frequency detecting means includes a counter for counting a clock generated by the generating means for a predetermined period, a register for holding a comparative value, and a comparing means for comparing the comparative value with the count value of the counter. 7. The reproducing apparatus according to claim 6, comprising: 9. The reproducing apparatus according to claim 8, wherein the counter counts the number of clocks during a period when the head traces one track on the recording medium. 10. The apparatus according to claim 8, wherein the counter is reset in response to a timing signal generated according to a switching signal for switching the plurality of heads.
The playback device according to any one of the preceding claims. 11. A conversion means for sampling a signal reproduced by said reproduction means in accordance with a clock generated by said generation means and converting the signal into a digital signal of a plurality of bits per sample, and a digital signal output from said conversion means. 7. The reproducing apparatus according to claim 6, further comprising a restoring means for restoring the digital signal into one bit per sample. 12. A signal is reproduced from a recording medium by a plurality of heads having different azimuth angles from each other, and a phase difference between a voltage controlled oscillating means, an output clock of the voltage controlled oscillating means and the reproduced signal is detected. An apparatus for generating a clock phase-synchronized with the reproduced signal by a PLL circuit including a phase difference detecting means and a loop filter, wherein an oscillation of an output clock of the voltage controlled oscillating means according to an azimuth angle of the head. Detecting a frequency error, adding the detection result of the oscillation frequency error to the output of the loop filter and integrating the result, adding the integration result to the output of the loop filter, and inputting the result to the voltage controlled oscillator. A reproducing apparatus characterized by the above-mentioned. 13. The reproducing apparatus according to claim 12, wherein the detecting operation of the oscillation frequency error and the integrating operation are performed by a microcomputer.