JPH07262704A - Digital data reproducing device - Google Patents

Abstract

PURPOSE:To automate adjustment of a PLL circuit and to suppress the occurrence of data errors to the min. by changing a VCO control voltage of the PLL circuit while utilizing error information. CONSTITUTION:Reproducing output data and E.E data are selected by a switch 5, and rise and fall information of the data is detected in an edge detecting circuit 26, and is sent to a phase comparator 27. A phase difference between edge information and a VCO output signal is detected by the comparator 27 to generate a phase error voltage, which is then sent via an LPF 24 to a voltage adder 23 to be the VCO control voltage. An error information signal 12 is inputted to a VCO control voltage controller 11, and is sent as VCO control data to a conversion table 21. Then, the VCO control voltage is set to a central voltage of a VCO control voltage range corresponding to a pull-in range from a central frequency of the PLL circuit, and the automatic adjustment of the PLL circuit is carried out.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data reproducing method for a data recorder, and more particularly to a reproduced clock extracting circuit, especially a PLL circuit.

[0002]

2. Description of the Related Art As a device for writing digital data on a helical track, for example, the Institute of Television Engineers Technical Report ITEJ, Technical Report is available.
Vol. 11 No. 24 pp. 13-18. VR '
87-30 (Oct, 1987) as described in D2.
Format digital video tape recorders are known. In the D2 format, a PLL circuit is adopted as a reproduction clock extraction circuit required for data discrimination.

[0003]

However, since the PLL circuit has a wide frequency follow-up range of the VCO and operates at a high frequency, it is greatly affected by the variation of the parts, which requires a large number of adjustment volumes. I was there. Therefore, the cost was increased. Further, since there is no means for automatically adjusting the phase relationship between the clock signal and the data in the data strobe circuit, the occurrence of data error in the data strobe circuit due to circuit variation can be minimized. There wasn't.

[0004]

In order to achieve the above object, automatic adjustment of the PLL circuit has been desired. In order to perform this automatic adjustment, the present invention uses the error information PLL
The pull-in range from the center frequency of the PLL circuit is measured by changing the VCO control voltage of the PLL circuit by using it as a signal for determining the operating state of the circuit. After that, the VCO control voltage is set to the center voltage of the VCO control voltage range corresponding to the pull-in range to automatically adjust the PLL circuit. The pull-in range referred to here is the range in which the VCO follows the input data when the input data is input to the PLL circuit from the state where there is no input data when a certain control voltage is applied to the VCO and the phase is synchronized. Shows. A phase difference detection circuit may be used instead of the error information. When performing the above means, the data input signal may reproduce the data recorded on the tape, or the recorded data after modulation may be used as it is without being recorded on the tape (EE system). Good. Further, the error information is used to automatically adjust the phase relationship between the clock signal synchronized with the data strobe circuit and the input data so that the number of data errors is minimized.

[0005]

With the above structure, the adjustment of the PLL circuit can be automated, the cost can be reduced, and the optimum VC can be obtained.
O control voltage can be obtained. Further, since the phase relationship between the clock and the data can be determined in the data strobe circuit while detecting the data error, it is possible to minimize the deterioration of the error rate in the data strobe circuit.

[0006]

EXAMPLES Examples of the present invention will be described below. Figure 1
FIG. 1 is a block diagram showing a configuration of a reproducing system of a digital data reproducing device, 1 is a recording data input terminal, 2 is a reproducing head output input terminal, 3 is a reproducing preamplifier, 4 is a reproducing waveform equalizing circuit, and 5 is a switching A switch, 6 is a data discrimination circuit, 7 is a demodulation circuit, 8 is a PLL circuit, and 9 and 12 are
Error information signal, 10 is an error correction circuit, 11 is a VCO
A control voltage controller, 13 is a speed information signal input terminal, 14 is a changeover switch control signal input terminal, and 15 is a digital data output terminal. The reproduction data input from the reproduction head output input terminal 2 is amplified by the reproduction preamplifier circuit 3, waveform-shaped by the reproduction waveform equalization circuit 4, and reaches the changeover switch 5. At the same time, digital data that is input from the recording data input terminal 1 and does not pass through the tape head system (usually data that is input to the recording circuit; hereinafter abbreviated as EE data) is also input to the switching switch 5. To be done. The changeover switch 5 to which these data are input is a changeover switch control signal input terminal 1
4, one of the above signals is selected by the input switch control signal, and the signal is sent to the subsequent circuit. The PLL circuit extracts a clock signal from the transmitted signal. Next, using the extracted clock signal, the data discrimination circuit discriminates data and discriminates whether the input data is 0 or 1. The determined data is demodulated by the demodulation circuit 7, the error correction circuit 10 performs error detection and error correction, and is output from the digital data output terminal 15. The error correction circuit outputs the error information signals 9 and 12 that discriminate the data error to the data strobe circuit 6 and the VCO control voltage controller 11. VCO control voltage controller 11
Controls the PLL circuit using the speed information signal input from the speed information signal input terminal 13, that is, the data transfer speed information and the information of the error information signal 12. Thus, by using the control signal, P
It is configured to allow automatic adjustment of the LL circuit. Hereinafter, the control means will be described in detail.

FIG. 2 is a diagram showing the configuration of the PLL circuit and its control circuit. 20 is an error information signal input terminal, 21 is a data conversion table, 22 is a D / A conversion circuit, and 23 is a voltage adder. , 24 are low-pass filters, 2
Reference numeral 5 is a VCO, 26 is an edge detection circuit, 27 is a phase comparator, and 28 is a reproduction equalization circuit output data input terminal. The reproduction output data input from the reproduction equalization circuit output data input terminal 28 reaches the changeover switch 5. At the same time, the E / E data input from the recording data input terminal 1 reaches the changeover switch 5. The two types of data input to the changeover switch 5 are selected by the switch control signal input from the changeover switch control signal input terminal 14. The edge detection circuit 26 detects rising and falling information (hereinafter abbreviated as edge information) of the selected input data, and reaches the phase comparator 27. The phase comparator 27 detects a phase difference between the edge information and the VCO output signal, and generates a phase error voltage according to the phase shift. The signal is sent to the voltage adder 23 through the low pass filter 24, and is input to the VCO as the control voltage of the VCO. That is, VCO 25,
The phase comparator 27 and the low pass filter 24 form a basic part of the PLL circuit. The PLL circuit supplies the voltage adder 23 with an offset voltage in addition to the phase error voltage output from the phase comparator, thereby providing a VCO.
The configuration is such that the oscillation frequency can be changed. With the above configuration, it is possible to absorb the variation in the control voltage characteristic due to the variation in the components of the VCO and the variation in the phase error voltage due to the variation in the components of the phase comparator. Next, the means for applying the offset voltage will be described. The speed information signal input from the speed information signal input terminal 13 is converted by the conversion table 21 into specific digital data determined corresponding to the speed information signal. The converted digital data is converted into an analog voltage by the D / A conversion circuit 22 and input to the voltage adder 23. With such a configuration, the PLL circuit is operated at various speeds. Further, the error information signal 12 input to the error information signal input terminal 20 is V
The CO control voltage controller 11 inputs the VCO control data to the conversion table 21. That is, in the steady state, the digital data on the conversion table is determined only by the speed information signal, but when automatically adjusting the PLL circuit, the VCO control data output from the VCO control voltage controller 11 is used. In this configuration, the digital data in the conversion table 21 is changed. By configuring as described above and adjusting the offset voltage of the VCO, it becomes possible to automatically adjust the PLL circuit in terms of circuit configuration. The offset voltage determined as a result of automatic adjustment is VC
It is stored in the memory in the O control voltage controller 11,
After the automatic adjustment, VCO control data is output to the conversion table as needed. Next, referring to FIG. 4, FIG. 5, and FIG.
A method of automatically adjusting the LL circuit will be described. Figure 5
FIG. 4 is a diagram showing a part of a recording data format of a digital data reproducing device, (A) is a data recording format, (B) is an error information signal, 40 is synchronous data,
41 is address data, 42 and 44 are recording data, 4
3 and 45 are error check data, and 46 and 47 are error flags. That is, (A) is an example of a data aggregation unit in the recording format of the data to be recorded,
It is called a sync block. The sync block shown in the above example is composed of an aggregate of two sets of data composed of data and its inspection data. Here, there are two sets, a set of data 42 and error check data 43 and a set of data 44 and error check data 45. One of the error flags 46 and 47 shown in (B) is generated for each data aggregate, and two are generated for each sync block. That is, this error flag is generated when one of the two sets of data has an error, indicating that there is at least one data error in this set. Therefore, even if most of the data in the aggregate is in error, only one error flag is generated. On the other hand, when the PLL circuit is not operating normally, that is, the input data and V
If the CO output signal is not phase-synchronized, most of the data in the aggregate will be in error, and as a result the error flag will be output reliably. Therefore, it is possible to determine whether the PLL circuit is operating normally by using the error flag. FIG. 4 is a diagram showing the pull-in range and the hold range of the PLL circuit, where 31 is the hold range, 32 is the pull-in range, and 3 is the hold range.
3 indicates the data transfer rate. During reproduction, the PLL circuit operates to generate a clock signal synchronized with the input signal.
The VCO control voltage range that can be in the synchronous state from the non-synchronized state is the pull-in range 32 in this case, and the VCO control voltage range from the synchronous state to the asynchronous state is the holding range 31. Therefore, each data transfer rate 3
If the pull-in range for each 3 can be determined, the VCO control voltage range can be determined, and the PLL circuit can be operated stably. Here, the error flag information shown in FIG. 5 is used to measure the pull-in range. That is, whether or not the operation is normal is automatically measured by the error flag information shown in FIG. 4 and the control voltage applied to the VCO is controlled to determine the digital data output from the VCO control voltage controller shown in FIG. However, the PLL circuit is controlled. By configuring as described above, VC
This makes it possible to determine the O control voltage and keep the PLL circuit within the pull-in range. Next, the operation of the VCO control voltage controller will be described with reference to FIG. First, the initial data i is output to the conversion table 21 as VCO control data. In this state, the PLL circuit is operated to determine whether or not it is in the synchronous state by the error flag having the information of the data error. If the error flag is detected in most sync blocks, ie all errors,
The initial data i is increased and the same operation is continued. If the error flag is not in the all error state, the data i is stored in the memory as described above. After that, if the data i is within the operable range N, the input signal is once switched in order to cancel the synchronous state, the asynchronous state is established, the data i is increased, and the same operation is continued. Switching the input signal is P
This is because, in the LL circuit, the holding range is usually larger than the pull-in range as shown in FIG. Therefore, the means for switching the input signal to make the once-synchronized state asynchronous becomes effective. This can be realized by switching the switch 5 shown in FIG. Continue the above operation, i is the operable range N of i
If it exceeds, the range of i input to the memory is calculated and the pull-in range is determined. After that, to obtain a more stable state, the value of i at the center of the pulling range is calculated,
Output to the conversion table. This operation is performed for each data transfer speed, the digital data to be output to the conversion table is determined for each speed, and the PLL circuit operates stably. As described above, since the operating state of the PLL can be determined by using the error information, it is possible to automatically respond to the change in the VCO control voltage due to the component variation of the PLL circuit. When performing this automatic adjustment, it is also possible to use the record data, that is, the record data before being recorded on the tape, as the input data. In this case, it is not necessary to play the tape. Alternatively, data may be input from the outside.

A second embodiment will be described with reference to FIG. FIG. 3 is a block diagram showing the configuration of the PLL circuit using the phase difference detection circuit, and 30 shows the phase difference detection circuit.
In this embodiment, the phase difference detection circuit 30 is used instead of the error flag to determine the operating state of the PLL circuit. The phase difference detection circuit 30 has a VC
The O output signal, the edge information after the edge detection, and the phase difference are detected for a certain period. If in the synchronized state, the phase relationship between the input signal and the clock signal is in a constant state. Therefore, by detecting the phase relationship, the operation state of the PLL circuit can be known and the pull-in range can be determined.

FIG. 7 is a diagram showing a circuit configuration for changing the timings of the data and clock signals at the data strobe point.
Is an edge detection circuit, 52 is a data delay circuit, 53
Is a data strobe circuit, 54 is a clock delay circuit, and 55 is a controller. Input data input terminal 5
The input data input from 0 detects the edge data of the input signal by the edge detection circuit 51 and is input to the PLL circuit to generate a clock signal synchronized with the input signal.
The generated clock signal reaches the clock delay circuit 54 and is input to the data strobe circuit 53. On the other hand, the input data passes through the data delay circuit 52 and reaches the data strobe circuit 53. The data strobe circuit 53 performs data discrimination for determining whether data is 0 or 1 using a clock signal synchronized with the data. After that, the data is demodulated by the demodulation circuit 7, the error data is detected and corrected by the error correction circuit 10, and the data is output from the data output terminal 15. The error information signal generated by the error detection is sent to the controller 55. Therefore, the error rate is calculated and the clock delay circuit 54 and the data delay circuit 52 are controlled. This control signal serves to change the delay time of the clock delay circuit 54 or the data delay circuit 52. As a result, the timing of the data and clock in the data strobe circuit 53 can be varied, and the occurrence of data error can be suppressed to the minimum. At this time, the delay time of the data delay circuit or the delay time of the clock delay circuit is determined by reproducing the reference tape. The determined data is stored in the controller and the delay time is adjusted to the determined time at any time. With this configuration, the timing of data and clock can be automatically optimized.

[0010]

According to the present invention, the pull-in range of the PLL circuit can be detected by controlling the VCO control voltage using the data error information or the phase difference detection circuit. As a result, it is possible to realize automatic adjustment that absorbs component variations of the PLL circuit. Further, since the data strobe circuit is configured to determine the timing of the data and the clock while monitoring the error rate, the timing of the data and the clock can be optimized, and the deterioration of the error rate at the data strobe point can be suppressed.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a reproduction system of a digital data reproduction device.

FIG. 2 is a block diagram showing a configuration of a PLL circuit and its control circuit.

FIG. 3 is a block diagram showing a configuration of a PLL circuit using a phase difference detection circuit.

FIG. 4 is a diagram showing a pull-in range and a holding range of a PLL circuit.

FIG. 5 is a diagram showing a part of a recording data format of the digital data reproducing device.

FIG. 6 is a diagram illustrating an operation of a VCO control voltage controller.

FIG. 7 is a diagram showing a circuit configuration for changing data and clock timings at a data strobe point.

[Explanation of symbols]

 6 ... Data strobe circuit, 8 ... PLL circuit, 11 ... VCO control voltage controller, 30 ... Phase difference detection circuit, 32 ... Pull-in range, 46, 47 ... Error flag.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Koji Fujita, 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa, Ltd. Inside the Video Media Research Laboratories, Hitachi, Ltd. Factory Storage Systems Division

Claims (7)

[Claims] 1. A means for amplifying reproduction data reproduced by a reproduction head, a means for waveform equalizing the amplified output data, a means for detecting an edge portion of the output data after the waveform equalization and the edge signal. And a means for extracting data from the reproduction equalizer output data by using the synchronized clock signal, a means for demodulating the data, and a means for error correcting the demodulated signal. In the digital data reproducing device, the means for extracting the clock signal is a PLL (phas
e locked loop) circuit,
Allowable range of VCO (voltage controlled oscillator) control voltage error in the circuit, that is, VCO of the PLL circuit
The digital data reproducing apparatus is provided with means for detecting a control voltage range that is phase-locked with the input data and means for correcting the control voltage error. 2. The digital data reproducing / reproducing apparatus according to claim 1, wherein the allowable range of the VCO control voltage error in the PLL circuit is a pull-in range of the PLL circuit. 3. The digital data according to claim 1, wherein the allowable range of the VCO control voltage error in the PLL circuit is judged and determined by an error information signal output from the error correcting means. Playback device. 4. The allowable range of the VCO control voltage error in the PLL circuit is judged by detecting the phase difference between the VCO output signal and the output data of the edge detection circuit for a certain period of time. Digital data reproduction device. 5. When the tape speed changes, the allowable range of the VCO control voltage error in the PLL circuit is determined according to each tape speed, and the allowable range of the VCO control voltage error is stored in a memory. The digital data reproducing device according to claim 1, wherein 6. The digital data reproducing apparatus according to claim 1, wherein the VCO control voltage in the PLL circuit is determined to be a voltage at the center of an allowable range of a VCO control voltage error in the PLL circuit. 7. A means for amplifying reproduced data reproduced by a reproducing head, a means for waveform equalizing the amplified output data, a means for detecting an edge portion of the output data after the waveform equalization, and the edge signal. And a means for extracting data from the reproduction equalizer output data by using the synchronized clock signal, a means for demodulating the data, and a means for error correcting the demodulated signal. In the digital data reproducing device, the means for extracting the clock signal has means for changing the phase relationship between the clock and the data when the data is extracted by the means for extracting the data by the extracted clock signal, Recording / reproducing apparatus characterized in that it is determined by the error information signal output from the error correcting means.