JPH06195875A - Reproducing device - Google Patents

Abstract

PURPOSE:To prohibit miswriting a memory caused by erroneous ID detection. CONSTITUTION:An ID detecting circuit 42 outputs a state signal 42b indicating an ID detecting state besides an ID detecting signal 42a. A continuous detecting circuit 44 detects whether good ID detection is continuously performed more than (n) times until now or not, with the signal 42b. When ID detection is continuously performed (n) times in accordance with the detected result of the continuous detecting circuit 44, a request mask circuit 46 passes a request signal for writing a memory generated by a timing generation circuit 24, and when ID detection is performed less than (n) times, the circuit 46 masks it. In order to cancel a delay time caused by the continuous detecting circuit 44, counted values of a block counter 28 and a high order counter 30 are applied to a latch circuit 38 via a (n) sync. block delay circuit 48, and a reproducing code train inputted to an input terminal 20 is applied to the latch circuit 38 via the (n) sync. block delay circuit 48.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reproducing apparatus, for example, a reproducing apparatus in a digital data transmission system such as an image transmission system.

[0002]

2. Description of the Related Art In an image recording system for digitally recording an image signal on a magnetic tape, an image transmission system using a digital telephone line, etc., a transmitting device (or a recording device)
Divides the image data into blocks by a predetermined number, adds a synchronization code (hereinafter referred to as SYNC), an identification code (hereinafter referred to as ID), and a parity for error correction in block units, and performs a predetermined modulation. After that, it is sent to the transmission path.
On the receiving device (or reproducing device) side, the timing of each data separation is determined by the ID. Then, the arrangement of the received (or reproduced) data is determined by the ID, the data is written in the corresponding address of the data memory, and a predetermined reproducing process is performed.

Consider a digital image recording / reproducing apparatus as an example. The format of one sync block is shown in FIG. 10
Is SYNC, and 12 is a high-order address of data I
D and 14 are ID 12 error detection codes, 16 is image data, and 18 is image data 16 error detection and correction codes.

In the magnetic recording / reproducing system, dust or the like adheres to the magnetic head, resulting in dropout of the output of the magnetic head. At the time of reproduction, when the analog recording / reproducing apparatus detects this dropout, it performs dropout compensation by substituting with the signal of the horizontal line immediately before having a correlation, but the digital recording / reproducing apparatus prohibits writing to the data memory. Then, the dropped out bad data is invalidated, and the dropout is compensated by the address operation of the data memory.

FIG. 3 shows a block diagram of the basic structure of a conventional example. The reproduced sync blocks having the format shown in FIG. 2 are sequentially input to the input terminal 20. The synchronization detection circuit 22 determines whether the code string input to the input terminal 20 is SYN
C is detected, and the synchronization detection signal 22a is applied to the timing generation circuit 24. The timing generation circuit 24 supplies a timing signal (hereinafter abbreviated as an IDT signal) 24a that defines the ID detection timing of the ID detection circuit 32 to the ID detection circuit 32 according to the synchronization detection signal 22a. The timing signal generation circuit 24 internally counts a symbol counter 26 that counts the number of symbols (for example, 207 symbols) in one sync block, a block counter 28 that counts the number of sync blocks, and channels, fields, and frames. A high-order counter 30 is provided. The symbol counter 26 is initialized by the sync detection signal 22a from the sync detection circuit 22.

The ID detection circuit 32 detects an ID code from the reproduction code string of the input terminal 20 according to the IDT signal 24a, and outputs an ID load timing signal (hereinafter abbreviated as IDL signal) 32a in the timing signal generation circuit 24. Apply to block counter 28. Block counter 2
Reference numeral 8 reads ID information (block number and line number) from the reproduction code string of the input terminal 20 according to the IDL signal 32a. The timing signal generation circuit 24 also outputs the counter values of the symbol counter 26, the block counter 28, and the high-order counter 30, which operate on the basis of the synchronization detection signal 22a and the IDL signal 32a, as the memory address signal 24b, and A write request (WRQT) signal 24c for requesting write permission is output.

The request mask circuit 34 uses a dropout (DOS) signal from a dropout detection circuit (not shown) to cause the WRQT signal 24 when a dropout occurs.
c is masked, and when no dropout occurs, it is passed and applied to the memory circuit 40. Memory circuit 4
0 outputs a write enable (WACK) signal after arbitration processing inside the memory circuit 40 in response to the write request signal from the request mask circuit 34. Data latch circuit 36
The address latch circuit 38 is enabled by the WACK signal, and latches the data portion of the reproduction code string at the input terminal 20 and the address output from the counters 26, 28, 30 respectively. The data held by the latch circuit 36 is written at a predetermined timing in the storage location of the memory circuit 40 designated by the address held by the latch circuit 38.

[0008]

In the above-mentioned conventional example, the maskability of the write request signal 24c is controlled only by the presence or absence of dropout. Therefore, in the conventional example,
When SYNC or ID is erroneously detected, the erroneous detection causes writing to an address generated by the counters 26, 28, 30 and destroys the data stored in the memory circuit 40. There is.

An object of the present invention is to provide a reproducing apparatus which solves such a problem.

[0010]

In a reproducing apparatus according to the present invention, data included in a sync block is designated by an identification code included in the sync block at a timing specified by the sync code included in the sync block. A reproducing device for writing to a memory address, which monitors the detection state of an identification code included in a sync block, and permits the data included in the sync block to be written to the memory when correctly detected n consecutive times. It is characterized in that a control means for controlling is provided.

[0011]

According to the above means, the good ID detection permits the memory write only after n times in succession. Therefore, for example, an erroneous ID signal can be detected due to an erroneous detection of the sync signal, or the ID signal can be detected.
If the signal detection fails, or if the reproduced ID itself has an error, the memory writing is prohibited.
This makes it possible to prevent erroneous reproduction data from being written to the memory and reproduction data from being written to an erroneous portion of the memory.

[0012]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a basic block diagram of an embodiment of the present invention. The same circuit elements as those in FIG. 4 are designated by the same reference numerals. Reference numeral 42 denotes an ID detection circuit, which is an ID detection signal 32.
In addition to the ID detection signal 42a similar to that of a, a detection state signal 42b indicating whether or not the ID detection state is good is output. ID
Whether or not the detection state is good can be determined by the ID CRC. Reference numeral 44 is a continuous detection circuit that detects how many times good ID detection is continuous up to the present time by the detection state signal 42b output from the ID detection circuit 42. Set to (high) and set to L (low) when n times cannot be continued.

Reference numeral 46 denotes an output signal 44 of the continuous detection circuit 44.
A request mask circuit that passes or masks the write request signal 24c in accordance with a. When the output signal 44a is H, the write request signal 24c is passed and the output signal 44a is output.
When L is L, the write request signal 24c is masked.

Reference numeral 48 is an n-sync block delay circuit for delaying the count values of the block counter 28 and the high-order counter 30 by n sync blocks and supplying it to the latch circuit 38. Reference numeral 50 is input to the input terminal 20. Similarly, it is an n sync block delay circuit that delays the reproduced data by n sync blocks and supplies it to the latch circuit 36.

The sync detection circuit 22 detects the sync code SYNC from the reproduction code string of the input terminal 20 and supplies the sync detection signal 22a to the timing signal generation circuit 24. The timing generation circuit 24 follows the synchronization detection signal 22a,
The IDT signal 24a is output to the ID detection circuit 44. In addition, the timing generation circuit 24 uses the synchronization detection signal 22.
It is initialized by a.

The ID detection circuit 42 detects an ID code from the reproduction code string of the input terminal 20 according to the IDT signal 24a, outputs the ID signal 42a to the block counter 28 in the timing signal generation circuit 24, and detects the ID detection state. The signal 42b is output to the continuous detection circuit 44. Continuous detection circuit 4
No. 4 detects how many times good ID detection has been performed in succession up to the present time, and when it is n times in succession, the output signal 44a is set to H level.
Set to (high), and set to L (low) when not continuous n times.

As in the conventional example, the block counter 28
Reads the ID information (block number and line number) from the reproduction code string of the input terminal 20 in accordance with the IDL signal 42a.
The counter value of 6, 28, 30 is used as the memory address signal 2
4b and a write request (WRQT) signal 24c for requesting memory write permission.

The continuous detection circuit 44 outputs the memory output from the block counter 28 and the upper counter 30.
A delay corresponding to n sync blocks occurs between the address and the write request signal 24c. The n-sync block delay circuit 48 absorbs this delay. Similarly, the n-sync block delay circuit 50 is
Playback code and write request signal 24 to be written in
It absorbs the time difference between it and c.

The request mask circuit 46 is a continuous detection circuit 44.
According to the output signal 44a of the above, when the good ID detection is continued n times or more until the present time point, the write request signal 24c of the timing signal generation circuit 24 is passed, and when it is less than n times, it is masked. The detailed operation of the request mask circuit 46 will be described later.

In response to the write request signal from the request mask circuit 46, the memory circuit 40 outputs a write enable (WACK) signal after arbitration processing inside the memory circuit 40. The latch circuits 36 and 38 are enabled by the WACK signal, and the latch circuit 36 causes the data portion (including the error correction code portion) of the reproduction code string at the input terminal 20 to
The latch circuit 38 latches the address from the counters 26, 28, 30 via the n-sync block delay circuit 48. The data held by the latch circuit 36 is written at a predetermined timing in the storage location of the memory circuit 40 designated by the address held by the latch circuit 38.

In the present embodiment, if an erroneous ID signal is detected due to erroneous detection of a sync signal, or if the ID signal detection fails, or if the reproduced ID itself has an error, erroneous reproduction is performed. It is possible to prevent the data from being written in the memory 40 and the reproduction data from being written in a wrong location in the memory 40.

FIG. 4 shows an operation flowchart of the continuous detection circuit 44 and the request mask circuit 46. First, the continuous detection circuit 44 checks whether or not the current ID detection is good and has continued n times (S1, 2). If good ID detection has been performed n times in succession until now, the request mask circuit 4
6 passes the write request signal 24c (S3), and if the current ID detection is defective (S1), or if the current ID detection is good but not continuous n times (S2), the write request signal 24c is sent. Mask (S4).

The functions described in the flowchart shown in FIG. 4 can be easily realized by a combinational logic circuit and software.

The circuit shown in FIG. 1 can be specifically applied to a reproducing circuit of a helical scan type digital video recording / reproducing apparatus. FIG. 5 shows a schematic block diagram of the reproducing circuit. The circuit 60 surrounded by the broken line is exactly the same as the circuit shown in FIG. 62 is a magnetic tape, 64 is a reproducing head, 66 is a reproducing amplifier for amplifying the output of the reproducing head 64, and 68 is a demodulation circuit for demodulating the output of the reproducing amplifier 66 and outputting reproduced data. Reference numeral 70 denotes a D / A converter that converts the reproduction data read from the memory 40 into an analog signal. Although the reproducing head 66 may have a plurality of channels, only one channel is shown here.

Reference numeral 72 is a pinch roller, 74 is a capstan, 76 is a capstan motor for rotating the capstan 74, and 78 is a motor control circuit for controlling the capstan motor 76. As is well known, by rotating the capstan while the magnetic tape 62 is sandwiched between the pinch roller 72 and the capstan 74,
The magnetic tape 62 can be run in a desired direction at a desired speed. That is, in addition to normal reproduction, special reproduction such as slow reproduction and search reproduction can be performed.

FIG. 6 is a plan view of a rotary drum of such a helical scan type digital video recording / reproducing apparatus, and FIG. 7 is a development view of the rotary drum. Reference numeral 80 is a rotary drum, 82A, 82B, 84A and 84B are recording or reproducing magnetic heads, and 86 is a magnetic tape. Head 82
A and 84A are plus azimuth and heads 82B and 84B
Is a minus azimuth, and the heads 82A and 84A are arranged apart from the heads 82B and 84B by a small angle θ in the circumferential direction of the rotary drum.
B is arranged 180 degrees apart from the heads 84A and 84B in the circumferential direction of the rotary drum 80. At the time of recording or reproduction, the pair of heads 82A and 82B and the head 8
Alternately use pairs of 4A and 84B.

FIG. 8 shows a track pattern on the magnetic tape 86 recorded by the head structure shown in FIGS. 6 and 7. When reproducing at twice the tape speed, the magnetic head scans each track as shown by the dotted line. Only the shaded area can be reproduced due to the difference in azimuth. The playback envelope for one channel is shown in FIG.

As described above, when the magnetic tape is run and played back faster than during recording, a portion where the head output becomes extremely small appears and many playback errors occur. Even with the reproduction envelope as shown in FIG. 9, it is possible to obtain a good reproduction image by using the circuit 60. For example, n of the continuous detection circuit 44 is set to 2, and the reproduced data is written to the memory 40 only when it is determined that there is no error twice in succession.

[0030]

As can be easily understood from the above description, according to the present invention, erroneous memory writing can be appropriately prevented. Therefore, in the case of the image reproducing apparatus, a high quality reproduced image can be obtained.

[Brief description of drawings]

FIG. 1 is a basic circuit configuration block diagram of an embodiment of the present invention.

FIG. 2 is a configuration diagram of a synchronization block.

FIG. 3 is a circuit configuration block diagram of a conventional example.

4 is an operation flowchart of a continuous detection circuit 44 and a request mask circuit 46 of FIG.

FIG. 5 is a schematic block diagram of an example of application to a reproducing circuit of a digital video recording / reproducing apparatus.

FIG. 6 is a plan view of a head arrangement of a rotary drum.

FIG. 7 is a development view of a head arrangement of a rotary drum.

FIG. 8 is a diagram showing a track formed by the head shown in FIGS.
It is a pattern.

FIG. 9 is a reproduction envelope during double speed reproduction.

[Explanation of symbols]

10: Sync code SYNC 12: ID 14: Error detection code 16: Image data 18: Error detection and correction code 20: Input terminal 22: Sync detection circuit 22a: Sync detection signal 24: Timing generation circuit 24b: Memory address signal 24c: Write request (WRQT) signal 26: Symbol counter 28: Block counter 30: Upper counter 32: ID detection circuit 32a: ID load
Timing signal 34: Request mask circuit 36, 38:
Latch circuit 40: Memory circuit 42: ID detection circuit
42a: ID detection signal 42b: Detection status signal 44:
Continuous detection circuit 46: Request mask circuit 48, 50: n
Sync block delay circuit 60: circuit shown in FIG. 1 6
2: magnetic tape 64: reproducing head 66: reproducing amplifier 68: demodulating circuit 70: D / A converter 72: pinch roller 74: capstan 7
6: Capstan motor 78: Motor control circuit 8
0: rotating drum 82A, 82B, 84A, 84B: magnetic head for recording or reproduction 86: magnetic tape

Claims (1)

[Claims] 1. A reproducing apparatus for writing data included in a sync block to a memory address specified by an identification code included in the sync block at a timing defined by the sync code included in the sync block, Reproduction characterized by providing a control means for monitoring the detection state of the identification code included in the sync block and permitting the memory write of the data included in the sync block when the data is correctly detected n times consecutively. apparatus.