JP3232563B2 - Video playback device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video reproducing apparatus for reproducing a digitally recorded video signal.

2. Description of the Related Art For example, a digital VTR is a digital video recording device that digitizes a video signal and records it on a recording medium. In the digital VTR, an analog video signal (FIG. 4A) is sampled and quantized and converted into, for example, 8-bit digital data DD (FIG. 4B).
Then, in order to prevent the adverse effects caused by the burst error, the digital data DD is subjected to distributed processing such as shuffling, and further, as shown in FIG. Blocking, adding a block synchronization signal SYNC to the beginning of the block, adding an address signal ID and its error detection code ICRC in consideration of deshuffling (processing for returning shuffled data to the original arrangement), and transmitting data transmission errors Is added with an error detection code DCRC and error correction code parities P and Q for detecting and correcting SYNCB to form one synchronous block SYNCB.

A plurality of the synchronous blocks SYNCB are combined to form one track block TB (FIG. 4 (d)), and the track block TB is magnetically recorded on one track of the magnetic tape.

By the way, when reproducing a video signal recorded on a magnetic tape, a high-speed search mode for searching a recorded video at high speed is usually prepared in addition to a normal reproduction mode for faithfully reproducing a recorded video. is there. In normal playback mode,
There is no problem because the recording signal of each track of the magnetic tape is reproduced in order, but in the high-speed search mode, the reproduction head scans over a plurality of tracks T1 to TN, for example, like a locus HTR shown in FIG. In some cases, it may not be possible to obtain all data necessary for signal reproduction. Even if the video data can be reproduced, if the address signal ID cannot be reproduced correctly, the video data of the synchronous block SYNCB cannot be reconstructed correctly.

Therefore, conventionally, in the high-speed search mode, the address signal ID
The error detection code ICRC added to the error detection of the reproduced address signal ID is performed, and if there is no error in the ID, the video data of the synchronous block SYNCB is trusted and reconstructed. In the case where there is, for example, a method of replacing with the video data of the old (that is, the same screen position of the previous screen) synchronous block SYNCB has been adopted.

[Problems to be Solved by the Invention] However, in such a method, even if the video data is correctly reproduced, if there is an error in the address signal ID, all the video data of the synchronous block is not used. It becomes useless. Further, in such a case, since the image data is replaced with the video data of the old synchronous block SYNCB, there is a problem that the image quality is significantly deteriorated.

Therefore, an object of the present invention is to provide a video signal reproducing apparatus capable of obtaining a video of good image quality even in a high-speed search mode.

[Means for Solving the Problems] A video reproducing apparatus according to the present invention digitizes a video signal, adds identification data to each block composed of a predetermined number of video data, and outputs a plurality of blocks each having the identification data added thereto. A video reproducing apparatus in a video signal digital recording system for recording said blocks on a number of tracks on a recording medium in a predetermined order, comprising: reproducing means for reproducing a recording signal of said recording medium; Memory means for storing video data, write address control means for controlling a write address of the memory means, error detection means for detecting an error in reproduced identification data, and presence / absence of dropout of reproduced identification data. Dropout detection means for detecting the write address in the high-speed search mode. When there is no error in the reproduced identification data, the writing control unit determines the write address based on the identification data at that time,
When there is an error in the identification data and no dropout is detected by the dropout detection means, the write address is changed by new identification data obtained by advancing the value of the identification data reproduced in the past by a predetermined number. It is characterized in that it is determined.

[Operation] Even if there is an identification data error in the synchronous block, as long as the video data is reproduced, the video data is stored in the memory means and used for restoring the video. Therefore, the image quality is significantly improved as compared with the conventional example in which old video data is simply used when other identification data has an error.

Embodiment An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.
In this example, the above-mentioned synchronization block SYNCB is 1
It is assumed that the tracks are sequentially arranged on one track. That is, the fifth
It is assumed that the ID values are arranged in order of 1, 2, 3,... As shown in the figure.

In FIG. 1, the reproduction output of the reproduction head 10 is amplified by a reproduction amplifier 12, and the output of the reproduction amplifier 12 is supplied to a digital demodulation circuit 14 and a PLL circuit 16. The PLL circuit 16 generates a clock synchronized with the reproduction signal.
The digital demodulation circuit 14 digitally demodulates the output of the reproduction amplifier 12. Further, a dropout detection circuit 18 including an envelope detector detects the presence or absence of a dropout from the output of the reproduction amplifier 12, and outputs a dropout signal when the dropout exists.

The data demodulated by the digital demodulation circuit 14 is ECC
It is applied to the decoder 20 and the ID decoder 22. The ECC decoder 20 has an error detection code DCRC and error correction code parities P and Q.
Is used to correct the error in the demodulated data and output to the data bus 21, and the ID decoder 22 outputs the ID signal 23,
Outputs the error check signal 24 by the built-in CRC checker. If there is no error in the ID signal,
Check signal 24 is “0”, and if there is an error, “1”
It is. The error check signal 24 is connected to the preset control terminal of the write address counter 26, and the address signal
ID23 is connected to the preset input terminal of the write address counter 26.

If the error check signal 24 is “0”, the ID decoder 22
Of the write address counter 26
Preset to. The value held by the write address counter 26 is applied to the address input of the memory 30 via the address bus 28, and the memory 30 is responsive to the data input from the data bus 21.
(The output of the ECC decoder 20). In addition,
At this time, the clock input of the write address counter 26 does not count up because the AND gate 32 is blocked by the error check signal 24.

Next, the error check signal 24 is set to "1" (there is an error)
When the output of the dropout detection circuit 18 is "1" (no dropout), one clock per synchronous block generated by the frequency divider 34 from the output of the PLL circuit 16 passes through the AND gate 32. Applied to the clock input terminal of the write address counter 26
26 counts up by one. This allows the memory
30 reads the output (decoded data) of the ECC decoder 20 into the next address.

During a high-speed search, when the magnetic head traces across the track boundary, an error check signal
When 24 is "1", the output of the dropout detection circuit 18 becomes "0" (dropout is present). In this case, although illustration is omitted, writing to the memory 30 is prohibited. This allows
The memory 30 stores the data of the previous screen.

When the data for one screen is written in the memory 30 as described above, the next read operation is performed. That is, the crystal oscillator 36 oscillates at a constant period, and the read address counter 38 counts up by the output of the crystal oscillator 36. The output of the read address counter 38 is connected to the address input of the memory 30 via the address bus 28,
Data stored in the memory 30 is sequentially read out to the data bus 21 and output from the output terminal 40.

As described above, even if an error occurs in the ID signal,
This is simply determined as a random error, and the ID value is set in the write address counter 26, so that the decoded data is read into the memory 30 and is effectively used.

FIG. 2 is a block diagram showing the configuration of another embodiment of the present invention. The same components as those in FIG. 1 are denoted by the same reference numerals.
FIG. 3 shows a recording format which is the object of FIG. 2. The synchronous block syncb is interleaved between a plurality of tracks, and is distributed with a predetermined number (10 in this example) of offsets in the same track. I have. Such a format is designed to avoid noise bars being fixed at the same position on the playback screen during high-speed search.

In FIG. 2, the write address counter comprises a first write address counter 42 for outputting the lower part of the write address and a write address counter 44 for outputting the upper part of the write address. The write address counters 42 and 44 are, for example, decimal counters. The carry output of the lower write address counter 42 is connected to the clock input of the upper write address counter 44. The output of the AND gate 32 is connected to the clock input control terminal of the write address counter 44.

When the error check signal 24 of the ID decoder 22 is “0” (no error) and there is no dropout, the value of the corresponding bit of the ID output 23 of the ID decoder 22 is preset in the write address counters 42 and 44. The resulting address signal is applied to memory 30 via address bus 28. Thereby, the memory 30 reads the decoded data output from the ECC decoder 20 and on the data bus 21.

Also, the error check signal 24 of the ID decoder 22 is "1"
When there is an error and the output of the dropout detection circuit 18 is “1” (no dropout), the output clock of the frequency divider 34 is input to the clock input of the write address counter 44 via the AND gate 32. Applied to terminal. As a result, the address value defined by the write address counters 42 and 44 advances by 10. That is, the memory 30 advances by an amount corresponding to the offset in the interleaving of FIG. 3, and the memory 30 stores the data bus 21 in the corresponding storage location.
Read the above data.

Other operations are the same as those in FIG. 1. In this way, even when the synchronous blocks are interleaved between the tracks, the video data of the synchronous blocks having an error only in the ID can be written to the memory 30. Can be used for video playback.

In the above embodiment, the case where the synchronization blocks have a specific arrangement order in each track has been described as an example. However, the present invention can be applied to the case where the arrangement and the order are other than those described above. Further, it goes without saying that the write address counters 26, 42, and 44 are not limited to the above-described hardware configuration, and may have a more general configuration.

[Effects of the Invention] As can be easily understood from the above description, according to the present invention, even if an error occurs in the identification data of a block, the video data of the block is used. Can be greatly improved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, FIG. 2 is a block diagram showing the configuration of a second embodiment, FIG. FIG. 5 is an explanatory diagram of a video signal digital recording processing procedure, and FIG. 5 is an explanatory diagram of a head trace at the time of high-speed search. 10: playback head, 12: playback amplifier, 16: PLL circuit, 18: dropout detection circuit, 20: ECC decoder, 21: data bus, 22: ID decoder, 23: ID signal, 24: error check signal, 26, 42, 44: Write address counter, 28: Address bus, 30: Memory, 32: AND gate, 34: Divider

Claims (1)

(57) [Claims] An image signal is digitized, identification data is added to each block of a predetermined number of video data, and a plurality of blocks each having the identification data added thereto are arranged in a predetermined order on a recording medium. What is claimed is: 1. A video reproducing apparatus in a video signal digital recording system for recording on a track, comprising: reproducing means for reproducing a recording signal of the recording medium; memory means for storing video data in a reproduced signal by the reproducing means; Address control means for controlling the write address of the reproduced data, error detection means for detecting an error in the reproduced identification data, and dropout detection means for detecting the presence or absence of a dropout of the reproduced identification data. In the search mode, the write address control means applies an error to the reproduced identification data. When there is no record, the write address is determined based on the identification data at that time, and when there is an error in the identification data and no dropout is detected by the dropout detection means, the value of the identification data reproduced in the past is used. A video reproducing apparatus, wherein the write address is determined based on new identification data obtained by proceeding by a predetermined number.