JP2714013B2 - Video data recording / reproducing device and reproducing device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video data recording / reproducing apparatus and a reproducing apparatus, and in particular, records or reproduces video data such that a screen switching position of video data differs between tracks. Related to the device.

[Prior Art] FIG. 5 is a diagram showing a schematic configuration of a conventional general digital video tape recorder (DVTR).

In FIG. 5, the operation at the time of recording will be described first. The input image signal is converted into digital data by the A / D converter 30, and redundant data is deleted by the encoder 31 using the correlation of the images.

Next, an error correction code (ECC) as an error occurrence countermeasure for the recording medium is added by an ECC encoding circuit 32, and further a digital code modulation 33 is performed so as to obtain a signal spectrum distribution suitable for magnetic recording and reproduction. Thereafter, the data is recorded on the magnetic tape 36 via the recording amplifier 34 and the recording head 35.

During reproduction, the video data recorded on the magnetic tape 36 is reproduced through a reproduction head 37, a head amplifier 38, and a digital demodulator 39. The signals at this stage include the garbage mentioned earlier,
A code error has occurred in the recording medium due to a flaw or the like. Therefore, the ECC decoder 40 performs processing such as error correction. Next, redundant information such as a synchronization signal is added, and the decoder 41 almost completely restores the input information. Finally, the analog image signal similar to the input image information can be restored by the D / A converter 42.

Although a large number of DVTRs having the above configuration have been developed in recent years, most of these recording track patterns constitute a single screen with a plurality of tracks as shown in FIG. For example, first the track T ₁ through T ₃ in FIG. 6
Field, recording video signals of the second field in the track T ₄ through T _6.

In general, the number of tracks formed for one field of video signal is always an integral number. This is due to the advantage of taking into account DVTR synchronous operation, splicing, editing, and even variable speed playback.

[Problems to be Solved by the Invention] In recent years, the technology of high-efficiency encoding of image data has been developing at a rapid pace mainly in communication fields such as a video conference system and a video phone.

Also, with respect to DVTR, the demand for long-time recording is increasing.

Considering these points, it is possible to extend the recording time of DVTR even a little by applying the high-efficiency image coding technology developed in the communication field, and it will be practiced in the future. Seem.

However, if the data further compressed by the high-efficiency coding is to be recorded at the highest possible density, the screen switching position of the video data recorded on the recording medium may not be constant on the recording track. In this case, it becomes extremely difficult to input / output the DVTR video data in units of fields or frames. As described above, this leads to difficulties in DVTR synchronous operation, splicing, editing, and the like.

On the other hand, if one field and one frame of video data are always recorded on an integer number of tracks, for example, even if one field of video data can be compressed until it can be recorded on 2.1 tracks, Eventually, three tracks must be prepared for one field of video data, which hinders high-density recording.

The present invention has been made under such a background. In recording and reproducing video data, the present invention has been made to make it possible to handle video data in units of screens regardless of the screen switching position of the video data on a track. The purpose is.

[Means for Solving the Problems] Under such a purpose, according to the present invention, an input unit for inputting video data, a memory unit for storing the video data input by the input unit, and a recording medium Recording means for recording the video data read from the memory means so that a number of tracks are formed on the track, and the screen switching position differs between the tracks; and reproducing the video data from the recording medium and the reproduced video data. Reproducing means for writing the data into the memory means, a position detecting means for detecting a screen switching position of video data on the track, and the input means for the memory means based on the screen switching position detected by the position detecting means. And a memory control means for determining a write address of video data from the CPU.

[Operation] According to the configuration described above, all data written to or read from the memory can be based on the screen switching position, and video data can be handled on a screen basis. .

EXAMPLES The present invention will be described below using examples.

FIG. 1 is a diagram showing a schematic configuration of a digital data recorder as one embodiment of the present invention, FIG. 2 is a diagram showing an arrangement of cylinders and heads of the data recorder of this embodiment, and FIGS. (B) and (C) are diagrams for explaining the recording format of the present embodiment, and FIG. 4 is a diagram showing a memory space of the present embodiment.

In FIG. 1, reference numeral 1 denotes an input terminal for a digital signal to be recorded. Reference numeral 2 denotes a clock generator. The clock generated by the clock generator 2 is frequency-divided by the frequency divider 4 at a frequency dividing ratio set in advance according to the data amount of the input data. The memory control circuit 5 supplies a write address and a write enable signal to the RAM 7 using the output clock of the clock generator 2 as a write clock. In this way, data indicating the input digital signal is written into the RAM 7. Drum control circuit 8 drum rotation detector 13 outputs (200/3) H _z and outputs the rectangular wave signal and the frequency divider 4 (200
/ 3) controls the rotation of the drum as to synchronize the signals of H _z.

The digital data recorder (DDR) of this embodiment is the second
As shown in the figure, the magnetic tape 21 is attached to a rotating drum 20 having three adjacent heads Ha, Hb, and Hc and three adjacent heads Hd, He, and Hf rotating with a phase difference of 180 °. 18
It is wound over an angular range of 0 ° or more, and recording is performed on a magnetic tape by these six heads in total.

The heads Ha, Hb, and Hc are configured to rotate while being shifted from each other by a predetermined distance in the direction of the rotation axis, and the amount of the shift is set according to the recording track pitch. The same applies to the heads Hd, He, Hf.

The rotational speed of the current head and 4000 rpm, when the data input to the image data of the vertical synchronizing frequency 60H _z, per vertical sync period, head becomes to rotate 10/9. Since the heads are attached in the configuration shown in FIG. 2, data is recorded / reproduced on the track pattern on the tape by six tracks per rotation as shown in FIG. 3 (C).

FIG. 3A shows a recording data format for one track according to the present embodiment. In the drawing, a data string is formed one line at a time from the upper left to the upper right, and the data string is formed from the upper part to the lower part. Become. FIG. 3 (B) simply shows this, and the left-to-right direction of this one-track data sequence is the oblique direction from the lower right to the upper left of each track in FIG. 3 (C). Matches.

If the line shown in FIG. 3A is the vertical synchronization position of the input image data, the recording data area shown in FIG. 3B is the same in FIGS. 3B and 3C. Area. In this embodiment, the head is
Since the vertical synchronization position appears every 10/9 rotations, the vertical synchronization position does not become constant in the tape width direction as shown in the position of FIG. It will be difficult to determine whether to do so.

Data of each one line At a third diagram (A) is split horizontally into _^1/2 on the tape, each sub-block (Sub Blo
ck) Parity C1 of an error correction code for correcting data errors on the tape as 0 and Sub Block 1
Is added. Further, immediately before Sub Blocks 0 and 1, a sync pattern Sync for block synchronization and ID data for block identification are added by an ID word adding circuit 10 in FIG. In order to further enhance error correction, parity C2 of an error correction code for 4 lines is added for every 85 lines in the vertical direction. The ID data includes, for identification of the position of a block consisting of two sub-blocks, a block number indicating the position of a vertical line where this block exists in the format shown in FIG. V data indicating whether or not the block is the first block from the vertical synchronization position is included. These block numbers and V data are formed by the memory control circuit 5 based on the clock output from the clock generator 2, the clock output from the PLL circuit 6, and the vertical synchronizing signal of the input image signal from the terminal 9. .

The memory control circuit 5 supplies the read enable signal and the read address to the RAM 7 by using the clock output from the PLL circuit 6 as the read clock, and the read from the RAM 7 is performed. The data read from the RAM 7 is distributed to the three recording systems in data block units,
2 Error correction encoder that adds parity and sync (ECC, E
N) 11a, 11b, 11c, and digital modulator (MOD) 12a, 12
b, 12c, and are supplied to the respective heads via the R terminals of the switches SW1, SW2, SW3. As shown, heads Ha and Hd, heads Hb and H
e, the heads Hc and Hf are recording heads of the same system.

Next, the reproducing system will be described. The reproduced signals of the three systems reproduced by the respective heads are demodulated by digital demodulators (DEM) 14a, 14b, 14c via P terminals of switches SW1, SW2, SW3, and then error-corrected decoders (ECC, DE) At 15a, 15b, and 15c, error correction by C1 and C2 parity is performed, and the data is serially written to the RAM 7 '.

FIG. 4 is a diagram showing the data storage area of the RAM 7 '. The horizontal direction corresponds to data for exactly one track. Each of the data shown in FIG. 4 is shown in FIG.
However, the same symbol was used.

Now, for example, consider a case where data is output in synchronization with an external vertical synchronization signal during reproduction. At this time, the vertical synchronization position can be known from the ID data indicating the block number in the reproduced signal and the V data included therein. That is, the line number including the V data, that is, the offset amount in the horizontal direction shown in FIG. 4A can be recognized. Therefore, in synchronization with the external vertical synchronizing signal, as shown in FIG.
The object is attained by sequentially reading out the data obtained by adding the offset amount as the read address of the RAM 7 '.

That is, the block number is extracted by the ID word extraction circuit 16 in FIG. 1, and the write address of the memory is controlled. The offset amount is extracted from the V data extracted at the same time by the memory control circuit 5 '. An external vertical synchronizing signal for reading is inputted from a terminal 9, and in synchronism therewith, reading is performed from the address of the offset amount, whereby reproduced signal data synchronized with the external vertical synchronizing signal is output from a terminal 17.

In the above embodiment, the RAM 7 in the recording system and the RAM 7 'in the reproducing system are separately shown for simplicity of description.
Actually, it is common to share the memory control circuits 5, 5 '.

In the embodiment as described above, a video signal synchronized with any external vertical synchronization signal can be reproduced.
It can easily perform operations such as DVTR synchronous operation and editing.

Lastly, a brief description will be given of a case where the above embodiment is applied to splicing. When the pause switch is pressed, data is stored in the RAM 7 'as shown in FIG.
At this time, it is assumed that the RAM is shared with the RAM 7 of the recording system. The tape is once rewound by a predetermined length, and is conveyed at a speed for normal recording and reproduction while controlling tracking.

Next, using information such as time code,
The data to be recorded from the RAM 7 is not read out from the RAM 7 until the timing at which the RAM 7 reads out the signals recorded at the timing of starting the tracing of the three tracks including that shown in FIG. Reading is performed at an address according to the block number. At this time, if the data is written in synchronization with the vertical synchronization signal of the input image signal from the address according to the offset amount A, the continuous shooting can be performed.

In order to make the video data to be recorded correspond to an arbitrary screen switching position on the track, the write address may be offset.

[Effects of the Invention] As described above, according to the present invention, a screen switching position on a track of reproduced video data is detected, and based on this screen switching position, an address for writing input data to a memory is determined. Since the determination is made, at the time of recording the video data, the video data can be handled on a screen basis, regardless of the screen switching position on any track.

Further, in another invention of the present application, the read address of the memory is determined according to the screen switching position on the track of the video data, so that when the video data is reproduced,
Video data can be handled in units of screens regardless of the screen switching position on any track.

Therefore, even if video data is recorded for as long a time as possible, various disadvantages in processing the video data do not occur.

[Brief description of the drawings]

FIG. 1 is a diagram showing a schematic configuration of a digital data recorder as one embodiment of the present invention, FIG. 2 is a diagram showing an arrangement of cylinders and heads of the digital data recorder of FIG. 1, FIG. (B) and (C) are diagrams for explaining a recording format of the data recorder of FIG. 1, FIG. 4 is a diagram showing a data storage space of a RAM in FIG. 1, and FIG. 5 is a diagram of a conventional DVTR. FIG. 6 is a diagram showing a general configuration, and FIG. 6 is a diagram showing a recording pattern on a tape by the DVTR of FIG. In the figure, 1 is an image signal input terminal, 5, 5 'are memory control circuits,
7, 7 'are RAMs, 9 is a vertical synchronizing signal input terminal, 10 is an ID word adding circuit, 16 is an ID word extracting circuit, and 21 is a magnetic tape.

Claims (2)

(57) [Claims] An input unit for inputting video data; a memory unit for storing the video data input by the input unit; a plurality of tracks formed on a recording medium, and a screen switching position differs between the tracks. Recording means for recording the video data read from the memory means, reproducing means for reproducing the video data from the recording medium and writing the reproduced video data to the memory means, A video comprising: a position detecting means for detecting a screen switching position; and a memory control means for determining a write address of video data from the input means to the memory means based on the screen switching position detected by the position detecting means. Data recording and playback device. 2. A reproducing means for reproducing the video data from a recording medium in which a number of tracks are formed and video data is recorded such that a screen switching position is different between the tracks, and a video data reproduced by the reproducing means. A memory for storing a screen switching position of the video data on the track; and a memory control unit for determining a read address of the memory based on the screen switching position detected by the position detecting unit. A playback device comprising: