JPH0782712B2 - Digital signal recording / reproducing device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to digital signal recording / reproducing, and more particularly to a digital signal recording / reproducing apparatus suitable for a tape recorder using a rotary head.

[Background of the Invention]

Convert audio to PCM signal and record / play back on magnetic tape P
The CM signal recording / reproducing apparatus has a feature that it can record voice with high quality and that the quality does not deteriorate even if copying is performed.

As one method of this PCM signal recording / reproducing apparatus, Japanese Patent Laid-Open No. 59-16
There is a system using a rotary head as described in No. 111.
In this method, the track pitch can be narrowed, so that the recording density can be increased.

In such a PCM signal recording / reproducing apparatus, it is necessary to record or reproduce the PCM signal and input from the A / D converter or output to the D / A converter at the same time. Input / output must be always performed at the sampling cycle, and recording / reproduction must be performed at another cycle. In particular, during reproduction, it is necessary to absorb the jitter component contained in the reproduction signal during writing to the RAM.
Furthermore, it is necessary to add an error correction code at the time of recording and also perform an error correction at the time of reproduction. Therefore, in the past,
As described in No. 59-16111, two systems of RAM were prepared and used by alternately switching between the recording / reproducing side and the input / output side.

[Object of the Invention]

An object of the present invention is to provide a digital signal recording / reproducing apparatus capable of recording / reproducing with one series of RAMs.

[Outline of Invention]

According to the present invention, the RAM access slot is divided into two types of slots, the recording signal is read or the reproduction signal is written in the first slot, and the A / D converter and D / D are used in the second slot.
Recording / playback is performed with one system of RAM by inputting / outputting to / from the A converter, adding error correction code, and performing error correction.

Example of Invention

 An embodiment of the present invention will be described below with reference to FIG.

FIG. 1 shows a digital signal recording / reproducing apparatus which records or reproduces a PCM signal by a recording / reproducing switching signal inputted from an input terminal 28. First, the case of recording will be described.

During recording, the analog signal input from input terminal 26
It is converted into a PCM signal by the A / D converter 25. The input signal may be a PCM signal output from another PCM signal reproducing device or a digital signal other than the PCM signal. In this case, the A / D converter 25 is unnecessary. This is the same when outputting. The PCM signal converted by the A / D converter 25 is written in the RAM 21 through the bus line 20. RAM21 at this time
The write address of is generated by the input / output address generation circuit 17. Incidentally, when the PCM signal is written in the RAM 21, the recording signal can be monitored from the output terminal 27 by simultaneously inputting it to the D / A converter 24 through the error correction circuit 23. At this time, the error correction circuit 23 may be controlled so as not to operate.

The PCM signal written in RAM21 is corrected address generation circuit 16
Is read according to the address generated by the bus line 20
Is input to the error correction circuit 22 to generate an error correction code. That is, the error correction circuit 22 generates an error correction code at the time of recording, and corrects an error in the reproduction signal by the error correction code at the time of reproduction. The error correction circuit 22 generates an error correction code based on the input PCM signal, and writes the generated error correction code in the RAM 21.

After the generation of the error correction code, the PCM signal and the error correction code stored in the RAM 21 are read according to the address generated by the recording / reproducing address generation circuit 11,
It is input to the recording circuit 5 through the bus line 20 and the interface circuit 6. In the recording circuit 5, a synchronization signal, a control signal, etc. are added and modulated. Then, after being amplified by the recording amplifier 4, it is recorded on the magnetic tape 1 by the rotary head 2. The rotary head 2 is composed of two heads, A and B, which are mounted on the cylinder so as to face each other by 180 °. The magnetic tape 1 is wound around a cylinder, and the winding angle is usually 180 ° or less, for example 90 °. Then, a signal is recorded when the head comes over the magnetic tape.

The timing generation circuit 15 generates a timing signal for controlling each part by a clock oscillated by the oscillation circuit 14. The oscillation frequency of the oscillator circuit 14 is selected to be an integral multiple of the sampling frequency of the PCM signal. The oscillator circuit 10 oscillates a clock having a frequency corresponding to the transmission rate of the recording signal. Then, the PCM signal and the error correction code are sequentially recorded according to this clock. The switching circuits 18 and 19 switch the address of the RAM 21. Further, the servo circuit 13 controls the rotational phase of the rotary head 2. Position detection circuit 12
Detects the phase of the cylinder with a reference signal indicating the position of the cylinder. Then, the recording timing is determined according to this reference signal.

FIG. 2 shows a recording pattern on the magnetic tape 1. 30 is 1
Shows the track of a book. On one track, a PCM signal and an error correction code are recorded by being divided into a plurality of blocks, for example, 128 blocks. FIG. 3 shows the structure of one block. Reference numeral 31 is a synchronization signal, 32 is a control signal related to the PCM signal, 33 is a block address indicating the number of the block, and 34 is a PCM signal and an error correction code.

FIG. 4 shows the timing of inputting a PCM signal during recording, generating an error correction code, and recording. 35 is A / D converter 2
5, the write timing to the RAM 21; 36, the generation timing of the error correction code; 37, the reference signal of the servo circuit 13; 38, the position detection signal of the rotary head 2; 39, the read timing from the RAM 21 to the recording circuit 5; Is the recording timing on the magnetic tape. The numbers 35, 36 and 39 indicate the storage areas of the RAM 21. That is, the RAM 21 has a capacity for storing RCM signals and error correction codes for four tracks, which are a first area, a second area, a third area, and a fourth area, respectively. A and B in 40 indicate recording heads. Writing from the A / D converter 25 to the RAM 21 is performed at a constant cycle according to the sampling frequency. For example,
If the sampling frequency of the PCM signal is set to 48 KHz and the PCM signal of 2 channels is recorded, it is necessary to write once in about 10 μsec. Here, the access frequency of RAM21 is 64 times the sampling frequency, that is, 3.072 MHz,
If a PCM signal having a quantization bit number of 16 bits is to be written in 8-bit units, it is necessary to write at a rate of 2 times for 32 accesses. Writing from the A / D converter 25 to the RAM 21 is performed by writing one rotation (360 °) of the rotary head to the first and second areas, and writing the next one rotation to the third and fourth, as shown at 35.
Will be written to the area. At this time, as shown at 36, an error correction code is generated for the PCM signals written in the first and second areas in the previous rotation. For the PCM signals written in the third and fourth areas, the error correction code is similarly generated in the next one rotation. After the error correction code is generated, the PCM signal and the error correction code are read from the RAM 21 at the timing of 39 and recorded on the magnetic tape 1 at the timing of 40. The recording timing is the position detection signal 38
Can be decided based on. The position detection signal 38 indicates the position where the rotary head is 0 ° (the position where the head A starts scanning the magnetic tape 1). The servo circuit 13 controls the rotation phase of the rotary head 2 so that the falling edge of the reference signal 37 generated by the timing generation circuit 15 and the position detection signal 38 match. Then, the recording / reproducing address generation circuit 11 determines the recording timing with reference to the position detection signal 38,
Reads PCM signal and error correction code from RAM21.
This reading is performed at a frequency corresponding to the recording rate oscillated by the oscillation circuit 10. The position of the position detection signal 38 may be a position other than 0 °. Also, the timing 36 for generating the error correction code and the read timing during recording
Although 39 are partially overlapped, if the generation order of the error correction code and the recording order are matched, there is no problem because the generation of the error correction code for the PCM signal already recorded is completed at the time of recording.

FIG. 5 shows the switching timing of the switching circuit 19, that is, the reading of the PCM signal and the error correction code for recording and the A / D converter.
It is the switching timing of the writing from 25 to the RAM 21 and the generation of the error correction code. 41 is the control signal of the switching circuit 19, 42 is R
It is an AM slot. Here, it is assumed that the switching circuit 18 is selected when the control signal 41 is "1" and the recording / reproducing address generation circuit 11 is selected when the control signal 41 is "0". That is, in slot 43 A /
The D converter 25 writes to the RAM 21 and generates an error correction code, and the slot 44 stores the PCM from the RAM 21 for recording.
The signal and the error correction code are read.

FIG. 6 shows the switching timing of the switching circuit 18, that is, A /
This is the switching timing of writing from the D converter 25 to the RAM 21 and generation of the error correction code. 45 is a control signal for the switching circuit 8, which selects the input / output address generation circuit 17 when it is "1",
When it is "0", the correction address generation circuit 16 is selected. As described above, the PCM signal may be written at a ratio of 2 slots to 64 slots. Looking at slot 43, 16
It may be performed at a rate of 2 slots per slot. In the present embodiment, the A / D converter 25
4 slots out of 16 slots are assigned to write the PCM signal to the RAM 21. Then, the error correction code is generated in the remaining 12 slots, that is, the RAM 21 and the error correction circuit 22.
Transfer data to and from.

FIG. 7 shows the operation timing of the interface circuit 6. 46 is the timing of the recording data input to the recording circuit 5. The numbers indicate the data numbers. The recording circuit 5 records data at a preset transmission rate. The access speed of the RAM 21 is set to be twice or more the speed of this recording transmission rate. In this embodiment, the recording transmission rate is about 1 MHz, and the RAM access speed (3.072 MHz) is about three times as high. In interface circuit 6, RAM21 is installed in slot 44.
The data rate is exchanged so that the read PCM signal and the error correction code have a recording transmission rate as indicated by 46.

FIG. 8 is a configuration example of the interface circuit 6. 55 ~
Reference numeral 59 is a latch circuit, 60 is an AND circuit, and 61 is an inverter. Further, 50 is an input terminal for the data read from the RAM 21,
51 is an input terminal of the slot switching signal 41, 52 is an output terminal of a read request signal, 53 is an output terminal of data to the recording circuit 5,
Reference numeral 54 is a clock input terminal synchronized with the recording transmission rate. The operation of the interface circuit of FIG. 8 will be described below with reference to the timing chart of FIG. The latch circuit 56 sequentially latches the data by the clock 66 input from the input terminal 54 and outputs the data from the output terminal 53. Therefore, when latched by the latch circuit 56, the recording data is
The read is controlled as if it is being read more. When the data is latched by the latch circuit 56, the output signal 65 of the latch circuit 58
Becomes "1". The output signal 65 is latched by the latch circuit 59, and the AND circuit 60 generates the latch clock 64 of the latch circuit 55 by the logical product of the output of the latch circuit 59 and the slot switching signal 41 input from the input terminal 51. Latch circuit 55
Then, the data read from the RAM 21 is latched at the rising edge of the latch clock 64. Reference numeral 63 indicates the output of the latch circuit 55. When data is latched by the latch circuit 55, the output of the latch circuit 57 becomes "1", the latch circuit 58 is cleared, and the output signal 65 is set to "0". The latch clock 64 is inverted by the inverter 61 to generate the read request signal 62 output from the output terminal 52. In the read / write address generation circuit 11, when the read request signal 62 becomes "1", the address of the RAM 21 is advanced by 1 and the next data is read from the RAM 21. In this way, the data rate conversion shown in FIG. 7 is performed.

As described above, by allocating the dedicated RAM slot for reading the recording signal at the time of recording in the RAM21, writing the PCM signal from the A / D converter and adding the error correction code, the PCM signal can be recorded in one system of RAM. Can be recorded.

Next, the case of performing reproduction in the PCM signal recording / reproducing apparatus of FIG. 1 will be described.

During reproduction, the switching circuit 3 is switched to the reproducing side by the recording / reproducing switching signal input from the input terminal 28, and the reproducing signal reproduced by the rotary head 2 is amplified and waveform equalized by the reproducing amplifier 7. It is input to the reproduction circuit 8. The recording / reproducing switching signal also switches the operation timing of the RAM 21, the operation of the error correction circuit 22, and the operation of the A / D converter 25.

The reproducing circuit 8 demodulates the PCM signal and the error correction code and detects the synchronization signal and the control signal. The PCM signal demodulated by the reproduction circuit 8 and the error correction code are written in the RAM 21 via the interface circuit 9 and the bus line 20.
The address of the RAM 21 at the time of writing is generated by the recording / reproducing address generating circuit 11 with reference to the block address in the synchronizing signal and the control signal detected by the reproducing circuit 8.

The PCM signal and the error correction code written in the RAM 21 are read according to the address generated by the correction address generation circuit 16 and input to the error correction circuit 22 through the bus line 20 to perform error correction. PC corrected by the error correction circuit 22
The M signal is written in the RAM 21 again.

The error-corrected PCM signal is read from the RAM 21 according to the address generated by the input / output address generation circuit 17 and input to the error correction circuit 23 through the bus line 20. The error correction circuit 23 performs error correction such as average value interpolation for replacing the error that could not be corrected with the average value of the preceding and following values, and outputs it to the D / A converter 24. Then, it is converted into an analog signal by the D / A converter 24 and output from the output terminal 27. The reproduced PCM signal may be directly output to another PCM device without being converted into an analog signal.

Recording / reproducing address generation circuit 11, correction address generation circuit 16
In addition, since the address generated at the time of recording and the address generated at the time of reproduction are the same, the same circuit can be used at the time of recording and reproduction.

FIG. 10 shows the timing of signal reproduction, error correction, and PCM signal output during reproduction. Reference numeral 70 is a reproduction timing from the magnetic tape 1, 71 is a write timing from the reproduction circuit 8 to the RAM 21, 72 is an error correction timing, and 73 is a read timing from the RAM 21 to the error correction circuit 23. The reproduction of the signal from the magnetic tape 1 is performed in synchronization with the reference signal 37. Then, at timing 71, the first to fourth areas of the RAM 21 are sequentially written. The reproduced signal written in the RAM 21 is error-corrected at the timing 72. Although the timing of writing the reproduced signal and the timing of error correction overlap, there is no problem if the order of reproduction and the order of error correction are the same. The error-corrected PCM signal is output by one rotation (360 °) of the next rotary head.

The switching timing of the switching circuits 18 and 19 may be the same as during recording. That is, error correction and RAM2 are performed in slot 43 of FIG.
The PCM signal is read from the error correction circuit 23 from 1 and the reproduction signal is written to the RAM 21 in the slot 44. In slot 43, as shown in FIG. 6, 4 out of 16 slots are used.
Slots are assigned to read PCM signals, and 12 slots are assigned to data transfer between the RAM 21 and the error correction circuit 22 during error correction. The PCM signal is read once by reading the upper 8 bits and the lower 8 bits of the 16-bit PCM signal of one word and the four data of two flags indicating whether or not the read PCM signal is incorrect. put out. That is, the RAM 21 is accessed four times with one read.

FIG. 11 shows the operation timing of the interface circuit 9. Reference numeral 74 is the timing of the reproduction data output from the reproduction circuit 8, and the reproduction transmission rate is about 1 MHz, as in recording. As shown in FIG. 11, during reproduction, the reverse conversion of the conversion of FIG. 7 during recording is performed.

FIG. 12 shows a configuration example of the interface circuit 9. 84 ~
Reference numeral 88 is a latch circuit, and 89 is a buffer. Further, 80 is an input terminal of the reproduction data 74 output from the reproduction circuit 8, 81 is an input terminal of a reproduction clock synchronized with the reproduction data, and 82 is a RAM 21.
Is a data output terminal to, and 83 is an input terminal of the slot switching signal 41. Below, according to the timing diagram of Fig. 13,
The operation of the interface circuit shown in FIG. 12 will be described. The latch circuit 84 latches the reproduction data 74 input from the input terminal 80 with the reproduction clock 90 input from the input terminal 81. 91 indicates the output of the latch circuit 84. Latch circuit
When the data is latched at 84, the output signal 92 of the latch circuit 86
Becomes "1". The output signal 92 is latched by the latch circuit 88 by the slot switching signal 41, and the AND circuit 60 generates the latch clock 93 of the latch circuit 85 by the logical product of the output of the latch circuit 88 and the slot switching signal 41. 94 is a latch circuit
The output of 85 is shown. When data is latched by the latch circuit 85, the output of the latch circuit 87 becomes "1",
Clear 86 and set output signal 92 to "0". Buffer 89
Outputs the reproduction data latched in the latch circuit 85 from the output terminal 82 to the RAM 21 when the slot switching signal 41 is "0", that is, in the slot 44. In this way
The data rate conversion shown in FIG. 11 is performed.

As described above, by writing a reproduction signal in the RAM 21 during reproduction, error correction, and allocating a dedicated RAM slot for output of the PCM signal, it is possible to reproduce the PCM signal with one system of RAM. Further, the RAM address generation circuit can be shared during recording and reproduction.

The switching circuits 18 and 19 may use a single 3-input switching circuit.

FIG. 14 shows an embodiment of the digital signal reproducing apparatus of the present invention. The operation is the same as when the circuit of FIG. 1 is reproduced. That is, a read-only circuit can be constructed by removing the recording circuit and the A / D converter from the digital signal recording / reproducing apparatus of FIG. Similarly, the recording-only circuit can be constructed by removing the reproducing circuit, the error correction circuit, and the D / A converter.

FIG. 15 shows an embodiment in which a subcode such as a time code is recorded / reproduced in addition to the PCM signal in the digital signal recording / reproducing apparatus of the present invention. Reference numeral 100 is a subcode address generation circuit, 101 is a switching circuit, and 102 is a subcode input / output circuit.

At the time of recording, a subcode is input from the input / output terminal 103 and written in the RAM 21 via the subcode input / output circuit 102. The write address at this time is generated by the subcode address generation circuit 11. Then, it is read from the RAM 21 together with the PCM signal and the error correction code and recorded on the magnetic tape 1. The subcode can be written in the RAM 21 by utilizing the idle time of the slot 44. Slot 44
Is used for reading data from the RAM 21 to the recording circuit 5, but the reading is not performed during 90 ° when the head A or B is not in contact with the magnetic tape 1. Therefore, the subcode can be written to the RAM 21 at this time. Figure 16 shows the timing of subcode input. 104 is a control signal for the switching circuit 101. Control signal 104
Is "0", the switching circuit 101 selects the recording / reproducing address generating circuit 11, records data, and outputs the control signal 104
Is "1", the switching circuit 101 selects the subcode address generation circuit 100 and writes the subcode to the RAM 21.

At the time of reproduction, the subcode which is reproduced from the magnetic tape 1 together with the RAM signal and the error correction code and is written in the RAM 21 is read by the address generated by the subcode address generation circuit 100, and is read via the subcode input / output circuit 102. Output from the input / output terminal 103. As for the subcode read timing, the idle time of the slot 44 may be used as in the recording.

The area for storing the subcode of the RAM 21 may be a dedicated area, but may be an area for storing the error correction code. For example, when recording / reproducing is performed using the first or second area of the RAM 21, the PCM signal is input or output in the third and fourth areas. That is, the PCM signal before adding the error correction code is written in the third and fourth areas, but the PCM signal after the error correction is read. Therefore, there is no problem even if the subcode is stored in the area for storing the error correction code in the third or fourth area. By doing so, the subcode can be stored without increasing the storage capacity of the RAM 21.

The switching circuits 18, 19, 101 of the circuit shown in FIG. 15 may use one switching circuit with four inputs.

As described above, according to the circuit in FIG.
Only by using the PCM signal, it is possible to record and reproduce the subcode such as the time code related to the PCM signal at the same time.

〔The invention's effect〕

According to the present invention, it is possible to record and reproduce a digital signal with one system of RAM. It is also possible to support recording / reproducing of subcodes.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of a digital signal recording / reproducing apparatus of the present invention, FIG. 2 is a recording pattern diagram on a magnetic tape,
FIG. 3 is a block diagram, FIG. 4 is a timing diagram at the time of recording, FIG. 5 is a timing diagram of the switching circuit 19, FIG. 6 is a timing diagram of the switching circuit 18, and FIG. 7 is data conversion of the interface circuit 6. FIG. 8, FIG. 8 is a diagram showing one configuration example of the interface circuit 6, FIG. 9 is a timing diagram of the circuit of FIG. 8, FIG. 10 is a timing diagram at the time of reproduction, and FIG. 11 is a diagram of the interface circuit 9. FIG. 12 is a diagram showing a data conversion, FIG. 12 is a diagram showing one configuration example of the interface circuit 9, FIG. 13 is a timing diagram of the circuit of FIG. 12, and FIG. 14 is a diagram showing an embodiment of the digital signal reproducing apparatus of the present invention. FIG. 15 is a configuration diagram of another embodiment of the digital signal recording / reproducing apparatus of the present invention, and FIG. 16 is a timing diagram at the time of recording of the circuit of FIG. 5 ... Recording circuit 6, 9 ... Interface circuit 8 ... Reproduction circuit 10, 14 ... Oscillation circuit 11 ... Recording / reproduction address generation circuit 15 ... Timing generation circuit 16 ... Corrected address generation circuit 17 ... Input / output Address generation circuit 18, 19 …… Switching circuit 21 …… RAM 22 …… Error correction circuit 23 …… Error correction circuit 24 …… D / A converter 25 …… A / D converter 100 …… Subcode address generation circuit 101 …… Switching circuit 102 …… Subcode input / output circuit

 ─────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP 59-215013 (JP, A) JP 60-79564 (JP, A) JP 55-70920 (JP, A)

Claims (3)

[Claims] 1. A digital signal input / output circuit for inputting / outputting a digital signal, a storage circuit for storing the digital signal, a control circuit for controlling writing / reading of the storage circuit, and a digital signal Error correction code for adding an error correction code or correcting an error in the digital signal, a subcode input / output circuit for inputting / outputting a subcode signal related to the digital signal, the digital signal, the error correction code And a digital signal recording / reproducing apparatus comprising a recording / reproducing circuit for recording a sub-code signal on a recording medium or reproducing the sub-code signal from the recording medium, wherein the control circuit is configured to control the digital signal according to a timing of inputting or outputting the digital signal. Writing from the signal input / output circuit or writing to the digital signal input / output circuit Digital signal input / output control circuit for controlling reading, and error correction control circuit for controlling reading to or writing from the error correction circuit for adding the error correction code or error correction at a predetermined timing And a recording / reproducing control circuit for controlling reading or writing of the digital signal, the error correction code, and the subcode signal to the recording / reproducing circuit at the timing of recording or reproducing on the recording medium, When the digital signal input / output control circuit, the error correction control circuit, and the recording / reproduction control circuit are not writing or reading the storage circuit, the subcode signal is written from the subcode signal input / output circuit or the subcode signal is written. With a sub-code signal input / output control circuit for reading to the code signal input / output circuit Digital signal recording and reproducing apparatus characterized by comprising more. 2. The digital signal recording / reproducing apparatus according to claim 1, wherein the control circuit places the sub-code signal in the same area as the area in which the error correction code is stored in the storage circuit. A digital signal recording / reproducing apparatus characterized by being controlled to be stored. 3. A digital signal recording / reproducing apparatus according to claim 1 or 2, wherein an access cycle of the storage circuit is set to a transmission rate of 2 in byte unit when recording or reproducing on the recording medium. A digital signal recording / reproducing device characterized by being more than doubled.