JPS6286584A - Pcm signal recording and reproducing device - Google Patents

Abstract

PURPOSE:To perform a recording/reproduction by a RAM of one system by sorting an access slot of the RAM out into two types, carrying out a reading/ writing by the first slot, and applying A/D, D/A conversions, and operating an error correction. CONSTITUTION:According to a writing address produced in an input and output address producing circuit 17 during recording, a PCM signal is written in a RAM 21. The PCM signal written in the RAM 21 is read according to an address produced in a correcting address producing circuit 16, an error correcting code is produced in an error correcting circuit 22, written in the RAM 21, and during reproducing, the error correction in a reproducing signal is performed by the error correction code. To input and output addresses and correction address, exclusively used slots are respectively allocated, and recording/reproduction of the PCM signal is performed by the RAM of one system.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to recording and reproducing PCM signals, and relates to a PL'M signal recording and reproducing apparatus suitable for a tape recorder using a reproducing head in the back.

[Background of the invention]

A PCM signal recording and reproducing device that converts audio into a PCM signal and records and reproduces it on a magnetic tape has the feature that it can record audio with high quality and that the quality does not deteriorate even when it is copied.

As one method of this PCM signal recording and reproducing device,
There is a method using a rotating head as described in No. 9-16111. With this method, the track pitch can be narrowed, so the recording density can be increased.

In such a PCM signal recording and reproducing device, recording or reproducing a PCM signal and inputting from a ~0 converter or D/A
It is necessary to output to the converter at the same time. Input/output must be constant at the sampling period, and recording and reproduction must be performed at a different period. In particular, during reproduction, it is necessary to absorb jitter components included in the reproduced signal when writing to the RAM. Furthermore, it is necessary to add an error correction code during recording and to perform error correction during reproduction at the same time. Therefore, conventionally, as described in JP-A-59-16111,
A system chart was prepared and used by switching alternately between the recording/playback side and the input/output side.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a PCM signal recording and reproducing apparatus that can perform recording or reproducing using one system of votes.

[Summary of the invention]

According to the present invention, the access slot of the RAM is divided into two slots, the first slot is used to generate a recording signal or the reproduction signal is written, and the second slot is used to send a signal to an N0 converter and a D/A converter. input/output and addition of error correction code,
By performing error correction, recording or reproduction is performed using one system of &W.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to FIG.

In FIG. 1, a PCM signal is recorded or reproduced by a recording 4 raw switching signal inputted from an input terminal 28.
This is a signal recording and reproducing device. First, the case of recording will be explained.

During recording, an analog signal input from the input terminal 26 is converted into a PCM signal by the .about.Φ converter 25. In addition, the input signal is a PC output from another λ blade signal reproducing device.
It may be an M-fold signal or a digital signal other than a PCM signal. In this case, a VDK converter'? 5 is unnecessary. This also applies to output. The PCM signal converted by the A/D converter 25 is passed through the path line 20 to the RA
Written to M21. The write address of the RAIld 21 at this time is generated by the input/output address generation circuit 17.

Incidentally, when the PCM multiplied signal is stored in the RAM 21, the recording signal can be monitored from the output terminal 27 by simultaneously inputting it to the D/A converter 24 through the error correction circuit 25. At this time, the error correction circuit 25 can be controlled so as not to operate (it is better if the error correction circuit 25 is not operated).

The PCM multiplied signal written in the RAM 21 is read out in accordance with the address generated by the correction address generation circuit 16, and is input to the error correction circuit 22 through the pass line 20 to generate an error correction code.

That is, the error correction circuit 221 generates an error correction code during recording, and corrects errors in the reproduced signal using the error correction code during reproduction. error correction circuit 22
Right hand, generates an error correction code based on the input PCM signal, and stores the generated error correction code in the RAM21 VCI.
'Include.

After the error correction code is generated, the PCM multiplied signal and error correction code stored in the section M21 are read out according to the address generated by the recording/reproduction address generation circuit 11, and are read out through the pass line 20 and the interface circuit 6. The signal is input to the recording circuit 5. In the recording circuit 5, addition and modulation of synchronization signals, division signals, etc. are performed. and.

After being amplified by the recording amplifier 4, the signal is recorded on the magnetic tape 1 by the rotary head 2. The rotating head 2 is composed of 82 heads mounted 1800 times opposite each other on a cylinder. The magnetic tape 1 is wound around a cylinder at a temperature of 1800 degrees Celsius or less.
For example, it is 900. Then, when the head comes over the magnetic tape, a signal is recorded.

The timing generation circuit 15 generates timing signals for controlling various parts using the clock oscillated by the oscillation circuit 14. The oscillation station algebra of the oscillation circuit 14 is selected to be an integral multiple of the PCM signal sampling frequency. The oscillation circuit 10 finds a clock with a frequency corresponding to the transmission rate of the recording signal, and sequentially records the PCM signal and error correction code according to this clock (switching circuits 18 and 19 switch the address of the RAM 21). It is.

Further, the servo circuit 15 controls the rotational phase of the rotary head 2. The position detection circuit 12 detects the phase of the cylinder based on a reference signal indicating the position of the cylinder. Then, the recording timing is determined according to this reference signal.

FIG. 2 shows a recording pattern on the magnetic tape 1. As shown in FIG. 50 indicates one track. For one track, PCM
The signal and error correction code are multi-valued blocks, e.g. 12
It is divided into 86 parts and recorded. FIG. 5 shows the configuration of one block. 51 is a synchronization signal, 52 is a control signal related to the PCM signal, 55 is a $block address indicating the block number, and 54 is a PCM double signal error correction code.

Chestnut 4 shows the input of the PCM signal during recording, the generation of the error correction code, and the timing of recording. 35 is vDx
Timing of writing from converter 25 to RAM 21, 56 timing of error correction code generation, 57 servo circuit 1
50 reference signal, 58 position detection signal of rotary head 2, 5
9 is the read timing from the RAM 21 to the recording circuit 5;
40 is the recording timing on the magnetic tape. 55,
The numbers 56 and 59 indicate the storage area of the RAM 21. In other words, RJ%! vi21)
This is the fourth area. Further, A and B at 40 indicate recording heads. Writing from the A/D converter 25 to the auxiliary plate 21 is performed at a constant cycle according to the sampling frequency. For example, if the sampling frequency of the PCM signal is 48)G(z), then the 2-channel PC:M
If a signal is to be recorded, it is necessary to write once every approximately 10 μsec. Here, we set the access frequency of key 21 to 64 times the sampling frequency, that is, 5,072
MHz, the number of quantization bits is 16 bits, and a PCM signal of 8 bits is written in units of 8 bits.
It is necessary to write at a rate of 1. N0 converter 25
When data is written into the RAM 21, as shown at 55, data is written into the first and second areas with one revolution (560G) of the rotary head, and written into the fifth and fourth areas with one revolution of the circle.

At this time, as shown at 56, an error correction code is generated for the PCM multiplied signal written in the first and second areas in the previous rotation. PCM written in the fifth and fourth areas
For the double signal, an error correction code is similarly generated in one rotation.

After the error correction code is generated, the PCM signal and the error correction code are read out from the RAIld 21 at timing 59 and recorded on the a tape 1 at timing 40. The recording timing is determined based on the position detection signal 58. The position detection signal 58 is 00 for one rotation head.
The position t (the position at which the head A starts scanning the magnetic tape 1) is shown.

The servo circuit 13 controls the rotational phase of the rotary head 20 so that the fall of the reference signal 57 generated by the timing generation circuit 15 and the position detection signal 58 coincide. Then, the recording timing is determined based on the recording/reproduction address generation circuit 11''CtS position detection signal 58, and the RAM 2
1, the PGM signal and error correction code are read out.

This readout is performed at a frequency corresponding to the recording rate oscillated by the oscillation circuit 10. Note that the position detection signal S8
The position may be other than 00. Also, the timing 56 for generating the error correction code and the timing 59 for ejecting the bladder during recording partially overlap, but if the order in which the error correction code is generated matches the order in which the recording is performed, it will be recorded already at the time of recording. There is no problem because the generation of the error correction code for the P(l signal has been completed.

FIG. 5 shows the switching timing of the switching circuit 19, that is, the reading of the PGvi signal for recording and the error correction code and the N
This is the timing of switching between loading the 0 converter 25 into the RAM 21 and generating an error correction code. 41 is a control signal for the switching circuit 19, and 42 is a slot in section M. Here, when the control signal 41 is "1", the switching circuit 18 is selected and "
0'', the recording/reproducing address generation circuit 11 is selected. That is, in the slot 45, N converters 25 write to the RAM 21 and generate an error correction code.

Slot) 44T5 P from RAMz 1 for record of work
CM.

Reads signals and error correction codes.

FIG. 6 shows the switching timing of the switching circuit 18, that is,
This is the switching timing between writing from the Φ converter 25 to the RAM 21 and generation of an error correction code.

45 is a control signal for the switching circuit 80, which selects the input/output address generation circuit 17 when the signal is "0" and selects the correction address generation circuit 16 when the signal is "0". As mentioned above, the PcM signal may be written in 2 slots out of 64 slots. Regarding the slots 43, it is sufficient to perform them at a ratio of 2 out of 16 slots. In this example, 4 slots out of 16 slots are allocated to transfer the PCM signal from the AIDK converter 25 to the RAM 21 in consideration of the use during playback, which will be described later. The remaining 12 slots are used to generate error correction codes, that is, to transfer data between the RAM 21 and the error correction circuit 22.

FIG. 7 shows the operation timing of the interface circuit 6. 46 is the timing of recording data input to the recording circuit 5. The numbers indicate data numbers. The recording circuit 5 records data at a preset transmission rate.

The access speed of the RAM 21 is set to be at least twice the recording transmission rate.

In this embodiment, the recording transmission rate is approximately 1 MH2, and the access speed (5,072 Mi-1x) is approximately five times as high. In the interface circuit 6, the PL'M read from the RAM 21 in the slot 44
Data rates are exchanged so that the recording transmission rate matches the signal and error correction code.

FIG. 8 shows an example of fermentation of the interface circuit 6. 5
5 to 59 are latch circuits, and 60 is an AND circuit.

61 is an inverter. Also, 50 is RAIV121
51 is an input terminal for slot switching signal 41, 52 is an output terminal for read request signal, 55 is an output terminal for data to recording circuit 5, 54 is synchronized with the recording transmission rate. This is a clock input terminal. The operation of the interface circuit shown in FIG. 88 will be explained below according to the timing diagram shown in FIG. Latch circuit 56”(”)
X, the data is sequentially latched by the clock 66 inputted from the input terminal 54 and outputted from the output terminal 55. Therefore, when the latch circuit 56 latches, the reading is controlled so that the recorded data is being read from the RAM 21. When the data is latched by the latch circuit 56, the output signal 65 of the latch circuit 58 becomes 11". This output signal 65
is latched by the latch circuit 59, and the AND circuit 60 generates the latch clock 64 of the latch circuit 55 by logically adding the output of the latch circuit 59 and the slot switching signal 41 inputted to the input terminal 51J.

RA at the rising edge of latch circuit 551 and latch clock 64
Latch the data read from M21. 6S indicates the output of the latch circuit 55. When the data is latched by the latch circuit 55, the output of the latch circuit 57 becomes @1'' and the latch circuit 58 is cleared.

Set the output signal 65 to @0'. Also, latch clock 6
The read request signal 62 is inverted by the output terminal 52 and output from the output terminal 52. When the recording/reproduction address generation circuit 11 chain receives the continuous output request signal 62 and becomes 1-, it advances the address of the RAM 21 by one and reads the secondary data.
Read from AM21. In this way, the data rate conversion shown in FIG. 7 is performed.

As mentioned above, by allocating a dedicated RAM slot for reading the recorded signal during recording in the RAM 21, writing the PCM signal from the ~Φ converter, and adding an error correction code, it is possible to read the PCM signal with one system of RAM. Recording can be done.

Next, the case where reproduction is performed in the PCM signal recording and reproducing apparatus shown in FIG. 1 will be explained.

During playback, the switching circuit 5 is switched to the playback side by the recording/playback switching signal inputted from the input terminal 28, and the playback signal played back by the rotary head 2 is amplified and waveform equalized by the playback amplifier 7, and then The signal is input to the reproduction circuit 8.

Note that the recording/reproduction switching signal k''L, switching of the operation timing of the RAM 21, switching of the operation of the error correction circuit 22, and prohibition of the operation of the A/D converter 25 are also performed.

The reproducing circuit 8 demodulates the PCM signal and error correction code, and detects synchronization signals and side signals.

The PCM signal and error correction code demodulated by the reproducing circuit 8 are written into the RAM 21 via the interface circuit 9 and the pass line 20. The address of the RAM 21 at the time of writing is generated by the recording/reproduction address generation circuit 11 based on the block address in the synchronization signal and control signal detected by the reproduction circuit 8.

The PCM signal and error correction code written in the RAM 21 are read out according to the address generated by the correction address generation circuit 16, and are sent to the error correction circuit 2 through the path line 20.
2 and error correction is performed. error correction circuit 2
The PCM signal corrected in step 2 is again stored in RAM21 K @
be included.

The error-corrected PCM signal is read out from the RAM 21 according to the address generated by the input/output address generation circuit 17 and sent to the error correction circuit 25 through the path line 20.
is input. The error correction circuit 25 performs error correction such as average value interpolation, which replaces the error with the average value of the previous and subsequent values, and outputs it to the D/A converter 24. Then, the D/A converter 24 converts it into an analog signal and outputs it from the output terminal 27. In addition, the reproduced PCM
The signal can be sent directly to other PGs without converting it to an analog signal.
It may be output to M device.

Recording/reproduction address generation circuit 11. When generating addresses in the correction address generation circuit 16 and the input/output address generation circuit 17, the address generated during recording and the address generated during reproduction are the same, so the same circuit can be shared during recording and reproduction. .

Figure 10 shows signal reproduction, error correction and PCM during reproduction.
Indicates the timing of signal output.

70 is the reproduction timing from the magnetic tape 1, and 71 is the storage timing from the reproduction circuit 8 to the RAM 21.

72 is an error correction timing, and 75 is a read timing from the RAM 21 to the error correction circuit 25. Reproduction of signals from the magnetic tape 1 is performed in synchronization with the reference signal 57. Then, at timing 71, data is sequentially written into the first to fourth areas of the RAM 21.

RAM21K Corrects the written reproduction signal at timing 72''C*.Although the timing of the reproduction signal and the error correction partially overlap, the order of reproduction and the order of error correction are made to match. There is no problem if you leave it as is.The error-corrected PCM signal will be sent to the next rotating head.
It is output in rotation (560G).

The switching timing of the switching circuits 18 and 19 may be the same as that during recording. That is, in slot 45 of FIG. 5, error correction and PL, 'M times signal readout from RAM 21 to error correction circuit 25 is performed, and in slot 44, the reproduced signal is read out from RAM 2.
Write to 1. In the slot 45z family, as shown in FIG. 6, 4 of the 16 slots are used for reading the PCM signal, and 12 slots are used for transferring data between the RAM 21 and the error correction circuit 22 during error correction. The reading of the PCM signal is performed once, and the upper 8 bits and lower 8 bits of the 1 word 16-pit PCM signal and the 2 bits indicating whether the read PCM signal is incorrect or not are read.
Read the data of four flags. That is, the RAM 21 is accessed four times in one read.

FIG. 11 shows the operation timing of the interface circuit 9. 74 is the timing of the playback data output from the playback circuit 8, and the playback transmission rate is about I as during recording.
It is MHz. As shown in FIG. 11, during playback, the reverse conversion of the conversion shown in FIG. 7 during recording is performed.

FIG. 12 shows an example of the configuration of the interface circuit 9. 84
88 is a latch circuit, and 89 is a buffer. Also, 8
0 is an input terminal for the reproduced data 74 output from the reproduction circuit 8, 81 is an input terminal for a reproduced clock synchronized with the reproduced data, 82 is an output terminal for data to the RAM 21, and 83 is an input terminal for the slot switching signal 41. be. Below, the 15th
The operation of the interface circuit shown in FIG. 12 will be explained according to the timing diagram shown in the figure. The latch circuit 84 latches the reproduced data 74 input from the input terminal 80 with the reproduced clock 90 input from the input terminal 81. Reference numeral 91 indicates the output of the latch circuit 84. When the latch circuit 84 latches the data, the output signal 92 of the latch circuit 86 is 1.
This output signal 92 is latched by the slot switching signal 41 in the latch circuit 88, and the latch clock 95 of the latch circuit 85 is generated by ANDing the output of the latch circuit 88 and the slot switching signal 41 in the AND circuit 60. .

Reference numeral 94 indicates the output of the latch circuit 85. When the data is latched by the latch circuit 85, the output of the latch circuit 87 becomes mis, clearing the latch circuit 86, and outputting the signal 9.
2 to 10″″. The buffer 89 outputs the reproduced data latched in the latch circuit 85 from the output terminal 82 to the RAM 21K when the slot switching signal 41 is "0", that is, when the slot 44 is set. Performs the indicated data rate conversion.

As mentioned above, the R
By assigning AM slots, one system of RAM can
CM signals can be reproduced. Furthermore, the key address generation circuit can be shared during recording and reproduction.

Note that the switching circuits 18 and 19 may be a single five-man switching circuit.

FIG. 14 shows an embodiment of the PcM signal reproducing device of the present invention. The operation is the same as when reproducing the circuit of FIG. That is, by removing the recording circuit and N converters from the PCM signal recording/reproducing apparatus shown in FIG. 1, a reproduction-only circuit can be constructed.

Furthermore, the recording-only circuit can be configured similarly by removing the reproducing circuit, error correction circuit, and D/A converter.

FIG. 15 shows an embodiment in which subcodes such as time codes are recorded and reproduced in addition to PCM signals in the PL and 'M signal recording and reproducing apparatuses of the present invention. 100 is a subcode address generation circuit, 101 is a switching circuit, and 102 is a subcode input/output circuit.

During recording, a subcode is input from the input/output terminal 105 and written to the RAM 21 via the subcode input/output circuit 102. The write address at this time is subcode address generation port 1! Generated by %11. and,
It is read out from the RAM 21 and recorded on the magnetic tape 1 together with the PCM signal and error correction code. RA of subcode
Writing to M21 can be done by using the vacant time of the slot 44. Slot 444! Although it is used for successively outputting data from the RAM 21 to the recording circuit 5, reading is not performed during the period 9000 when the head A or B is not in contact with the magnetic tape 1. Therefore, the subcode can be written into the RAM 21 during this time. 16th
The figure shows the timing of subcode input. 10
4 is a switching circuit 1010 control signal. control signal 104
When the control signal 104 is @0'', the switching circuit 101 selects the recording/reproducing address generation circuit 11 to record data, and when the control signal 104 is @1m, the switching circuit 101 selects the subcode address generation circuit 100, Subcode 7N
21.

During playback, KfB is used together with the PCM signal and error correction code.
The subcode reproduced from the tape 1 and stored in the RAM 21 is read out using the address generated by the subcode address generation circuit 100 and outputted from the input/output terminal 105 via the 1st subcode input/output circuit 102. The reading timing of the subcode may be determined by using the vacant time of the slot 44, as in the case of recording.

Although a dedicated area may be used as the area for storing subcodes in the RAM 21, it is also possible to use an area for storing error correction codes (
You can also do S. For example, when recording and reproducing are performed using the first or second area of the RAM 21, the PL'M signal is input or output in the fifth and fourth areas. That is, in the fifth and fourth areas, the PCM signal before adding the error correction code is written, but the PCM signal after error correction is read out. Therefore, there is no problem even if the subcode is stored in the area for storing the error correction code in the fifth or fourth area. By doing so, subcodes can be stored without increasing the storage capacity of the RAM 21.

Note that the switching circuits 18, 19, and 101 of the circuit shown in FIG. 15 may be replaced by a single switching circuit operated by four people.

As described above, according to the circuit shown in FIG.

PCM signal and PCM signal at the same time by only one system
Subcodes such as time codes related to the double signal can also be recorded and reproduced.

〔Effect of the invention〕

According to the present invention, it is possible to record and reproduce PCM signals using one system of RAM. It can also support recording and reproduction of subcodes.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the PCM signal recording and reproducing apparatus of the present invention, FIG. 2 is a recording pattern diagram on a magnetic tape, and FIG.
The figure is a block diagram, and Figure 4 is a timing diagram during recording.
5 is a timing diagram of the switching circuit 19, FIG. 6 is a timing diagram of the switching circuit 18, FIG. 3387 is a diagram showing data conversion of the interface circuit 6, and FIG. 8 is a diagram showing an example of one-time purchase of the interface circuit 6. , Figure 9 is a timing diagram of the circuit in Figure 8, Figure 10 is a timing diagram during playback, and Figure 1 is a timing diagram of the circuit in Figure 8.
1 is a diagram showing data conversion of the interface circuit 9,
12 is a diagram showing an example of the configuration of the interface circuit 9, FIG. 15 is a timing diagram of the circuit shown in FIG.
4 is a block diagram of one embodiment of the PCM signal reproducing device of the present invention, FIG. 15 is a block diagram of another embodiment of the PCM signal recording and reproducing device of the present invention, and FIG. 16 is a block diagram of the circuit of FIG. 15. FIG. 4 is a timing chart during recording. 5... Recording circuit 6.9... Interface circuit 8... Playback circuit 10.14... Shooting circuit 11... Recording and playback address generation circuit 15... Timing generation circuit 16... Correction address Generation circuit 17... Input/output address generation circuit 18.19... Switching circuit 21... Rib N 22... Error correction circuit 25... Error correction circuit 24... D/A converter 25. ...~Φ converter 100... subcode address generation circuit 101...
switching circuit

Claims (1)

[Claims] 1. A recording and reproducing circuit that records and reproduces a PCM signal, an error correction code that corrects errors in the PCM signal, and a signal related to the PCM signal on a recording medium, and a PCM signal and error correction code to be recorded and reproduced. A PCM signal recording/reproducing device comprising a memory circuit for storing data, an address control circuit for controlling addresses during writing and reading of the memory circuit, and a correction circuit for generating an error correction code during recording and correcting errors during playback. In the apparatus, the address control circuit controls the PC during recording and reproduction.
A recording/reproduction address generation circuit that generates a read or write address for the M signal, a correction address generation circuit that generates an address for transferring data between the correction circuit, and a write or write address for input/output of the PCM signal. An input/output address generation circuit that generates a read address and an address generated by the recording/reproduction address generation circuit are output when an even or odd numbered access is made to the storage circuit to generate a PCM signal and a PCM signal in the storage circuit for recording and reproduction. The error correction code is read or written, and when the memory circuit is accessed at an odd or even number, the address generated by the correction address generation circuit and the input/output address generation circuit is outputted to connect the memory circuit and the correction circuit. 1. A PCM signal recording and reproducing device, characterized in that it is provided with an address switching circuit for transferring data between and inputting and outputting PCM signals. 2. In the PCM signal recording and reproducing apparatus according to claim 1, further subcode address generation for generating an address for writing or reading from the storage circuit when inputting/outputting a subcode related to the PCM signal. and an address generated by the subcode address generation circuit is outputted to the storage circuit when recording and reproduction is not performed in an even numbered or odd numbered access. 1. A PCM signal recording/reproducing device comprising an address switching circuit for inputting and outputting subcodes by outputting them to a circuit. 3. In the PCM signal recording and reproducing apparatus according to claim 1 or 2, the access cycle of the storage circuit is set to be at least twice the transmission rate during recording and reproducing. Device.