JPH0563860B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to address signals and additional information signals corresponding to each block of a rotary head PCM recorder, and particularly to reducing redundancy for each block and arranging additional information signals within blocks. The present invention relates to a data formation method suitable for.

Converts analog signals to digital signals, records and reproduces these digital signals on recording media.
PCM recorders can achieve dramatic improvements in sound quality compared to conventional analog audio recorders. However, on the other hand, the amount of information transmitted is approximately 50 times that of the analog method, and when magnetic tape is used as the recording medium, the number of tracks must be increased, or
As with the rotating head system, it is necessary to increase the amount of information transmitted per unit time by increasing the relative speed between the tape and the head. at present,
There are two types of PCM recorders: a fixed head type with multitrack and a rotating head type.In order for PCM recorders to become popular among general users, it is necessary to lower the price, reduce running costs, and increase the number of functions. The rotary head type has many possibilities when considering the One of the functions that can be realized with a rotating head type but is difficult to realize with a fixed head type is an address search function in double speed mode. This function adds a specific address number to each block of PCM data, displays the song position in blocks during normal playback, and at the same time finds a specific address in double speed mode.

In a rotating head PCM recorder, a PCM signal is divided into several symbols (1 symbol = 8 bits), for example, 12 symbols, and these several symbols are treated as one block. Then, several blocks, for example 128 blocks, are recorded on one track.

Figure 1 shows the block configuration of a rotary head PCM recorder. 1 is a synchronization signal and serves as a reference when reproducing data. 2 is a control signal that records information related to the PCM signal. 3 is a PCM signal, and 4 is a parity for performing error detection and correction. The control signal must record the information necessary to correctly reproduce the PCM signal.

FIG. 2 shows an example of the structure of the control signal. Reference numeral 5 indicates an inter-song signal, which is, for example, "0" during a song and "1" between songs. This signal is used for finding the beginning of a song or for random song selection. 6 is information related to the PCM signal,
These include sampling frequency, number of quantization bits, quantization method (linear quantization, linear compression, etc.), analog characteristics (emphasis, noise reduction, etc.), dubbing prohibition code, mute signal, signal type, etc. Approximately 24 bits are required to record this information in BCD code. Reference numeral 7 denotes a track identification signal, which is used to detect when a track jump occurs during playback. This signal requires about 4 bits. 8 is a block address, which is a signal for preventing interleaving deviation during reproduction. When recording 128 blocks on one track, 7 bits are required.

In this way, the control signal requires about 36 bits, but this is a PCM signal (12 symbols = 96 bits).
This increases the redundancy level to 40%.

An object of the present invention is to provide a method for recording additional information that has little redundancy and is easy to detect.

The present invention is a data recording method in which a control signal is composed of a plurality of blocks of data and a plurality of control signals are multiplexed and recorded on one track, thereby reducing redundancy and facilitating detection.

An embodiment of the present invention will be described below with reference to FIGS. 3 and 4.

FIG. 3 shows the structure of the control signal of the present invention. The control signal consists of 16 bits. The inter-track signal 5, track identification signal 7, and block address 8 are the same as in FIG. It is preferable to add the inter-song signal 5 to each block in order to facilitate detection at the time of random access. Also, it is naturally necessary to add a track identification signal 7 and a block address 8 to each block. On the other hand, it is sufficient to add the PCM signal 6 on a track-by-track basis. Therefore, as shown in FIG. 4, information is expressed using 32 blocks of second bits, that is, 32 bits. Furthermore, PCM signal information 6 is 0 to 31 blocks, 32 to 63 blocks, 64
The same information is overwritten in four locations: ~95 block and 96~127 block.

FIG. 5 shows the structure of 32-bit PCM signal information. 6-1 is the sampling frequency, 6-2 is the number of quantization bits, 6-3 is the linear/non-linear display of the quantization method, 6-4 is the presence or absence of emphasis, 6-5 is the dubbing prohibition code, 6-6 is a miute signal, 6
-7 is the type of signal, and 6-8 is parity for error detection. Of course, the information 6-1 to 6-7 may have other configurations. Furthermore, the error detection parity 6-8 can be made 8 bits and 24 bits of information can be stored therein. In this way, by representing information by combining the signals of multiple blocks, PCM signal information 6
The number of bits can be reduced. Furthermore, by adding parity for error detection, malfunctions due to data errors can be prevented.

As mentioned above, the PCM signal information 6 is multiplexed at four locations on one track. Thereby, even if part of the reproduction signal is lost due to scratches or the like on the tape, the information can be reproduced correctly.

Other information is recorded in the third and fourth bits. By representing the information in several blocks, a large amount of information can be recorded in this portion as well.

FIG. 6 shows a rotary head PCM recorder for recording control signals according to the present invention. 13 is a synchronization signal generation circuit, 14 is a control signal generation circuit, 15 is a timing generation circuit, 16 is an A/D conversion circuit, 17 is a signal processing circuit, 18 is a signal switching circuit, and 19 is a recording circuit.

Two-channel audio signals inputted from input terminals 11 and 12 are converted into PCM digital signals by an A/D conversion circuit 16. and,
A signal processing circuit 17 adds interleave and parity signals.

The control signal is generated by the control signal generation circuit 14. 21 is an inter-song signal generation circuit, which generates an inter-song signal 5; 22 is a PCM signal information generation circuit, which is composed of a 32-bit shift register. The shift register has the values shown in Figure 5.
Load 32-bit data. The input and output of the shift register are connected, and data is circulated by shifting. When recording a control signal, it is recorded in each block by shifting this shift register at the block period.
PCM signal information 6 can be generated. 23
and 24 are circuits that generate information to be recorded at 9 and 10 in FIG. 3, and the PCM signal information generation circuit 22
Performs the same operation as .

During recording, the synchronization signal 1 generated by the synchronization signal generation circuit, the signal generated by the control signal generation circuit 14, the track identification signal and block address generated by the timing generation circuit 15,
The PCM signal and parity generated by the signal processing circuit 17 are sequentially switched by the signal switching circuit 18 to generate one block of data shown in FIGS. 1 and 3. The signal is then converted into a predetermined signal by the recording circuit 19, and recorded on the tape 26 by the head 25 on the cylinder.

FIG. 7 shows another embodiment of the invention. In FIG. 7, the control signal is composed of 8 bits, and FIG. 7A is the control signal for even blocks, and FIG. 8 is the control signal for odd blocks. The first bit of the control signal indicates whether it is an even block or an odd block; if it is "0", it is an even block;
If it is "1", it is considered an odd block. In the even-numbered block in FIG. 7A, the block address is recorded in the remaining 7 bits. Naturally, it is not necessary to record the least significant bit of the block address. In the odd-numbered blocks in FIG. 7B, the second bit is the inter-track signal 5, the third bit is the PCM signal information 6, the fourth bit is other information 9, and the fifth to eighth bits are the track identification signal 7. The PCM signal information 6 and other information 9 represent one piece of information in 32 blocks as in FIG. In this case, there are 64 odd blocks, so double writing is performed. In addition, the number of multiple writes is
It can be arbitrarily determined depending on the number of blocks and the amount of information. For example, if one track is composed of 240 blocks, the PCM signal information can be expressed in 40 bits and triple-written.

FIG. 8 is a rotary head PCM recorder recording the embodiment of FIG. The control signal input to the signal switching circuit 18 is switched by the least significant bit of the block address generated by the timing generation circuit 15. That is, the signal switching circuit 27
Then, the least significant bit of the block address is “0”
In the case of ``1'', the block address excluding the least significant bit is selected, and in the case of ``1'', the output of the control signal generation circuit 14 and the track identification signal generated by the timing generation circuit 15 are selected. The output of the signal switching circuit 27 and the least significant bit of the block address constitute a control signal.

As described above, the number of bits of the control signal can be reduced by representing information that needs to be recorded in units of tracks by several blocks of control signals. Furthermore, by overwriting information expressed in several blocks multiple times in one track, it is possible to cope with missing reproduced data due to scratches on the tape or the like.

According to the present invention, information related to a PCM signal can be recorded in a small capacity, and even if a reproduction signal is missing, the information can be easily reproduced.

[Brief explanation of the drawing]

Fig. 1 shows the block configuration of the rotary head PCM recorder, Fig. 2 shows the control signal structure, Fig. 3 shows the control signal structure of the present invention, Fig. 4 shows the data structure of one track, and Fig. 5 shows the present invention. PCM signal information configuration,
FIG. 6 shows an embodiment of a rotary head PCM recorder, FIG. 7 shows another embodiment of the control signal structure of the present invention, and FIG. 8 shows another embodiment of a rotary head PCM recorder. 1...Synchronization signal, 2...Control signal, 3...
PCM signal, 4... Parity, 5... Inter-song signal,
6...PCM signal information, 7...Block address,
8... Track identification signal, 13... Synchronization signal generation circuit, 14... Control signal generation circuit, 15... Timing generation circuit, 17... Signal processing circuit, 18...
...Signal switching circuit, 21...Song signal generation circuit, 2
2...PCM signal information generation circuit, 27...signal switching circuit.

Claims (1)

[Claims] 1. A synchronization signal, a control signal related to the PCM signal, and a parity signal for error detection and correction are added to 1 m PCM signals to form one block, and n blocks of signals are recorded on a magnetic tape. In a rotary head PCM recorder that records on one track, information is composed of n 1 bits or n ₁ × k bits, in which the control signal of ₁ bit or k bits is grouped into n ₁ blocks where n = n ₁ × n ₂ . , above n ₁ bit or n ₁ ×k
A data recording method characterized by recording bit information n ₂ times on one track. 2. In the data recording method according to claim 1, n ₃ bits or n ₃ × k bits of the information of n ₁ bits or n ₁ × k bits are taken as actual information, and (n ₁ − n ₃ ) bits or (n ₁ -n ₃ )×k bits as an error detection signal.