JP2822186B2 - Digital signal recording / reproducing method - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a recording / reproducing method of a digital signal, and more particularly, to recording of a digital signal to which a block synchronization signal and a block address are assigned for each block composed of a plurality of words. Reproduction method.

[Summary of the Invention]

The present invention relates to a method of recording and reproducing a digital signal to which a synchronization signal and an address are assigned for each predetermined word of digital data, wherein an address signal from a reference address generating means is compared with the reproduced synchronization signal and address. By shifting the recording timing of the digital signal according to the amount of shift between them, the continuity of the signal in the signal rewritten portion by editing or the like is improved.

[Conventional technology]

When recording or reproducing or transmitting a digital signal such as an audio PCM signal, it is necessary to determine a format including a sampling frequency, the number of bits of a sample, and the like in advance.

For example, the present applicant has previously disclosed in Japanese Patent Application Laid-Open Nos. 57-36410 and 59-104714 a so-called DASH as a fixed-head audio PCM signal recording system for business use.
A method is proposed. In this audio PCM signal recording system, 32 kHz, 44.1 kHz, 48
It has a format corresponding to a sampling frequency of kHz, and the recording pattern on the tape includes a plurality of (8 to 48) digital audio tracks, two analog audio tracks, and one for each. The time code track and the control track of the book are formed along the tape running direction. The audio data is divided into blocks each having a predetermined number of samples (for example, 12 samples). Each block is provided with a block address and recorded on the digital audio track together with a block synchronization signal and the like. I have.

By the way, in a digital VTR (video tape recorder) for recording and reproducing a digital video signal on a magnetic tape, an audio signal is also digitally recorded. For example, the present applicant has previously disclosed in Japanese Patent Application Laid-Open No. 62-199179 a VTR for digitally recording a so-called high-definition television signal. In this prior art, three examples of audio signal recording modes are shown. In addition to these modes, the tape running speed of the digital recording VTR of this high-definition television signal is relatively high (about 805 mm).
/ s), digital recording of an audio signal by a fixed head using the so-called DASH format has been considered.

[Problems to be solved by the invention]

Here, when the fixed head digital audio signal recording method is applied to VTR audio recording,
When the digital audio signal is edited with the tracking of the head for the video track adjusted or using a VTR different from that used for recording,
At the edit point, the data blocks may not be connected consecutively, and the value from the internal block address counter operating in a flywheel manner may not match the reproduced block address. If the data blocks are not consecutive normally as described above, several blocks of data will be rejected before the operation recovers during playback, and errors that cannot be corrected by considering ordinary random errors will be considered. It is likely to be.

The present invention has been made in view of such circumstances, and can prevent signal discontinuity caused by rewriting a signal such as editing after performing tracking adjustment or using a VTR different from that at the time of recording. And a method for recording and reproducing digital signals.

[Means for solving the problem]

According to the digital signal recording / reproducing method of the present invention, in order to solve the above-mentioned problems, a synchronizing signal and an address are provided for each predetermined word of digital data in correspondence with a digital signal recorded / reproduced by a rotary head. In a digital signal recording / reproducing method for recording / reproducing a digital signal with a fixed head, a reference address generating means for generating a reference address in accordance with the digital signal reproduced by the rotary head. Comparing the address signal with the synchronization signal and address of the digital signal reproduced by the fixed head to detect a shift amount, and controlling the recording timing of a digital signal to be newly recorded by the fixed head according to the shift amount; It is characterized by.

(Operation)

For a digital signal to be newly recorded (rewritten) by the fixed head, a reference address signal from a reference address generating means for generating a reference address in accordance with the digital signal reproduced by the rotary head, By comparing the synchronization signal and the address of the reproduced digital signal to detect the amount of deviation, and controlling the recording timing of the digital signal to be newly recorded by the fixed head according to the amount of deviation, the already recorded signal is controlled. Can be maintained.

〔Example〕

Hereinafter, as a preferred embodiment of the digital signal recording / reproducing method according to the present invention, a method for recording / reproducing an audio PCM signal by a fixed head will be described with reference to the drawings.

FIG. 1 shows a recording / reproducing circuit system for realizing a recording / reproducing method of a digital audio signal according to one embodiment of the present invention, and a VTR (VTR) for digitally recording / reproducing a so-called high definition television signal. 2 shows an example of a circuit configuration applied to audio PCM signal recording and reproduction in a video tape recorder). In the signal format of this recording / reproducing method, a digital audio signal is divided into blocks each having a predetermined number of words, error correction coding is performed using the blocks as delay units for interleaving, and one block (recording block) of the recording format is formed. An address (block address) is assigned to each of these recording blocks.

In the first view, the reproducing head AH _P1 ~AH _P8 of example eight channels audio PCM signals of a magnetic tape (video tape) 8 audio tracks, as shown in example FIG. 2 recorded formed on MT Each of T _{A1 to} T _A8 is scanned. That is, in FIG. 2, the eight audio tracks T _{A1 to} T _A8 are recorded and formed in parallel to each other along the tape running direction (the direction of arrow A) of the magnetic tape MT. recording track (video track) T _V high-definition television video signal is recorded and formed as a plurality of tracks parallel to each other obliquely with respect to the tape MT by the rotary head. The direction of arrow B in the figure indicates the running direction of the rotating video head with respect to the magnetic tape MT. Further, on the magnetic tape MT, a time code track _TTC , a control track _TCTL, and a cue track _TQ are provided along the tape running direction (the direction of arrow A).

In Figure 1 again, the signal from the reproducing head AH _P1 ~AH _P8 digital audio signal is sent to the demodulation circuit section (LSI) 12 through a reproducing equalizer circuit 11, a predetermined modulation scheme (e.g. HDM- Processing such as signal demodulation of one modulation scheme, CRCC check, and synchronization separation is performed. A memory 13 is connected to the demodulation circuit section 12. The demodulated digital signal from the demodulation circuit section 12 is subjected to error correction decoding processing by a memory (RAM) 14 and a parity check correction circuit 15 of a deinterleave processing circuit, and is input to an input / output control circuit section 20 via a latch circuit 16. Sent to In the demodulation circuit section 12, a block address of a recording block as described later is also reproduced, and the reproduced address is sent to a comparison circuit 17 where the count value from a so-called flywheel counter 18 is compared. Flywheel counter 18
Is a flywheel type block address counter, which is used to maintain the continuity of the reproduction address. That is, data writing to the deinterleaving memory 14 is performed using the reproduction address. Therefore, when the reproduction address cannot be obtained due to dropout or the like, the data from the flywheel counter 18 is not read. The output is sent to the write address control circuit 19W so that it is written to an appropriate address in the memory 14. The data written in the memory 14 is read-controlled by the read address control circuit 19R. The digital audio signal supplied to the input / output control circuit unit 20 is subjected to processing such as level adjustment, delay, interpolation, and mute, and is taken out as an input to a DA converter or as a digital out as it is.

A digital audio signal such as an AD converter output or a so-called digital-in input is used as an audio signal to be recorded.
The digital audio signal is sent to a memory (RAM) 22 and a parity addition circuit 23 of an interleave processing circuit via a latch circuit 21 to be subjected to error correction coding processing. Here, data writing to the interleaving memory 22 is performed by the write address control circuit 24W, and data reading from the memory 22 is performed by the read address control circuit 24R. The data read from the interleave memory 22 is sent to the modulation circuit 26 via the synchronization signal word and CRCC word addition circuit 25. In the modulation circuit 26, a signal is modulated based on a predetermined modulation method, for example, a so-called HDM-1 modulation method, and is sent to a pulse train recording reordering memory (RAM) 31 for pulse train recording to be described later. Data conversion is performed. Data is written to the memory 31 by a write address control circuit 32.
W is performed, and data read from the memory 31 is performed by the read address control circuit 32R. The data read from the pulse train type recording rearrangement memory 31 is passed through a head drive circuit 33, for example, to a digital audio signal recording head AH _R1 for eight channels.
Sent to ~AH _R8, it is recorded and formed as an audio track T _A1 through T _A8 of FIG. 2 in a magnetic tape (video tape) on MT.

Incidentally, and adjusted for tracking state of the rotary head relative to the video track T _V of FIG. 2 (a so-called tracking adjustment), in such a case where the recording VTR and the reproducing VTR are different, the vertical synchronizing signal and the length of the reproduced video signal In some cases, the correspondence with the content of the reproduction signal of the directional tracks (audio tracks T _{A1 to} T _A8 ) is reproduced with a deviation from the correspondence at the time of the original recording.

That is, for example, the magnetic tape on which the digital audio signal shown in FIG. 3B is recorded corresponding to the vertical synchronization signal of the video signal shown in FIG. Reproduction at a later time may cause a shift as shown in FIG. 3C, for example. The numbers attached to the digital audio signals in FIG. 3 indicate the addresses of the respective recording blocks as described later. Considering the case where a new digital audio signal is recorded (rewritten) on a magnetic tape by editing or the like when such a deviation occurs, the newly recorded digital audio signal is a video signal. Above vertical synchronization signal (FIG. 3A)
Is obtained by signal processing based on
Each recording block is as shown in FIG. 3D obtained at the same timing as each recording block of the digital audio signal shown in FIG. 3B. If the digital audio signal of FIG. 3D is recorded as it is, the continuity of the recording block with respect to the previously recorded signal is disturbed as shown in FIG. 3E. In this case, the shift in recording block units can be corrected relatively easily by shifting the block address or the like, but it is difficult to correct any component shorter than the recording block.

For this reason, in the embodiment of the present invention, the deviation or difference between the reference block address (FIG. 3B) and the reproduced block address (FIG. 3C) is determined by the segment length shorter than the recording block length. The error is detected in units, for example, 1/36 of one block, and this shift or difference is corrected in the process of signal processing at the time of recording. As a method of this correction, for example, digital audio data is written into an interleave memory for error correction processing,
A method of controlling the amount of delay when reading is considered,
In the present embodiment, the shift or difference is corrected by controlling writing and reading to and from the pulse rearrangement recording reordering memory 31.

That is, for example, a reference block address signal from a circuit 34 for generating a reference block address according to a video vertical synchronization signal and a reproduction block address signal from the demodulation circuit section 12, and a reproduction block By sending the synchronization signal to the shift amount detection circuit 35, the shift amount (or difference) of these address signals is extracted in segment units shorter than the recording block length (for example, 1/36 unit of one block). This shift amount is
For example, the pulse-train-type recording rearrangement memory
By being sent to the read address control circuit 32R of 31,
The data is read from the memory 31 with the deviation between the reproduction address and the reference address corrected.

Prior to the specific description of the block shift correction operation, a data format for recording and reproducing the audio PCM signal by a fixed head will be described in the fourth section.
This will be briefly described with reference to FIGS.

First, in FIG. 4, a digital signal is generated for three field periods (three vertical periods) of the high-definition television signal.
50 large blocks of audio data are allocated, and 48 samples of 20-bit word length are allocated in one large block. That is, there are 800 samples per field for 2400 samples in three fields, and the field frequency of a high-definition television signal is 60 Hz, so the sampling frequency of the audio signal is 48 kHz. The one large block is composed of five blocks, and each block is composed of 12 symbols of 16-bit data of one symbol. Here, five consecutive blocks in the large block are sequentially replaced with blocks 0 to 0.
When the data of the 48 samples are sequentially set to D0 to D47, the upper 16 bits of the sample data D0 to D47 are stored in the first four blocks 0 to 3 (12 × 4 = 48 symbols). The lower 4 bits of the sample data D0 to D47 are sequentially arranged in the last block 4. Thus, the sample data having a word length of 20 bits is divided into upper 16 bits and lower 4 bits,
The upper 16 bits of 48 samples are allocated to 48 symbols of 4 blocks in the large block of 60 symbols, and the lower 4 bits of 48 samples are allocated to 12 symbols of the remaining 1 block. Then, error correction coding is performed on each symbol of the data format having such a structure, using the one block as a delay unit of the interleave processing.

The error correction encoding process in this case will be described.
The 12 symbols for one block shown in FIG.
(1) to W (12), these 12 symbols are first converted into odd-numbered words W (1), W (3),..., W (11) and even-numbered words W (2), W ( 4),..., W (12), and the first parity word P ₁ for each sequence.
And generates added P _2. Next, after applying a predetermined delay to each of the data of the odd and even data series and performing an interleave process, the second parity word Q ₁ and the second parity word Q ₁
Generate and add Q ₂ respectively. Furthermore, a predetermined delay is applied to each data, and a delay interleave process is performed between the odd-numbered sequence and the even-numbered sequence to obtain a data sequence that has been subjected to the error correction coding process. The output data that has been subjected to the error correction coding processing is added with P and Q parities for both odd-numbered and even-numbered data sequences, and has eight symbols, that is, 1 symbol.
There are 16 symbols per block.

Next, when actually recording the output data (16 symbols) corresponding to one block after the error correction coding processing is performed, a recording block as shown in FIG. 5 is formed. That is, at the beginning of the recording block, 16
A synchronization signal word corresponding to bits is arranged, and even-numbered data and odd-numbered data are alternately arranged in order. The P and Q parities are arranged at respective positions of the center four symbols of the block. Has been arranged. The order of the 16 symbols of the data and parity part between this synchronization signal word and the error check code CRCC is It has become. In these formulas It is. Here, for example, information of an address (block address) for each block is provided in the synchronization signal word.

Next, the pulse train recording will be briefly described. In the pulse train recording, when recording signals of a plurality of channels on parallel tracks, one bit of a recording signal is time-divided by the number of channels in order to eliminate mutual interference (crosstalk) between adjacent tracks. A signal current flows. Therefore, for example, an information signal that is time-divided in block units like a signal A in FIG. 6 needs to be channel-time-divided in bit units like a signal B. Such a data rearrangement operation is performed by the pulse train system recording rearrangement memory 31.
And peripheral circuits. FIG. 6 shows an example of time-division processing for eight channels (ch1 to ch8). A period in which blocks for the eight channels are combined is composed of 288 bits of 18 words from a synchronization signal word to a CRCC word. The signal A, in which the recording blocks are composed of 288 × 8 = 2304 bits for eight channels, is rearranged into a time-division channel-by-bit form to form a signal B of 8 × 288 = 2304 bits.

In this embodiment, the deviation between the reference address and the reproduction address is corrected in accordance with the data rearrangement for the pulse train recording, and a specific example of this correction operation is shown in FIGS. This will be described with reference to FIG. That is, FIG. 7 shows the read address control circuit 32R, the write address control circuit 32W and the shift amount detection circuit 35 of the pulse train type recording reordering memory 31 shown in FIG.
FIG. 8 shows a time chart for explaining the operation.

First, in FIG. 7, a write address and a read address for the pulse train type recording reordering memory 31 are supplied via a write / read selector 41. The output from the write address counter 42 is supplied to the write address input terminal of the write / read selector 41, and the read address
The output from the counter 43 is supplied via an adder 44. The adder 44 is constituted by, for example, an addition ROM, and is supplied with data on the amount of deviation between the reference address and the reproduction address, and adds the data to the output from the read address counter 43. If only the data rearrangement operation is performed, the storage capacity of the memory 31 is 4608 bits for two blocks (that is, one recording block).
(2 times 2304 bits for 8 channels of 288 bits) is sufficient. In order to simultaneously perform the block shift correction accompanying the tracking adjustment and the like described above, a capacity for, for example, 16 blocks is provided. This is because a block shift caused by the above-described tracking adjustment or the like is at most a few blocks, and it is sufficient if a range of ± 7 blocks can be specified. Therefore, 16 blocks can be specified. Four bits are required. Since 12 bits are required to specify the 2304 bits, the output address data of each address counter 42, 43 requires 16 bits (A _{0 to} A ₁₅ ). That is, in the write address counter 42, the 16 blocks higher 4-bit addresses A ₁₂ to A ₁₅ for the specified time-division channels (8 channels) middle 8-bit address for the specified A ₉ to A _11, 1 The lower 9-bit addresses A _{0 to} A ₈ are respectively assigned for the designation of 288 bits in the recording block, and the read address counter 43 records the upper 4-bit addresses A _{12 to} A ₁₅ for the above 16 block designation, 1 recording In the block
Middle 9-bit address of 288 bits for the specified A ₃ ~A _11,
The lower 3-bit address A ₀ ~ for the specified time-division channel
A ₂ is assigned to each. Read address counter
Of the 16-bit output data from 43 (addresses A _{0 to} A ₁₅ ), the upper 10 bits (the upper 4 bits for the block designation, the addresses A _{12 to} A ₁₅ and the upper 6 bits of the middle 9 bits for the bit designation) The addresses A _{9 to} A ₁₁ ) are sent to the adder 44 and added to the 10-bit shift amount data. The 10-bit added data and the read address counter 43 are added.
Lower remaining six bits of the 16 bit out with (the bit lower 3-bit address specified for middle 9 bit A ₃ to A ₈ and the channel designation for the lower 3-bit address A ₀ to A ₂₎ of the Read address data is formed. In this case, for the 10-bit shift amount data, data of the corresponding channel is supplied each time the time-division channel is switched.

The components corresponding to the shift amount detection circuit 35 in FIG. 1 for obtaining such shift amount data include a difference calculation circuit 51 and a block for calculating the shift between the reference address and the reproduction address in block units. The main component is a small displacement detection circuit 52 for detecting components shorter than the length in units of the segment (for example, 1/36 block). The outputs from these circuits are combined and sent to a displacement output circuit 53. The shift amount data is sent to the adder 44 in accordance with the rewriting operation accompanying the editing or the like described above. That is, the difference calculation circuit 51 is supplied with the reference block address signal from the reference block address generation circuit 34 shown in FIG. 1 and the reproduced block address signal from the demodulation circuit section 12 and calculates the address values of these. Output difference data (in blocks). The difference data in block units is
As described above, since it is enough to address the range of ± 7 blocks, the range is set to 4 bits. The output data from the small deviation detecting circuit 52 needs 6 bits because the segment is 1/36 of one block.
The bits are arranged on the upper side, and a total of 10 bits of shift amount data are sent to the shift amount output circuit 53.

Here, the operation of detecting the amount of deviation in the unit of a segment in the minute deviation detecting circuit 52 will be described with reference to FIG.

First, FIG. 8A shows segments obtained by dividing the block period BLK into 36, and these 36 segments are sequentially assigned addresses 0 to 35, respectively. This segment address is stored in the read address counter 43
This is an address specified by the upper 6 bits (A _{6 to} A ₁₁ ) of the above 9 middle bits of the 16-bit output data (addresses A _{0 to} A ₁₅ ).
A _{6 to} A ₁₁ are count data that repeats at 36 of 64 (= 2 ⁶ ) counts. In order to correct the shift amount in units of such a segment, the first
The reproduced block synchronization signal (see FIG. 8B) obtained from the demodulation circuit unit 12 shown in the figure is used. This playback block synchronization signal is output for each corresponding channel in FIG. 8c obtained by time-dividing the above-mentioned segment in the channel. In the example of FIGS. It is output at the position of bit address value 0). If a deviation occurs due to the tracking adjustment or the like, the output timing of the reproduced block synchronization signal in FIG. 8B moves within a range of up to several blocks in segment units. Next, FIG. 8D shows addresses corresponding to FIG. 8C, and 3-bit address values 0 to 7 are assigned to the respective channels ch1 to ch8 in FIG. 8C. This is an address corresponding to the lower three bits (A _{3 to} A ₅ ) of the middle nine bits in the 16-bit output data from the read address counter 43. Then, the 6-bit address (A _{6 to} A ₁₁ ) shown in FIG. 8A is supplied to the data input terminal D for a memory such as a RAM as the minute displacement detecting circuit 52, and with 3-bit addresses shown in FIG. 8 d (a ₃ ~A ₅₎ is supplied by the block synchronization signal is supplied as shown in the FIG. 8 c to the write signal input terminal WE, time division 8 The segment address at the time when the block synchronization signal is obtained is written in the storage location of each corresponding channel in the channel. In the example of FIG. 8, the segment address 0 is written for all eight channels. The 6-bit segment address written in the minute shift detecting circuit 52 such as a RAM corresponds to the minute shift amount for each time-division channel. This is the difference data (4 bits ) Are combined with each other to form 10-bit shift amount data, which is sent to a shift amount output circuit 53.

The 10-bit shift amount data thus obtained is sent to the adder 44 via the shift amount output circuit 53 only when the digital signal is rewritten as in the above-described editing or the like. Has become. That is, the 10-bit shift amount data is written to the shift amount output circuit 53 composed of a memory such as a RAM only at the time of signal rewriting.
For this write control, an address selector 55 is provided. This address selector 55, the eighth and middle 9 bits of the lower side 3-bit address A ₃ to A _5, as shown in FIG. D, the lower 3 bits (upper reading address as shown in FIG. 8 e counter 16 bit address a ₀ from 43
Address A ₀ of the lower 3 bits) of the to A ₁₅ to A ₂ and are supplied, these addresses, the rewrite control signal,
For example, it is selectively switched according to the edit-in point signal (FIG. 8f) and output from the address selector 55. That because the signal of FIG. 8 f has 3 bit address A ₃ to A ₅ in FIG. 8 d becomes "H" (high level) when the edit-in point is selected, in the example of FIG. 8, Channel 4 (ch
The address value 3 of 4) is output, and the address selector 55
The output from is as shown in FIG. 8g. The edit-in point signal shown in FIG. 8f is supplied to the write signal input terminal WE of the shift-in output circuit 53, and the shift-in data (10 bits) at the edit-in point is stored in RAM or the like. Deviation output circuit 5
3 is written to the storage location corresponding to the fourth channel ch4 (address value 3). Since the reading from the shift amount output circuit 53 is sequentially performed for each address shown in FIG. 8E, the shift for each time-division channel is updated according to the update of the lower three-bit addresses A _{0 to} A _2. The quantity data is sent to the adder 44. The upper 10 bits (addresses A _{6 to} A ₁₅ ) of the 16-bit data from the read address counter 43 are added to each of the time-division channels and sent to the write / read selector 41. . The write / read switching operation of the write / read selector 41 and the pulse train recording rearrangement memory 31 is as follows.
This is performed in response to a write / read switching signal as shown in FIG. 8h. In FIG. 8h, W corresponds to writing, and R corresponds to reading.

In this way, blocks, channels,
The data written to the rearrangement memory 31 in accordance with the write address from the write address counter 42 specified in the bit order is specified by the read address from the read address counter 43 in the order of block, bit, and channel from the upper side. By reading the data, the rearrangement of the data as shown in FIG. 6 is performed, and at the same time, the read address is controlled by the adding circuit 44 in accordance with the above-mentioned shift amount, so that the shift amount is corrected. . Therefore, the continuity between the newly recorded (rewritten) portion and the previously recorded portion is improved, and it is possible to prevent an adverse effect such as occurrence of an error at the next reproduction.

It should be noted that the present invention is not limited to only the above-described embodiment. For example, not only application to a digital VTR,
Application to a normal fixed-head type digital audio tape recorder is also easy. In addition, the present invention can be applied to not only a case where a digital signal is recorded on a recording medium but also a block shift correction in a case where a digital signal is generally divided into blocks and recorded / reproduced. Further, the recording timing control according to the shift amount may be performed by an interleave memory (the memory 22 in FIG. 1) instead of the reordering memory. In addition, it goes without saying that various changes can be made without departing from the spirit of the present invention.

〔The invention's effect〕

According to the digital signal recording / reproducing method according to the present invention, a digital signal having a synchronization signal and an address assigned to each predetermined word of digital data corresponding to the digital signal recorded / reproduced by the rotary head is fixed. When a new digital signal is to be recorded (rewritten) by a fixed head in response to an editing operation or the like on a recording medium recorded according to the above, an address serving as a reference according to the digital signal reproduced by the rotating head The shift amount is detected by comparing the reference address signal from the reference address generating means for generating the digital signal with the synchronizing signal and address of the digital signal reproduced by the fixed head, and recording is newly performed by the fixed head according to the shift amount. By controlling the recording timing of the digital signal to When the head tracking is adjusted or when a different VTR is used for recording, the correspondence between the video vertical synchronization signal and the playback signal of the audio track differs from the original correspondence during the original recording. Even when the data is reproduced with a deviation, the continuity between the already recorded signal and the newly recorded signal can be maintained. Therefore, even when an edited recording medium is reproduced, the continuity of addresses and the like are kept good, so that errors that cannot be corrected are less likely to occur, and adverse effects can be prevented. It becomes possible.

[Brief description of the drawings]

All figures are for explaining an embodiment applied to a method of recording and reproducing an audio PCM signal with a fixed head in a VTR for digitally recording a so-called high-definition television signal as a method of recording and reproducing a digital signal according to the present invention. FIG. 1 is a block circuit diagram showing a schematic configuration of an audio PCM signal recording / reproducing system, FIG. 2 is a plan view showing a specific example of a recording pattern of a recording track on a magnetic tape,
FIG. 3 is a diagram for explaining a state near an edit point when an audio signal is edited, FIG. 4 is a diagram showing a data format when audio data is divided into blocks, and FIG. FIG. 6 is a diagram showing a recording format of audio data for blocks, FIG. 6 is a diagram for explaining the rearrangement of data for pulse train recording, and FIG. 7 is a diagram for performing rearrangement of the data and correction of a shift amount. FIG. 8 is a block diagram showing a specific circuit configuration example, and FIG. 8 is a timing chart for explaining the operation of FIG. 12 Demodulation circuit section 20 Input / output control circuit section 22 Interleaving memory 31 Reordering memory 32 W Write address control circuit 32 R Read address control circuit 34 Reference block / address generation circuit 35 …… Amount detection circuit 41 …… Write / read selector 42 …… Write address counter 43 …… Read address counter 44… Adder 51 …… Difference calculation circuit 52 …… Small displacement detection circuit 53… Deviation output circuit

Claims (1)

(57) [Claims] 1. A digital signal for recording / reproducing by a fixed head a digital signal to which a synchronizing signal and an address are assigned for each predetermined word of digital data in correspondence with the digital signal recorded / reproduced by a rotary head. In a recording / reproducing method, according to a digital signal reproduced by a rotating head,
A reference address signal from a reference address generating means for generating a reference address is compared with a synchronous signal and an address of a digital signal reproduced by a fixed head to detect a shift amount, and a new shift amount is detected in accordance with the shift amount. A recording / reproducing method of a digital signal, comprising controlling a recording timing of a digital signal to be recorded by a fixed head.