JPS63140464A - Digital audio reproducing device - Google Patents

Abstract

PURPOSE:To eliminate the need of the provision of a separate RAM for storing error flags and to drastically reduce the capacity and number of RAMs in a device by storing temporarily reproducing data reproduced as one unit and an error flag generated for one unit using an area of corrected data of the previous one unit in the RAM as well. CONSTITUTION:Reproducing data and an error flag are temporarily stored in a random access memory (RAM) by writing/reading of the floating address system and at this time a part of audio data, i.e. correction processed reproducing data of one unit and an error flag are read out and then reproducing data of the next unit and an error flag are subsequently written. Consequently, when the writing, one unit is started corrected data of the previous unit reproducing data become already unnecessary data. Since corrected data areas (a)-(c) are also used for the memory of reproducing data and error flag for one unit, reproducing data and error flag are stored temporarily by using, for instance, one RAM 4.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a digital audio reproducing apparatus such as a PCM audio reproducing apparatus and a digital audio tape recorder using a video chip recorder.

[Conventional technology]

Conventionally, in order to record and play back audio signals with high density and high quality, we have developed EIAJ standard PCM audio playback devices that use rotary head type video tape recorders for home use, 8mm video tape recorders, digital audio tape recorders, etc. Various digital audio playback devices have been devised, for example, 1 Toshiba Review, Vol. 40, No. 2 J (198
Pages 105 to 108 of the issue published in 2005 describe the recording and playback processing of PCM audio using an 8 mm video tape recorder, and the ``Sanyo Technical Review Vol.
, 12. "Arashi 1" (published February 1980), pages 11 to 22, describe recording and playback processing of PCM audio using a home video tape recorder.

In this type of digital audio playback device, PCM audio data, which is formed by digitally converting an analog audio signal, is processed on a recording medium such as a magnetic tape or a magnetic disk in units of correction processing, in other words, in units of fields.
It is recorded as digital information along with correction data, etc.
During playback, each time one unit of digital information is played back, correction processing using the PCM audio data E-correction data of that one unit of digital information is performed, and the PCM data that has undergone correction processing is sequentially processed. When a continuous analog audio signal is reproduced and formed by analog conversion, if correction processing is applied to each unit of reproduced PCM audio data, each unit of reproduced PCM audio data, correction data Playback data such as those normally needs to be temporarily stored using random access memory (hereinafter referred to as RAM).

For example, when playing PCM audio using an 8mm video tape recorder, the following two processes (a) and (b) are performed by the RAM described above in order to continuously reproduce and form the audio signal. It is necessary to do this for one field at the same time.

(a) writing the reproduced data of the reproduced l field and error correction of the reproduced PCM audio data;
Interleave.

(b) Reading out the PCM audio data of the previous field that has been corrected.

However, due to L@vRAM+c, image processing (a),
(b) t- Since it is difficult to perform the above process (a) on each field at the same time, two RAMs are conventionally used.

(b) This is done for each field at the same time.

That is, one of the two RAMs (thus, processing (a)).

(b) 'Alternately for each kl field, and processed by the other of both RAMs (a), (b) '! r
Processes (a) and (b) are simultaneously performed on each field by performing the processing alternately for each field in the reverse order.

For PCM audio data of an 8mm video tape recorder, the total capacity of playback data such as PCM audio data and correction data played back in each field is set to 1320 bytes (132 blocks x 10 bytes). The capacities of the two RAMs are typically set to 2 bytes each.

By the way, P (Ji audio data (
By applying ζ correction processing, one field (1320
An error flag of 1 field (bit) is generated, and this error flag is necessary for correction processing in the subsequent circuit3.Therefore, the error flag of 1 field generated by correction processing (ζ) is It is necessary to temporarily store the data using a vacant area of the RAM and read it out to the subsequent circuit at the same time as reading out the PCM data.

That is, this type of digital audio playback device performs correction processing on the played PCM audio data, and also uses at least one field in order to read out the corrected PCM audio data and the generated error flag to the subsequent circuit. It is necessary to provide two RAMs with a capacity for storing playback data and error flags for z, and in this case, the number of RAMs with a capacity of two to be provided in the apparatus becomes large and expensive.

Therefore, the above-mentioned "Toshiba Shivu, Vol. 40, No. 2" and "Sanyo Technical Review vOL, 12. III &11" are explained below. (a)
, m> in one RAM,
It is stated that the capacity of 9 items is to be deleted.

That is, in the process (b) from the end of the correction process to the start of playback of the first field, a part of the start address side, that is, the start end side, of the PCM audio of the first field that has been corrected is read out, Since it is possible to store the next field of playback data using the read out part of the area, processing (a), ( One RAM is provided to be used only for b), and the capacity of the RAM is set to be larger than the storage capacity of one field of reproduction data and smaller than the storage capacity of two fields of reproduction data, for example, 2 bytes.

For example, when the reproduced data reproduced in the Nth field is written and processed in the RAM (++) 1-field area (A) of FIG. 4(a), the reproduced data reproduced in the N+1st field is is written in the area (B) of the L field, which is made up of the empty area that was not used in the Nth field and a part of the starting end side of the area (A), as shown in FIG. furthermore, the Nth
The playback data played in the +2 field is shown in the same figure (C).
As shown in Figure 1, data is written to the area (C) of one field, which is made up of the empty area that was not used in the N+1 field and a part of the start end side of the area (B).
The playback data of each field is written and processed using the unused area of the field immediately before Mfll and the area that has already been read.

[Problem that the invention seeks to solve]

By the way, when processing (a) and (b) are performed using the floating address method described above, RAM[+l is dedicated to processing PCM audio, and RAM+1+ is used to store all error flags for each generated field. As described in
It is necessary to provide a 2 bit RAM for storing 1 field of error flags, ie 132 o bits of error flags.

Therefore, it is necessary for the device to be provided with a RAM for storing reproduced data and performing correction processing, and a RAM for storing generated error flags.

Further, the present invention does not use the RAM for storing the above-mentioned error flag, but uses only one RAM.

For example, the PCM played by RAM+11 only
The technical problem is to significantly reduce the RAM capacity of the device by storing and correcting audio data and storing generated error flags.

[Means for solving problems]

This invention was made with the above points in mind,
The digital information recorded on the recording medium in units of correction processing is reproduced, and each time one unit of digital information is reproduced (this,
Temporarily stores all playback data such as audio data and correction data of a unit of digital information, temporarily stores one unit of error flag generated by error detection of one unit of stored playback data, and stores correction data. After correcting the audio data stored in The storage capacity is set to be larger than the storage capacity of , and smaller than the storage capacity of 2 units of playback data and error flag.

Random access memory in which 1 unit of reproduced data obtained by reproduction and 7 errors are written, and an area where corrected data of 1 unit before is written every time 1 unit of digital information is reproduced, and an unused address. Specify,
One unit of playback data obtained by playback and an error flag are written to the memory (and after correction processing of one unit of audio data written to the memory) until one unit of digital information is played back. This digital audio reproducing apparatus is characterized in that it is completely equipped with an address generating section that sequentially addresses and reads out single audio data and error flags corrected during the processing from the front memory to the rear corner circuit.

[Effect]

Therefore, as shown in FIGS. 4(a) to (C), the random access memory, that is, the RAM, temporarily stores reproduced data and error flags by writing and reading using the 70-ting addressing method, and at this time, one unit of reproduced data The next unit of playback data and error flag are written after a part of the corrected audio data and the error flag are read out, so when writing of that unit starts, the previous playback Data correction data is unnecessary data E.

The correction data area that was not used in FIGS. 4(a) to (C) is also used for storing one unit of reproduced data and an error flag, so it is stored in, for example, one RAM.
(1+e can be used to temporarily store playback data and error flags.

〔Example〕

Next, this invention will be explained in detail with reference to FIGS. 1 to 3 showing one embodiment thereof.

Figure 1 shows the case where it is applied to the PCM O→IO playback of an 8mm video tape recorder.
Reproduction data such as CM audio data and correction data is checked by a cyclic redundancy (CRC) check circuit (2), and an error flag is initially generated. The generated error flag is transmitted to RAM+41 via flag bus (5).

At this time, the address for each block of 1 field (132 blocks) output from the block start address generation circuit (6) and the write address of RAM (41) output from the RAM input offset address generation circuit (7) are used. The write address of the reproduced data, which is formed by adding the address indicating the beginning, by the adder (8) ζ, is inputted to the RAM (4Hζ) via the address bus (9), and is written to the RAM+41 based on the write address. One field of playback data and an error flag are written and stored.

When one field of playback data is written to the RAM (4), the address and correction offset of the generation circuit (6) are used to correct the PCM audio data using the P and Q correction data in the playback data. □The adder (11) adds the address for specifying correction data output from the address generation circuit (10), and the address, that is, the correction write and read address, is input to the RAM (41) via the bus (9). , based on the address, R
The PCIVI audio data, correction data, and error flag of AIV1441 are transmitted to the correction circuit (12), and after the P and Q parity correction processing, they are sent to the R again.
The process is returned to AM (41), and at this time, the content of the error flag is set based on the correction result.

Furthermore, when the correction process is completed, the address of the generation circuit (6) and the RAM output offset address generation circuit (13) are
) is added by the adder (14), that is, the read address of the PCM audio data after correction processing and the generated error flag is added via the bus (9). R.A.
M (input in 41, based on the successive address, R
The corrected PCM is sent from AM+41 to the subsequent 8710 conversion circuit (15) via bus t31 e (5) f.
The audio data and the generated error flag are transmitted sequentially at the timing of continuous playback of the audio signal.

Then, the demodulated P (Ji audio data) is output to the digital/analog (hereinafter referred to as D/A) conversion circuit (17) via the input PCM O to the conversion circuit (17). Through the D7'A conversion, an analog audio signal is reproduced and formed.

Note that each generation circuit +6+ , (7) j (101,
:I31 forms an address generation section.

By the way, the data array of RAM [4+, that is, the array of playback data and error flags for each field is 1
Each field changes as described below.

Now, the reproduced data of the Nth field and the factory flag are transmitted to the RAM (41), and at this time the generation circuit +61
, (According to address G of 7+, one field area (Mn,) shown in the shaded area in FIG. 2(a) is addressed, and the audio data area (a) in order from the top of area (Mn), error The transmitted PCM audio data and error flag are shown in the flag area (b) and correction data area (C).

Assuming that each corrected data is stored, the following Nth
+1st field playback data and error flag are:
An area of one field consisting of area (b) of the Nth field, an unused area (X) below area (b), and a part of the area on the starting end side of area (a) that has already been read. , that is, the shaded area (Mn+ 1
) G is written.

That is, the correction process for each 17-yield PCM audio data is completed by the time the next field is played, as will be described later, and at this time, after the correction process, the area (b
) is no longer necessary, and the PCM data at the beginning of the corrected address is read out after the correction process and before the playback of the next field starts. When starting, at least part of the starting end of area (b) and area (a) is writable.

Therefore, the reproduced data of each field and the generated error flag are composed of the area (b) and unused area (X) of the previous field, and a part of area (a). Area of the field (Mn).

(Mn+t) using the 70-ting addressing method and temporarily stored.

The storage capacity of RAM (4) is P for 1 field.
The total capacity of 1320 bytes of CM audio data and correction data and 1320 bits of error flag of 1 field, that is, the capacity of 1 field of PCM audio data, correction data and error flag, and 2 fields of PCM audio. data,
The RA is set to 2 bytes, which is smaller than the capacity of the correction data and error flag, and then when playback of digital information of each field is started, as explained below, the RA
Since the reproduction data and error flag areas of at least one field of M14) are writable and free, RAM+11 for temporarily storing error flags is used.
1 of the same capacity as conventional RAM+11 without the need for
The RAM f4) k can be used to temporarily store playback data and error flags.

Next, the size of the writable area of the RAM (41) when the digital information of each field starts to be reproduced will be explained.

In the case of an 8 mm video tape recorder, each field of digital information recorded on the tape is reproduced at 26.32 degrees for each half rotation of the head cylinder.

As shown in FIG. 3, at the time TO when the head cylinder (one group) rotates half a rotation, that is, 180 degrees, the aforementioned digital information reproduction trace time of 26.32 degrees 2
When setting it to T1 (this, the initial setting time of the error flag, and the writing time iTz, T+f), and
Total correction processing time, from the start of the reproduction trace to the end of the correction process (this conversion circuit (15) i) The data readout time is set to iT4.Ts, and the next reproduction trace starts from the end of the correction process. When the time up to T6 is set to iTa, each time TO to T6 becomes as follows.

First, the cylinder (kuni) rotates once in 1/29.97 seconds, so it is full.

Since the error flag of the field is 1320 bits, the storage area for the error flag of one field is 13 bits of RAM (,+).
2 blocks x 2 (= 246 blocks = 246
X 8 bits) 1320 bits).

If it takes Ta time to write and read data such as one block of PCM audio data and error flags, then T2 is T2=264X2XTa.
It can be found from the formula.

T3 changes depending on the number of error data, but there is no error data and all error flags are set to 1 with no error.
0” (for rubbing, i.e. for the longest time, T3 =
It can be found from the formula 264 x 2 x Ta.

Next, correction of the P parity sequence of PCM audio data is performed by one error correction using 9 data pieces in each column, and correction of the Q parity sequence is performed using 10 data pieces for each column. This is done with one error correction using .

If the PCM audio correction process is repeated three times in the order of P, Q, P, Q, P, Q, then the correction of each column of the P parity sequence is This is done in 10 accesses, and each column of the Q parity sequence is corrected in 11 accesses, so 132 x (10+11) accesses are required to correct all data.

Further, the number of accesses to the error flag for correction processing is the same as the number of accesses for correction, 132 x (10+11).

Therefore, T4 is T4 = (132X (10+
11) ) It can be found from the formula x2xTa.

Next, since the PCM audio data is formed at a speed of 31.5KH2X2 by alternate sampling of the left and right channels at a sampling frequency of 31.5KHz, at the time Tl+T2+T:l+T4, the RA Mi
From 4+ to modulation circuit (151, ('1'l+T2+T3
+T4)/(1/31,5K HZ X 2)
The number of data is read out.

Find out.

Next, RAM (41 to 2 bytes (!=; 2048
(132 bytes) to record 2 fields of playback data and 1 field of error flags.
0x2 + 264-2048 = ) 856 bytes of capacity is insufficient.

Then, from the time after the correction process until the reproduction data of the next field is input to the RAIV 141, at least 856/might of data f RAM (41) is read out to the modulation circuit (15) at T6, and then each field is Since the writable area of RAM (4) at the start of playback is the capacity of one field of playback data and error flag, T6 is T6> (1320X2+264-20
48) ×31.5 KM It is necessary to satisfy the formula zX2.

By the way, when Tai is calculated from each condition of Tl-Ts mentioned above, it becomes Ta (274n see).

Therefore, one access time to RAM (41) is 2.
By using RAM=i shorter than 74n see, when playback of digital information for each field is started, the writable free area of RAM (4) is at least equal to the capacity of playback data and error flag for one field. In fact, since the time for one access to RAM is shorter than 274 nsec, one RAM [41] can be used to temporarily store playback data and error flags.

4(a) and (b) of the conventional RAMf
+], that is, a RAM with a storage capacity smaller than the storage capacity for two fields of playback data and error flags (because the playback data and error flags can be temporarily stored using 4i, the device's RAM capacity .

The number of pieces is significantly reduced.

In the above embodiment, the P of the 8 mm video tape recorder is
Although it was applied to the playback of commercial audio, the EIAJ standard P
The present invention can be applied to the reproduction of digital audio in various digital audio reproduction devices such as a commercial audio reproduction device and a digital audio tape recorder, and in this case, the size of the reproduction data, the storage capacity of the RAM, etc. may be different from the embodiments. Of course.

〔Effect of the invention〕

As described above, according to the digital audio playback device 1 of the present invention, one unit of played playback data and one unit of generated error flag are stored in a random access memory, that is, a RAM that has not been used conventionally. By using the area for the previous unit of correction data and temporarily storing it using the so-called floating address method, there is no need to provide a separate RAM'i for storing error flags, and the number of RAM's in the device can be greatly reduced. This can be reduced to

[Brief explanation of the drawing]

1 to 3 show one embodiment of the digital audio playback device of the present invention, FIG. 1 is a block diagram, FIGS. 2(a) and 2(b) are RAM storage pattern diagrams, and FIG. 3 is a block diagram. FIGS. 4(a) and 4(b), explanatory diagrams of the operation of the RAM, are storage patterns of the RAM of a conventional digital audio playback device: FIG. (4)...RAM1 [61, t71, 101 e j
131 ・Address generation circuit.

Claims (1)

[Claims] (1) Reproducing digital information recorded on a recording medium in units of correction processing, and each time one unit of digital information is reproduced, temporarily storing reproduction data such as audio data and correction data of the one unit of digital information. At the same time, one unit of error flag generated by error detection of one unit of stored playback data is temporarily stored, and the stored audio data is corrected using the stored correction data, and the correction process is performed. Later, in a digital audio playback device that sequentially transmits corrected audio data and generated error flags to a subsequent circuit, the storage capacity of two units of playback data and error flags is larger than the storage capacity of one unit of playback data and error flags. A random access memory whose storage capacity is set to be smaller than the storage capacity, and in which one unit of reproduced data obtained by reproduction and an error flag are written, and one unit of previous correction data every time one unit of digital information is reproduced. One unit area of the memory consisting of the area where is written, an unused area, and a part of the starting end side of the audio data area one unit before is addressed, and the result is obtained by playback. One unit of playback data and an error flag are written to the memory, and the correction is made between the time after the correction processing of the one unit of audio data written to the memory and the time when the next one unit of digital information is played back. 1
1. A digital audio playback device comprising: an address generation unit that sequentially addresses units of audio data and error flags and reads them from a previous memory to the subsequent circuit.