JPS57200915A - Reducing method for memory for crc writing - Google Patents
Reducing method for memory for crc writingInfo
- Publication number
- JPS57200915A JPS57200915A JP56084649A JP8464981A JPS57200915A JP S57200915 A JPS57200915 A JP S57200915A JP 56084649 A JP56084649 A JP 56084649A JP 8464981 A JP8464981 A JP 8464981A JP S57200915 A JPS57200915 A JP S57200915A
- Authority
- JP
- Japan
- Prior art keywords
- memory
- written
- crc
- writing
- words
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
- G11B20/18—Error detection or correction; Testing, e.g. of drop-outs
- G11B20/1806—Pulse code modulation systems for audio signals
- G11B20/1813—Pulse code modulation systems for audio signals by adding special bits or symbols to the coded information
Landscapes
- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Detection And Correction Of Errors (AREA)
- Error Detection And Correction (AREA)
Abstract
PURPOSE:To reduce the capacity of memory for cyclic code writing and to simplify circuit constitution, by using an empty part of a memory for data writing as a memory for cyclic code writing. CONSTITUTION:While eight words from sampled signal words L1n, R1n ... to error correctin words Pn and Qn are written in a memory successively, arithmetic for the error detection of CRCs (cyclic code) is performed and the values are held. An eight-bit part where the high-order digit bits of the L1n are written is read out immediately after a next L1(n+1) is written, the arithmetic result of the CRC is moved to the position indicated by slanting lines, and said read data is written at the original location together with the arithmetic result of the CRC. The R1n is read out shortly after an R1(n+1) is written, and the similar operation mentioned above is repeated.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56084649A JPS57200915A (en) | 1981-06-01 | 1981-06-01 | Reducing method for memory for crc writing |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56084649A JPS57200915A (en) | 1981-06-01 | 1981-06-01 | Reducing method for memory for crc writing |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS57200915A true JPS57200915A (en) | 1982-12-09 |
Family
ID=13836547
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56084649A Pending JPS57200915A (en) | 1981-06-01 | 1981-06-01 | Reducing method for memory for crc writing |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS57200915A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6187277A (en) * | 1984-10-05 | 1986-05-02 | Hitachi Ltd | Method and device for pcm signal reproduction |
| JPS63140464A (en) * | 1986-05-20 | 1988-06-13 | Sanyo Electric Co Ltd | Digital audio reproducing device |
-
1981
- 1981-06-01 JP JP56084649A patent/JPS57200915A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6187277A (en) * | 1984-10-05 | 1986-05-02 | Hitachi Ltd | Method and device for pcm signal reproduction |
| JPS63140464A (en) * | 1986-05-20 | 1988-06-13 | Sanyo Electric Co Ltd | Digital audio reproducing device |
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