JPS56114043A - Code converting circuit - Google Patents

Code converting circuit

Info

Publication number
JPS56114043A
JPS56114043A JP1725980A JP1725980A JPS56114043A JP S56114043 A JPS56114043 A JP S56114043A JP 1725980 A JP1725980 A JP 1725980A JP 1725980 A JP1725980 A JP 1725980A JP S56114043 A JPS56114043 A JP S56114043A
Authority
JP
Japan
Prior art keywords
data
parallel
written
conversion
length code
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1725980A
Other languages
Japanese (ja)
Other versions
JPS6214854B2 (en
Inventor
Kengo Fujita
Kiichi Matsuda
Makoto Hiraoka
Toshihiro Honma
Yutaka Fukuda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP1725980A priority Critical patent/JPS56114043A/en
Publication of JPS56114043A publication Critical patent/JPS56114043A/en
Publication of JPS6214854B2 publication Critical patent/JPS6214854B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/76—Arrangements for rearranging, permuting or selecting data according to predetermined rules, independently of the content of the data

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)

Abstract

PURPOSE:To obtain a converting circuit that performs all processes in parallel and is suited to a high-speed process, by using a matrix to give a conversion to the bit position of the data. CONSTITUTION:The input variable length code data is put into the matrix MT11 by a word and in parallel. The MT11 shifts the positions of the supplied n-bit data by an optional bit number and without changing the sequence and then delivers them in parallel. These data are then written in parallel via the memory 12 and switch 13 into the FF14. In this case, if some data remains through the precedent conversion, this data is added to the parallel data of the FF14 from the memory 12. When the data written into the FF14 does not reach n bits, the head part of the next variable length code data is added to the end of the data written into the FF14 in the next conversion. When the data written into the FF14 reaches n bits, it is shifted to the FF15 to be delivered in the form of a fixed length code data in the necessary timing.
JP1725980A 1980-02-15 1980-02-15 Code converting circuit Granted JPS56114043A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1725980A JPS56114043A (en) 1980-02-15 1980-02-15 Code converting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1725980A JPS56114043A (en) 1980-02-15 1980-02-15 Code converting circuit

Publications (2)

Publication Number Publication Date
JPS56114043A true JPS56114043A (en) 1981-09-08
JPS6214854B2 JPS6214854B2 (en) 1987-04-04

Family

ID=11938956

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1725980A Granted JPS56114043A (en) 1980-02-15 1980-02-15 Code converting circuit

Country Status (1)

Country Link
JP (1) JPS56114043A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62157424A (en) * 1985-12-18 1987-07-13 アドバンスト・マイクロ・デイバイシズ・インコ−ポレ−テツド Apparatus for converting asynchronous different type variable width parallel data pattern input signals into series data pattern signals
JPS62157425A (en) * 1985-12-18 1987-07-13 アドバンスト・マイクロ・デイバイシズ・インコ−ポレ−テツド Apparatus for converting series data pattern signal

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62157424A (en) * 1985-12-18 1987-07-13 アドバンスト・マイクロ・デイバイシズ・インコ−ポレ−テツド Apparatus for converting asynchronous different type variable width parallel data pattern input signals into series data pattern signals
JPS62157425A (en) * 1985-12-18 1987-07-13 アドバンスト・マイクロ・デイバイシズ・インコ−ポレ−テツド Apparatus for converting series data pattern signal

Also Published As

Publication number Publication date
JPS6214854B2 (en) 1987-04-04

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