JPS5474642A - Operation circuit - Google Patents

Operation circuit

Info

Publication number
JPS5474642A
JPS5474642A JP14163177A JP14163177A JPS5474642A JP S5474642 A JPS5474642 A JP S5474642A JP 14163177 A JP14163177 A JP 14163177A JP 14163177 A JP14163177 A JP 14163177A JP S5474642 A JPS5474642 A JP S5474642A
Authority
JP
Japan
Prior art keywords
circuit
output
memory
parallel
serial
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14163177A
Other languages
Japanese (ja)
Inventor
Tsutomu Sakamaki
Jinichi Sakurai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP14163177A priority Critical patent/JPS5474642A/en
Publication of JPS5474642A publication Critical patent/JPS5474642A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To reduce the number of access of the main memory and to speed up the processing speed, by constituting the operation circuit with the circuit converting parallel one word picked up from the main memory, temporary memory of 1-bit x n words memorizing the output, and the circuit converting the output into parallel one word etc. CONSTITUTION:The output of the main memory 1 is connected to the parallel serial conversion circuit 5 via the output bus 10, and the circuit 5 converts the word information of parallel plurality bit into serial word information. Next, the output of the circuit 5 is fed to the temporary memory 6 and the processing speed is quickened by selecting the data faster in the access time in comparison with the main memory 1. To this memory 6, the function memorizing the data from the circuit 5 as well as the output from the one-bit operation circuit 2 is given. After that, the output of the memory 6 is connected to the serial parallel conversion circuit 7 and the circuit 2, the circuit 7 converts the serial data from the memory 6 into the word information of parallel plurality bit, and the information is written in the memory 1 via the input bus 11.
JP14163177A 1977-11-28 1977-11-28 Operation circuit Pending JPS5474642A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14163177A JPS5474642A (en) 1977-11-28 1977-11-28 Operation circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14163177A JPS5474642A (en) 1977-11-28 1977-11-28 Operation circuit

Publications (1)

Publication Number Publication Date
JPS5474642A true JPS5474642A (en) 1979-06-14

Family

ID=15296521

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14163177A Pending JPS5474642A (en) 1977-11-28 1977-11-28 Operation circuit

Country Status (1)

Country Link
JP (1) JPS5474642A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02244329A (en) * 1989-03-17 1990-09-28 Mitsubishi Electric Corp Digital signal processor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02244329A (en) * 1989-03-17 1990-09-28 Mitsubishi Electric Corp Digital signal processor

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