JPS5534356A - Memory device - Google Patents

Memory device

Info

Publication number
JPS5534356A
JPS5534356A JP10703978A JP10703978A JPS5534356A JP S5534356 A JPS5534356 A JP S5534356A JP 10703978 A JP10703978 A JP 10703978A JP 10703978 A JP10703978 A JP 10703978A JP S5534356 A JPS5534356 A JP S5534356A
Authority
JP
Japan
Prior art keywords
line
positive integer
bit
block satisfying
bit lines
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP10703978A
Other languages
Japanese (ja)
Other versions
JPS6114599B2 (en
Inventor
Toshinori Otsuka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP10703978A priority Critical patent/JPS5534356A/en
Publication of JPS5534356A publication Critical patent/JPS5534356A/en
Publication of JPS6114599B2 publication Critical patent/JPS6114599B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers

Landscapes

  • Static Random-Access Memory (AREA)

Abstract

PURPOSE:To carry out the high speed processing by selecting a plurality of bit lines simultaneously and providing more than one block satisfying the particular conditions. CONSTITUTION:There is provided more than one block satisfying the following conditions. At first, bit line B of positive integer number K (K>=2) in which the respective one of the memory cell of one bit is connected through the gate controlled by the signal given to the common word line, positive integer l (l>=1) select line S and positive integer m (m>=2) data line D are included. K bit lines B are respectively connected to m data lines D through the gate circuit controlled by the signal applied to the select line S.
JP10703978A 1978-08-31 1978-08-31 Memory device Granted JPS5534356A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10703978A JPS5534356A (en) 1978-08-31 1978-08-31 Memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10703978A JPS5534356A (en) 1978-08-31 1978-08-31 Memory device

Publications (2)

Publication Number Publication Date
JPS5534356A true JPS5534356A (en) 1980-03-10
JPS6114599B2 JPS6114599B2 (en) 1986-04-19

Family

ID=14448961

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10703978A Granted JPS5534356A (en) 1978-08-31 1978-08-31 Memory device

Country Status (1)

Country Link
JP (1) JPS5534356A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6432496A (en) * 1987-07-27 1989-02-02 Mitsubishi Electric Corp Read-only memory

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6432496A (en) * 1987-07-27 1989-02-02 Mitsubishi Electric Corp Read-only memory

Also Published As

Publication number Publication date
JPS6114599B2 (en) 1986-04-19

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