JPS56152064A - Data transfer device - Google Patents

Data transfer device

Info

Publication number
JPS56152064A
JPS56152064A JP5565780A JP5565780A JPS56152064A JP S56152064 A JPS56152064 A JP S56152064A JP 5565780 A JP5565780 A JP 5565780A JP 5565780 A JP5565780 A JP 5565780A JP S56152064 A JPS56152064 A JP S56152064A
Authority
JP
Japan
Prior art keywords
address
cpu1
data
signal
order half
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5565780A
Other languages
Japanese (ja)
Inventor
Yoshiharu Yamazaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP5565780A priority Critical patent/JPS56152064A/en
Publication of JPS56152064A publication Critical patent/JPS56152064A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus

Abstract

PURPOSE:To transfer data at a high speed by providing a storage device in common to the 1st and 2nd CPUs differing in the length of data to be processed and by subordinating said device to either CPU by switching. CONSTITUTION:Central processing unit CPU3 has a data length 1/2<n> (n=1) times as long as for CPU1, and storage devices 11 and 12 in common to CPUs 1 and 3 are provided. Address signal (a), once outputted from CPU1, is selected by address selector 13 and outputted to address line 22. The high-order half and low-order half of bits of data, when sent to data lines 18 and 19 by CPU1, are stored in the address, specified by signal (a), of devices 11 and 12. Next, when CPU1 outputs switching control signal (b) to interruption line 10, CPU3 outputs address signal (c) and selector 13 is switched to select signal (c); and gates 17 and 16 are opened in time-division mode to send the high-order half and low-order half of bits from devices 11 and 12 to CPU3 in time-division mode.
JP5565780A 1980-04-23 1980-04-23 Data transfer device Pending JPS56152064A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5565780A JPS56152064A (en) 1980-04-23 1980-04-23 Data transfer device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5565780A JPS56152064A (en) 1980-04-23 1980-04-23 Data transfer device

Publications (1)

Publication Number Publication Date
JPS56152064A true JPS56152064A (en) 1981-11-25

Family

ID=13004903

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5565780A Pending JPS56152064A (en) 1980-04-23 1980-04-23 Data transfer device

Country Status (1)

Country Link
JP (1) JPS56152064A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58225460A (en) * 1982-06-25 1983-12-27 Fujitsu Kiden Ltd Access system to memory
JPS61217859A (en) * 1985-03-25 1986-09-27 Fujitsu Ltd Data transfer system
JPS63113745A (en) * 1986-10-31 1988-05-18 Sony Tektronix Corp Memory controller
JP2007156544A (en) * 2005-11-30 2007-06-21 Canon Inc Information processing system, memory control device, and data transmission control method

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58225460A (en) * 1982-06-25 1983-12-27 Fujitsu Kiden Ltd Access system to memory
JPS61217859A (en) * 1985-03-25 1986-09-27 Fujitsu Ltd Data transfer system
JPS63113745A (en) * 1986-10-31 1988-05-18 Sony Tektronix Corp Memory controller
JP2007156544A (en) * 2005-11-30 2007-06-21 Canon Inc Information processing system, memory control device, and data transmission control method

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