JPS56162165A - Data transfer system - Google Patents

Data transfer system

Info

Publication number
JPS56162165A
JPS56162165A JP6618780A JP6618780A JPS56162165A JP S56162165 A JPS56162165 A JP S56162165A JP 6618780 A JP6618780 A JP 6618780A JP 6618780 A JP6618780 A JP 6618780A JP S56162165 A JPS56162165 A JP S56162165A
Authority
JP
Japan
Prior art keywords
devices
digit lines
controller
digit
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP6618780A
Other languages
Japanese (ja)
Other versions
JPS6017132B2 (en
Inventor
Akizo Kitamura
Koichi Iwasaki
Hiroaki Sato
Mitsuo Nishida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP55066187A priority Critical patent/JPS6017132B2/en
Publication of JPS56162165A publication Critical patent/JPS56162165A/en
Publication of JPS6017132B2 publication Critical patent/JPS6017132B2/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Microcomputers (AREA)

Abstract

PURPOSE:To use a direct memory controller, which is used before extension, continuously when plural memory devices are extended, by specifying areas requiring access in respective memory devices and by adding a simple-constitution switching device. CONSTITUTION:A processor 1 and a direct memory access controller 2 are connected by a data bus 5 and the 0th - the 13th digit lines 61 as an address bus. These digit lines 61, the 14th digit line 62, and the 15th digit line 63 are distinguished from other digit lines and are connected to memory devices 31-34 having specific areas 311-341 requiring access. A control line 70 from the processor 1 is connected to devices 31-34 through a register 7 to designate respective devices 31-34. The 0th - the 13th digits of the memory address signal from the controller 2 are connected to digit lines 61 directly, and two bits of the 14th - the 15th digits are connected to digit lines 62 and 63 or a decoder 8 through a switching circuit 11. Thus, the controller is used continuously when devices 32-34 are extended.
JP55066187A 1980-05-19 1980-05-19 Data transfer method Expired JPS6017132B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55066187A JPS6017132B2 (en) 1980-05-19 1980-05-19 Data transfer method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55066187A JPS6017132B2 (en) 1980-05-19 1980-05-19 Data transfer method

Publications (2)

Publication Number Publication Date
JPS56162165A true JPS56162165A (en) 1981-12-12
JPS6017132B2 JPS6017132B2 (en) 1985-05-01

Family

ID=13308585

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55066187A Expired JPS6017132B2 (en) 1980-05-19 1980-05-19 Data transfer method

Country Status (1)

Country Link
JP (1) JPS6017132B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62133555A (en) * 1985-12-06 1987-06-16 Nippon Telegr & Teleph Corp <Ntt> Dma address control system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62133555A (en) * 1985-12-06 1987-06-16 Nippon Telegr & Teleph Corp <Ntt> Dma address control system

Also Published As

Publication number Publication date
JPS6017132B2 (en) 1985-05-01

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