JPS57113144A - Stored program computer - Google Patents

Stored program computer

Info

Publication number
JPS57113144A
JPS57113144A JP55188158A JP18815880A JPS57113144A JP S57113144 A JPS57113144 A JP S57113144A JP 55188158 A JP55188158 A JP 55188158A JP 18815880 A JP18815880 A JP 18815880A JP S57113144 A JPS57113144 A JP S57113144A
Authority
JP
Japan
Prior art keywords
bit
data memory
data
arithmetic processing
speed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55188158A
Other languages
Japanese (ja)
Inventor
Setsuzo Tachibana
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Suwa Seikosha KK
Original Assignee
Seiko Epson Corp
Suwa Seikosha KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp, Suwa Seikosha KK filed Critical Seiko Epson Corp
Priority to JP55188158A priority Critical patent/JPS57113144A/en
Publication of JPS57113144A publication Critical patent/JPS57113144A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/04—Addressing variable-length words or parts of words

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)
  • Microcomputers (AREA)

Abstract

PURPOSE:To improve the arithmetic processing effeciency of a microprocessor, etc., by increasing the speed of data transfer via a data memory, by enabling to switch the word length of the data memory to the length twice as long as an arithmetic processing unit. CONSTITUTION:A computer which has a PROM07, and (n)-bit bus lines 13 and 14 at the operator and operand input sides of an (n)-bit arithmetic processing unit 04 is provided with a data memory 01 consisting of two RAMs with (n)-bit word length. In addition to an (n)-bit data memory access address line 15, a (2n)- bit data memory I/O line 17 is provided, and in accordance with the kind of an instruction, (n)-bit processing and (2n)-bit processing are changed over to each other to input and output all of data on the bus lines of the two systems to and from the data memory at the same timing. Therefore, the speed of data transfer via the data memory is increased to improve processing performance.
JP55188158A 1980-12-30 1980-12-30 Stored program computer Pending JPS57113144A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55188158A JPS57113144A (en) 1980-12-30 1980-12-30 Stored program computer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55188158A JPS57113144A (en) 1980-12-30 1980-12-30 Stored program computer

Publications (1)

Publication Number Publication Date
JPS57113144A true JPS57113144A (en) 1982-07-14

Family

ID=16218762

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55188158A Pending JPS57113144A (en) 1980-12-30 1980-12-30 Stored program computer

Country Status (1)

Country Link
JP (1) JPS57113144A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6285339A (en) * 1985-10-09 1987-04-18 Fujitsu Ltd microcomputer
JPH03206525A (en) * 1990-01-09 1991-09-09 Seiko Instr Inc Stack system for single chip microcomputer
JPH0410144A (en) * 1990-04-27 1992-01-14 Matsushita Electric Ind Co Ltd Data transfer circuit
US5901301A (en) * 1996-02-07 1999-05-04 Mitsubishi Denki Kabushiki Kaisha Data processor and method of processing data
US6757809B1 (en) 1989-12-16 2004-06-29 Renesas Technology Corp. Data processor having 2n bits width data bus for context switching functions

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5039436A (en) * 1973-08-10 1975-04-11
JPS5344130A (en) * 1976-10-05 1978-04-20 Toshiba Corp Floating access memory device
JPS5537651A (en) * 1978-09-07 1980-03-15 Matsushita Electric Ind Co Ltd Microcomputer circuit

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5039436A (en) * 1973-08-10 1975-04-11
JPS5344130A (en) * 1976-10-05 1978-04-20 Toshiba Corp Floating access memory device
JPS5537651A (en) * 1978-09-07 1980-03-15 Matsushita Electric Ind Co Ltd Microcomputer circuit

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6285339A (en) * 1985-10-09 1987-04-18 Fujitsu Ltd microcomputer
US6757809B1 (en) 1989-12-16 2004-06-29 Renesas Technology Corp. Data processor having 2n bits width data bus for context switching functions
JPH03206525A (en) * 1990-01-09 1991-09-09 Seiko Instr Inc Stack system for single chip microcomputer
JPH0410144A (en) * 1990-04-27 1992-01-14 Matsushita Electric Ind Co Ltd Data transfer circuit
US5901301A (en) * 1996-02-07 1999-05-04 Mitsubishi Denki Kabushiki Kaisha Data processor and method of processing data
USRE38679E1 (en) * 1996-02-07 2004-12-28 Mitsubishi Denki Kabushiki Kaisha Data processor and method of processing data

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