JPS6214854B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a code conversion circuit that converts an input signal consisting of a variable length code into a signal consisting of a fixed length code and outputs the signal.

The variable-length code system is a system in which the number of bits constituting one word changes depending on the content of information, and corresponds to a fixed-length code system in which the number of bits in one word is always constant. The variable length code system is used for transmitting image signals, audio signals, etc., and has the advantage that the total number of bits required to transmit the same amount of information can be reduced compared to the fixed length code system. On the other hand, the fixed-length code system has a simple configuration;
Commonly used. There is generally no flexibility between these two systems, and code conversion circuits are required between systems with different code formats.

FIG. 1 is a block diagram showing the configuration of a conventional code conversion circuit. In the figure, 1 is a parallel-to-serial converter (P/S), and 2 is a series-to-parallel converter (S/
P), 3 is a register, and 4 is a control circuit.

In FIG. 1, data consisting of a variable length code is input word by word in parallel to a parallel-to-serial converter 1, and is converted into a serial signal having a code length corresponding to the number of bits of the data. Since the parallel-to-serial converter 1 has a constant bit variation, the readout resulting serial signal consists of a valid part containing data and an invalid part not containing data. The serial-to-parallel converter 2 receives such a serial signal, converts only the effective portion including data into a parallel signal, and stores the parallel signal in the register 3. Register 3 also has a fixed number of bits, and when the number of bits of the effective part input from serial-parallel converter 2 becomes equal to the number of bits of register 3,
Output the contents in parallel. Series-parallel converter 2
If the number of bits of data input to register 3 is less than the number of bits in register 3, the contents of register 3 are not output, and the output data of the next serial-to-parallel converter is added to the data in register 3. Output when it becomes equal to the number of bits. These operations of the parallel-to-serial converter 1, the serial-to-parallel converter 2, and the register 3 are performed by the control circuit 4 receiving data number information of input variable length code data and performing necessary control. In this way, variable length code data is converted to fixed length code data.

Such conventional code conversion circuits include parallel-to-serial converters and perform code format conversion processing as described above using serial signals, making them difficult to apply to areas that handle high-speed data. It was hot.

The present invention attempts to eliminate such drawbacks of the prior art, and its purpose is to perform all processing in parallel by converting the bit position of data using a matrix, thus achieving high speed. The purpose of the present invention is to provide a conversion circuit suitable for processing. In order to achieve this purpose, the code conversion circuit of the present invention rotates the parallel input data in a ring shape, arranges the data so that the upper bits of the input data match the empty bits in the first flip-flop, and outputs the data. a memory for storing the output of the matrix, a memory for writing the unproduct data from the previous conversion in the memory into the same position of the first flip-flop, and a portion corresponding to the unproduct data from the output data of the matrix; a switching device that writes data excluding the data into a first flip-flop, and a second switching device that inputs the data in parallel and outputs it at a required timing when the data written to the first flip-flop satisfies a predetermined number of bits. It is characterized by having a flip-flop.

Examples will be described below.

FIG. 2 is a block diagram showing the configuration of one embodiment of the code conversion circuit of the present invention. This figure shows the case where input data consisting of a variable length code is converted into output data consisting of an n-bit fixed length code. In the figure, 11 is an n×n matrix (rotating element), 12 is a memory for recording residual data, and 13 is a
14 is a flip-flop for storing valid bits; 15 is n for output.
It is a bit flip-flop.

In FIG. 2, input variable length code data is input into matrix 1 word by word in parallel. The matrix 11 is an n×n rotating element that moves the n-bit data input in parallel by an arbitrary number of bits without changing the order, as if rotating the n-bit data. It has the function of converting the bit position and outputting it in parallel. These functions of Matrix 11 are
This is carried out under the control of a control circuit 16 which operates in response to data number information of input variable length code data.

The output of matrix 11 is written in parallel to flip-flop 14 via switch 13. At this time, if there is data left over from the previous conversion, it is added to the beginning of the parallel data in the flip-flop 14. In this way, flip-flop 1
If the data written in the flip-flop 14 does not reach n bits, the beginning of the next variable length code data is added to the end of the data written in the flip-flop 14 at the next conversion. When the data written to the flip-flop 14 in this way reaches n bits, the contents are temporarily transferred to the flip-flop 14.
5 and output as fixed length code data at a required timing.

FIG. 3 is a diagram for explaining the operation of the code conversion circuit of the present invention shown in FIG. 2. In the figure, a indicates input variable length code data, and b
indicates the output data of the matrix 11. c.
shows the assembly of fixed-length code data in the flip-flop 14 and the remaining data in the memory 12. Also, in each of these figures,
, , indicate the conversion steps for each data. Each data is the third
In the figure, the bits are arranged in order from the upper bit to the lower bit from the top to the bottom.

The operation of the code conversion circuit shown in FIG. 2 will be described in more detail below with respect to the data illustrated in FIG. 3. In this case, the number of bits of fixed-length code data required as output is n=8, and therefore the matrix 11 in FIG. 2 has an 8.times.8 configuration.

First, when the data a ₁ to _{a 6} shown in FIG.
FIG. 3c,) is further written to the flip-flop 14 (FIG. 3c,). Next, when the data b ₁ to _{b 3} shown in FIG. 3a are input, the control circuit 1
6 controls the matrix 11 according to the availability of the lower bits in the flip-flop 14, so that the matrix 11 converts the input data as shown in FIG. 3b and outputs the converted data. The switch 13 writes the lower bits b ₁ and b ₂ of the matrix 11 to the flip-flop 14 corresponding to the empty space in the flip-flop 14, and at the same time, the matrix output shown in FIG. 3b is provided to record the remaining data. (FIG. 3c,). As a result, flip-flop 14 is filled with 8-bit contents, and the contents are transferred to flip-flop 15. flipflop 1
The contents of 5 are output as fixed length code data at a required timing.

Next, when _the data shown in FIG. The control circuit 16 controls the matrix 11 according to the availability of lower bits in the flip-flop 14, so that the matrix 11 converts input data as shown in FIG. 3b and outputs the converted data. The switch 13 switches the matrix 1 according to the free space in the flip-flop 14.
The lower bits c ₁ to _{c 7} of 1 are written to flip-flop 14, and at the same time the output of matrix 11 is written to memory 12 (FIG. 3c,).
This completes the 8-bit data in the flip-flop 14, and the contents are stored in the flip-flop 15.
and output.

Next, when _the data shown in FIG. The matrix 11 receives input data under the control of the control circuit 16 as shown in FIG.
Convert and output as shown below. Switch 13 writes the lower bits d ₁ to _{d 7} in matrix 11 to flip-flop 14 (FIG. 3d). As a result, 8-bit data is prepared in the flip-flop 14 and outputted via the flip-flop 15.

In this way, variable length code data is converted into fixed length code data by the circuit shown in FIG. According to the code conversion circuit of the present invention, there is no need to first convert data into a serial signal and perform code conversion processing, but all processing can be performed in parallel by converting the bit position of data using a matrix. Therefore, a code conversion circuit suitable for high-speed processing can be realized, and excellent effects can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a conventional code conversion circuit, FIG. 2 is a block diagram showing the configuration of an embodiment of the code conversion circuit of the present invention, and FIG. 3 is a block diagram showing the configuration of an embodiment of the code conversion circuit of the present invention. FIG. 3 is a diagram for explaining the operation in the code conversion circuit of FIG. 1... Parallel-serial converter (P/S), 2... Series-parallel converter (S/P), 3... Register, 4
... Control circuit, 11 ... Matrix (rotating element), 12 ... Memory, 113 ... Switch, 1
4,15...flip flop.

Claims (1)

[Claims] 1. A matrix that rotates data input in parallel in a circular manner and arranges and outputs the data so that the upper bits of the input data match empty bits in the first flip-flop; a memory that stores the output of the matrix; a switching device that writes unproduct data from the previous conversion in the memory to the same position of a first flip-flop, and writes data obtained by removing a portion corresponding to the unproduct data from the output data of the matrix to the first flip-flop; ,
1. A code conversion circuit comprising: a second flip-flop which inputs the data written in the first flip-flop in parallel and outputs it at a required timing when the data satisfies a predetermined number of bits.