SU1264347A1 - Converter of pulse-code modulated signals to delta modulated signals - Google Patents

Abstract

The invention relates to computing. Its use for interfacing digital pulse-coded and delta-modulated data transmission channels allows an increase in the signal-to-noise ratio in the output signal. The converter contains input and output registers, a digital expander, a memory register and a calculator. Introduction of a synchronizer, a sign register, a code converter, and a driver with an output signal reduces the approximation error of a linearly varying signal. 3 nl

Description

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4 00 4: The invention relates to a computing technique and is intended for interfacing digital pulse-coded (PCM) and delta-modulated (yes) information transmission channels. The purpose of the invention is to increase the signal-to-noise ratio in the output signal. Figure 1 shows the block diagram of the proposed Converter; in fig. 2 - forms of approximating on-r yarns, corresponding to different structures of the output DM signal; on fig.Z - timing work: device. The PCM signal converter into DM signal contains input register 1, digital expander 2, memory register 3, subtractor 4, encoder 5, output register 6, regis 7 characters, output driver 8, synchronizer 9, information input 10, input 11 synchronization, clock input 12 and output 13. Code converter 5 is made on a programmable memory block, the address inputs of which are information inputs of code converter 5. For each address, it contains the corresponding distribution of yes-signal symbols in parallel ohm code, the width of which is determined by the ratio of the clock frequencies of da- and PCM-signals. In the case of the равно шест шест шест characters corresponding to an odd number of quantization steps S. Therefore, the entire range of input PCM samples, defined by subtractor 4, is divided into eight even subbands, the number of each of which corresponds to the binary code of the three most significant bits of the code 472 at the outputs of the reader 4, when the output of the encoder 5 is fed to the integrator the subsequent delta demodulator produces the approximate stresses shown in Fig. 2, where the numbers on the ordinate axis are the differences of the number of ones and the number of zeros of the corresponding distribution of DM symbols. Shaper 8 output signal can be performed on the element EXCLUSIVE OR. On fig.Z presents the following signals: a - clock pulses f (t) at the sixth output of the synchronizer 9; b - signal N (t) at the first output of register 1; in - signal H, (t) on the first output of register 3; t is the signal V (t) at one of the first outputs of the subtractor 4: d is the signal (t) at the second. output subtractor 4; e - l - signal signals H (t), E (t), M (t), P (t), B (t) and Q (t), respectively, on the second, the first, the BOM, the third, the seventh, the fifth and the even - vertically the outputs of the synchronizer 9; m signal D (t) on code register 6; n. - signal S (t) at the output of register 7; about - output DM signal U (t). The operation of the device is considered for the case when the frequency ratio of the clock signal f (t) at input 12 and the channel clock signal f (t) at input 11 is sixteen. The device works as follows. The standard compressed 32-k analog PCM signal is fed from input 10 to the information input of input register 1. Register 1 is designed to convert the serial code of each PCM sample of one communication channel into parallel code. To write to the clock and control inputs of input register 1, clock signals f (t) from PCM equipment and signal E (t) from synchronizer 9 are sent. The start of recording each PCM sample determines the start of the conversion cycle. After completing Writing the PCM sample code at the outputs of input register 1, NP (t), ..., N (t) signals appear in the parallel code. This information is stored in input register 1 for the entire conversion cycle, i.e. before recording the code of the next PCM sample. Since the PCM equipment has a standard compression characteristic, the signals from the outputs of register 1 are fed to the inputs of the digital expander 2, from the outputs of which the linear PCM sampling codes are removed (signals N (t), ... N / t. Next, the device performs the conversion linear PCM signals to linear DM signals. This happens as follows: The linear PCM sample codes (N (t), ..., N, (t)) are fed to both the first inputs of subtractor 4 and the inputs of register 3 memory The 3 memory register is used for storing the code (1-1) d, i.e. the previous selection of the linear AND CM. Thus, the first inputs of the subtractor 4 are given the code of the i-th sample, and the second inputs of the subtractor 4 are supplied with the code (1-1) of the second sample, which is removed from the outputs of the register 3 of the memory in the form of 4j signals, (t ), ..., H (t). After the control signal Q (t) arrives from synchronizer 9 to subtractor 4, the code ,, .., F (1) is subtracted from code N (t), ... , N, (t). This takes into account the signs of both PCM samples. So, with different signs of these. samples; to correctly determine the magnitude of their difference, subtractor 4 performs an arithmetic summation of the codes of both samples, and for the same samples, subtraction. The difference is determined; the subtractor 4 also determines the sign of this difference. The difference of codes determines the magnitude of the slope of the linearly varying voltage at the output of the linear DM decoder during the PCM cycle time, and the sign of the difference in the same time interval determines only the direction of change of this voltage. Formation of the DM signal produced with cycles equal to the PCM cycle. The difference of one i-th and (1-1) -th samples in each conversion cycle determines one of the 5 distribution structures of the DM-signal symbols in the parallel code recorded in the code converter. Each structure contains the same number of DM symbols. This number is determined by the ratio of the clock frequencies of the DM and PCM signals. Signals V, (t), ... , yj (t) from the first outputs of the subtractor 4 are fed to the inputs of the encoder 5 and are determined in binary code - eight addresses. At these addresses, signals D, (t), ..., D (t) appear in the parallel code at the outputs of the code converter 5. These signals correspond to one of the structures of digital DM symbols. To convert the information about the structure from the parallel code to. Serial serves as the output register 6. Structurally, this block consists of one 16-bit parallel-serial register, at the output of the 16th bit of which a one-bit additional register is connected. The output of the additional register is the output of this block, from which the digital DM signal D (t) is taken. All the structures of the DM symbols are recorded in the code converter 5 in such a way that they determine only the positive direction of change of the reconstructed analog signal. To get the negative direction of change of this signal, all the symbols of this structure should be inverted. This task completes the shaper 8 output signal. Subtractor 4, in addition to the difference of codes, determines at its second output the sign of this difference. the difference sign is positive, then the signal ((t) has a level O, and if the difference is negative, the signal Φ (t) has a level 1. The signal T (t) goes to a 7-character register, in which the level of the signal T (t) is remembered and is supplied to the second input of the output driver 8 simultaneously with the second clock signal of each converter cycle. This is due to the delay of the DM signal in the additional register bit 7. Thus, a digital signal Vd (t) of the linear DM at output 13 is generated. Thus, if in the prototype the approximation error of the linearly varying signal in the middle of one PCM cycle increases to values, (dmax U), (5 where the max. of the slew rate of the approximating voltage in the delta demodulator, and is the slew rate of the transmitted signal, then in the considered example of the converter this error does not exceed 2S. With an increase in the number of subranges into which the range of output is divided

signals from subtractor 4, this error is reduced.

Formula Iobre

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A pulse-coding signal converter into delta-modulated signals containing input and output registers, a digital expander, a subtractor and a memory register, whose signals are connected to the corresponding subtractive inputs of the subtractor, in order to increase the signal-to-noise ratio in the output signal , a code converter, a character register, an output driver and a synchronizer are entered in it, the first input of which is the device synchronization input, the second synchronizer input is combined with a clock input of the input register and is a clock input of the device, the information input of the input register in the StL information input of the device, the outputs of the input register are connected to the corresponding information inputs of the digital expander, the control input of the input register

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connected to the first output of the synchronizer, the second output of which is connected to the control input of the digital expander, the outputs of which are connected to the corresponding summing inputs of the subtractor and information inputs of the memory register, the control input of which is connected to the third output of the synchronizer, the fourth

10 the output of which is connected to the control input of the subtractor, the first and second outputs of which are connected respectively to the inputs of the code converter and the information input of the character register, the outputs of the code converter connected to the corresponding information inputs of the output register, the output of which is connected to the first input of the output signal generator, the control and clock inputs are connected respectively to the fifth and sixth outputs of the synchronizer, the seventh output of which is connected to the control input of the register of the sign, output d is connected to a second input of the output signal, whose output is the output device.

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Claims (1)

Claim Pulse-code converter - 5 muzzle signals to delta-modulated signals, containing input and output registers, a digital expander, a subtractor and a memory register, the outputs of which are connected to the corresponding subtracting inputs of the subtractor, characterized in that, in order to increase the signal-to-noise ratio in the output signal, a code converter, a sign register, an output signal conditioner and a synchronizer are introduced into it, the first input of which is the device synchronization input, the second synchronizer input is combined with the clock input of the input register is the clock input of the device, the information input of the input register is the information input of the device, the outputs of the input register are connected to the corresponding information inputs of the digital expander, the control input of the input register is connected to the first output of the synchronizer, the second output of which is connected to the control input of the digital expander, the outputs of which are connected to the corresponding summing inputs of the subtractor and the information inputs of the memory register the input input of which is connected to the third output of the synchronizer, the fourth output of which is connected to the control input of the subtracter, the first and second outputs of which are connected respectively to the inputs of the code converter and the information input of the sign register, the outputs of the code converter are connected to the corresponding information inputs of the output register, the output of which is connected to the first input driver output signal, the control and clock inputs are connected respectively to the fifth | and sixth outputs of the synchronizer, seventh the first output of which is connected to the control input of the sign register, whose output is connected to the second input of the output driver, the output of which is the output of the device. Fig! V / z z z // 4 / " Λ 9ig2