SU1416973A1 - Multichannel device for restoring continuous functions by discrete counts - Google Patents

Abstract

The invention relates to computing and can be used in automatic control systems. The purpose of the invention is to reduce hardware costs per channel. The device contains subtraction unit 1, control unit 2, memory unit 3, accumulating adder 4, summing unit 5, digital-to-analogue interpolation converters 6 (and extrapolations 7, -7. The device performs multi-channel signal processing in time-sharing mode, which is provided by control unit. In each channel of the device, a piecewise linear reconstruction of the signal is carried out from discrete samples arriving at the information input. 4, ill. § (L

Description

but

(UD

with

The invention relates to computing and can be used in automatic control systems.

; The purpose of the invention is to reduce hardware costs per channel. ; Figure 1 shows the layout of the device; Fig. 2 is a control block diagram; Figs 3 and 4 are time diagrams explaining the operation of the device.

The device contains a subtraction unit 1, a control unit 2, a memory unit 3, an accumulator adder 4, a summing unit 5, digital-analogue converters (D / A) interpolation, an extrapolation DAC, an address 8 output of the control unit, control outputs 9 -12 control unit, Control output group 20 of control unit, informative distribution input fl4 of accumulating adder, address output 15, input entry 16, address input 17, address generation, input 18 overwriting the feuds, first 19, second 20 single outputs, information input 22 devices , Input clock 23, the synchronization input 24, outputs 25, and outputs interpolation channels 26 channels extrapolation gn n tion.

The control unit 2 forms the element OR 27 ,, the first 28 and second 29 address drivers, the driver 30 pulses, the switch 31 codes and: the distributor 32 pulses.

: The device works as follows.

The ordinates of the reconstructed functions are encoded with L-bit parallel codes, which are fed to the information input of the device at the corresponding time slots. The ordinates corresponding to positive values of the functions are presented in the forward code, and the ordinates corresponding to negative values are presented in the additional code.

Block 1 of the subtraction is designed to obtain the codes of the differences between the codes fed to the input information bus, and the codes fed from the output 19 of accumulating adder 4 to the second input of the subtracting unit. Memory unit 3 stores difference codes obtained in subtractor 55 in cells with the address of the corresponding channel. The control unit provides synchronous operation of the device when

40

45

d

5 0 5 n

:

0 5

0

five

using clock pulses supplied to input 23 and frame synchronization pulses fed to input 24. The first address generator 28 generates the addresses of the memory cells of blocks 3 and 4 involved in the accumulation of ordinate codes of the restored functions on different channels. The second address generator 29 generates the channel addresses for reading the reference codes from the accumulating adder 4 and writing the ordinate difference codes obtained in block 1 into memory block 3. In general, these address drivers are binary counters with a clock input and the possibility of installation in O. Pulse generator 30 produces pulses corresponding to the notation of the end code processing of the current ordinate of the N channel and can be a decoder with a short pulse shaping circuit. The OR element 27 is designed to combine frame sync pulses and N-channel processing end pulses to zero the former 28. Distributor 32 pulses generates the following control pulses: SI1 pulses to write ordinate difference codes in memory block 3 (output 9) , CI2 pulses for recording the current values of the ordinate codes in accumulator 4 (output 10) 5 PPE pulses for strobe the address in memory block 3 and accumulator 4 (output 11), CI4 pulses for overwriting the current values, ordinate codes in accumulating adder (output 12), synchronizing pulses SC- (, N) for recording the curve: current values of the ordinates in the D / V path; measurement and control (output 13). It can be implemented. n, and a binary counter with tact input and the possibility of installation in O and on the decoder. The switch 31 connects the address, the outputs of the first or second address driver to the output 8 of the control unit. The accumulating adder is designed to obtain the I-Kddikh values of the ordinate codes in the approximation interval. The blocks of the accumulating adder generally contain L + M bits, where M is the number of additional bits determined by the permissible error of approximation of the straight line segments of the step-broken curve. Usually, M is determined from Equation 2 K, where K is the number of summation cycles in the approximation interval, Informational input 14 contains L bits connected to L younger digit inputs of the (L + M) -discharge adder. With such a connection, the difference code is divided by.

In subtraction block 1, a difference is generated between the input ordinate codes and the codes from the first group of distant outputs of the accumulating adder 4. The difference code is recorded at the address specified by the control unit in memory block 3. From the memory block t, in the presence of PPE pulses, the difference codes are formed, and the current values of the ordinates are generated at the outputs of the adder, at the accumulating adder and at the outputs of the summing block.

Let be , . In this case, the accumulating adder contains 11 binary bits. The signals from the output of the memory block 3 are fed to the inputs of the eight least significant bits of the accumulating adder. The three groups of outputs of the accumulating adder are combined into one group of outputs (this is true only in the case under consideration), removed from the eight most significant bits.

In the initial state, I accumulate

the difference difference code is read off and feeds-2o Sch the adder 4 and the memory block 3 are reset, so the feedback circuit

to the first input of the summing unit 5 and to the input of the accumulating adder, where the current values of the ordinate codes are obtained. In the second group of bit outputs of the accumulating adder 4, codes are generated corresponding to the values of the functions reconstructed by the step-linear interpolation method. These codes are rewritten using write pulses to the corresponding D / A converters 6.

In block 5, the codes formed on the third group of bit outputs of block 4 and codes whose values correspond to the first differences of the interpolated functions coming from block 3 are summed up. Codes are formed at its output, corresponding to

 Corresponding values of functions reconstructed by the step-linear extrapolation method. These codes are rewritten into the corresponding D / A converters 7, where they are converted into analog signals.

Consider the principle of operation of the control unit when the number of channels is N 2 and the number of clock cycles in the approximation interval K 8. With N 2, the address output is transformed into a single signal line. At times tp, the frame synchronization pulse control unit 2 is set (FIG. 36) to the initial state. At times t, when the pulses CI4 and PPE coincide, the codes are overwritten from the corresponding memory blocks of the accumulating sum

, matora4 in its buffer register. In mo35

During the first polling period, codes equal to zero arrive at the addresses of all the cells at the second input of block 1 of the subtraction, and the code equal to eight conventional units 00001000 is sent to the first one.

After the input data bus receives a parallel code of the first channel corresponding to a single sample, the amplitude of which is, for example, eight arbitrary units, and the first control input of memory unit 3 receives a pulse SI1 (at time t) in the cell The difference code 00001000 is recorded with the first channel address. This difference code value on the first channel is stored in the memory block until the arrival time tjp, the next value of the input code on the first channel and the new difference code value is received. At the moment t, the arrival of the pulse CI2 on the first control: the input of the accumulating adder in the cell with the address of the first channel is written down the code 00000001. Thus, in the adder 4 the value of the difference obtained is divided by 8 (generally 2). This is due to the fact that the input signals are fed to the 8 least significant bits, and the output signals are removed from the eight most significant bits of the accumulating adder. With the arrival of the next SI2 pulses coinciding with SC1 (at the moments, 40

45

50

55

t, -,), the value of the code at the output of the accumulating adder at this address increases according to a linear law, and at tn the value of the code is

during the first polling period, codes equal to zero arrive at the addresses of all the cells at the second input of subtraction unit 1, and the code equal to eight conventional units 00001000 arrives at the first one.

After the input data bus receives the parallel code of the first channel corresponding to a single sample, the amplitude of which is, for example, eight arbitrary units, and the first control input of memory unit 3 receives a pulse SI1 (at time t), in the cell with the first channel address records the difference code 00001000. This difference code value on the first channel is stored in the memory block until the arrival time tjp, the next value of the input code on the first channel and the new difference code value is received. At the moment t, the arrival of the pulse CI2 on the first control: the input of the accumulating adder in the cell with the address of the first channel is written down the code 00000001. Thus, in the adder 4 the value of the difference obtained is divided by 8 (generally 2). This is due to the fact that the input signals are fed to the 8 least significant bits, and the output signals are removed from the eight most significant bits of the accumulating adder. With the arrival of the following impulses SI2, coinciding with the SC1 (at the moments

t, -,), the value of the code at the output of the accumulating adder at this address increases according to a linear law, and at tn the value of the code reaches 10

15

20

the maximum value is eight units. The value of the codes from the output of the accumulative

adder pulses CK1 are recorded in the first DAC 6, in which the conversion of a sequence of codes occurs, into an ascending stepwise linear analog signal (Fig. 4e). This is the formation of the first section of the impulse transient function of the device along the first channel of the measuring path. At time tj, the first input of block 1 of the subtraction receives a code equal to zero from the information bus, and the second corresponds to a code corresponding to eight units, consequently, the pulse CI enters the cell of the 3-ty block with the address of the first channel code spread, equal to (-8) edrschitsam. The resulting difference code value is stored until t. At time t, the content of the accumulating adder at the address of the first channel is reduced by 1 unit, at time t j by 2 units, and so on. At time t, the accumulator cm at the address of the first channel is zeroed. The linearly decreasing code values are converted in the DAC 6 into a stepwise linear analog signal decreasing in amplitude. This is how the second section of the device’s impulse response function is formed over the first interpolation channel,

At the time tjp, the two inputs of the subtractor are equal to zero, so the zero value of the difference is written to the memory at the address of the first channel. Therefore, on the first channel, the entire circuit returns to its original state.

The impulse transition function in the second channel of the measurement path is formed similarly. The difference is that the moment of the beginning of the formation coincides with the point t., And

the end time is with the point t, ". About- „

ci50

formation process is synchronized

sequence CK2.

Thus, at the outputs of the device 25, the OTs form pulse transition functions, having the form of isosceles triangles, the sides of which are formed by the method of stepwise approximation of straight segments. The duration of these triangles is 25

thirty

35

40

55

This is 2T, where T is the polling period of the channels. The height of the triangles is proportional to the value of the input device codes. Consequently, with the periodic input to the input of the codes of channel discrete samples at the outputs 25 of the device, the signals are restored by step-linear interpolation.

Consider the formation of a signal at the outputs of the device 26.

At the output of the summing unit 3, codes of the current values of the sums obtained from the values of the difference codes taken from the outputs of the memory unit 3 and the accumulative adder 4 are formed. On the (t, tj7) DL segment of the first channel, this sum varies from 8 to 16 and (t ,,, t 5 from O to -8. For the second channel, this amount varies from 8 to 16 in the segment (t,), and from O to -8 in the segment (t, tji). pulsed transient functions of the first (Fig. 4, h) and second (Fig. 4) ropes. The analysis shows that these functions are obtained by the method of stepwise approximation of the functions th linear extra- half torus.

Thus, the device performs independent signal processing on N channels with interpolated and extrapolated values.

Claims (1)

Invention Formula „ 0 0 five A multichannel device for retraining discrete-sample functions containing the first digital-analog interpolation converter, the first digital-analog extrapolation converter accumulating the accumulator, the memory block, the summing block and the subtractor whose first input is connected to the input data bus of the device, and the output is connected to the information input of the memory block, the output of which ;, is connected to the first input of the summing block and the information input of the accumulating adder, the first, The torus and the third group of bit outputs of which are connected respectively to the second input of the subtractor, the information input of the first digital-to-analog interpolation converter and the second input of the summing block, the output of which is connected to the information input of the first digital-to-analog extrapolation converter, the outputs of the first digital-analog interpolation converters and extrapolation are the first outputs, respectively, of interpolating and extrapolating the device, characterized by the fact that, in order to reduce equipment costs per channel, it contains second to Nth digital-analogue interpolation converters, second to Nth digital-analogue extrapolation converters, and a control unit containing the OR element, the first and second address drivers, the pulse distributor, the pulse driver and a code switch, while the output of the code switch is connected to the address inputs of the memory block and accumulating adder, the information inputs of the digital-to-analog converters of the interpolation from the second to the Nth link with the second group of bit outputs of the accumulating adder, the output of the summing block is connected to the information inputs of digital-to-second extrapolation transducers from the second to the Nth, the input clock of the device’s pulses is connected to the clock inputs of the first and second address formers and the pulse distributor, the device clock input connected to the first input of the OR element and the installation inputs to the initial state of the pulse distributor and the second address generator, the output of the OR element is connected to the input of the device The initial state of the first address generator, the output of which is connected to the first information input of the switch and via the pulse former, is connected to the second input of the OR element, the output of the second address generator is connected to the second information input of the code switch, the control input of which is connected to the first output of the distributor pulses, the second output of which is connected to the recording input of the memory block, the third output to the recording input of the accumulating adder, the fourth output to the inputs of the gate of the address of the memory block This output accumulator with the rewriting input of the accumulation adder codes, each i-th output of the group of N outputs of the pulse distributor is connected to the inputs of the i-x digital-analogue interpolation and extrapolation converters.   K, X, 4s ,, 4 fO "H C3 C5 fVi W one one one (t t2o (t, a () () fso (teo III I nil MM I II I II Ml II I III III II I in I li I g t.i:. (T. /./X.)y. , . ../y ({(, (n ; I Lls t . h figm Compiler G.Osipov Editor L.Pcholinska Tekhred L.Oliynyk Proofreader V.Romanenko Order 4065/46 Circulation 704 VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 I in I li I ./y ; I Lls t : /. Subscription