SU930656A1 - Multichannel analogue-digital converter - Google Patents

Description

The invention relates to a pulsed technical support in which can be used in computing in computer communication systems with various objects of control. A multichannel analog-to-digital converter is known, containing two buffer memories, a & switch, a co-converter, whose input is connected to a code register, divided into two parts: the high-order register is a counter-register, the low-order register is a register coding, and the output - with the inputs of the comparison circuits; and the second inputs of the KOTpfbix arrive; An analog analogue magnitude, a sequential control circuit and a bit-coded control circuit. The disadvantage of the device is its low speed and the presence of a switch that connects in turn all the channels for converting and writing to the low-order buffer memory, as well as the necessary This can be done periodically with a coarse coding step, since the measured analog quantity can drastically reduce its complexity. A multichannel analog-to-digital converter (ADC) is known, which contains n channels, each of which is formed by a comparison unit, the output of which is connected to one of the trigger inputs connected to the channel number code generation unit, the pulse generator, the counting input of which is connected to the counting the counter input, the outputs of which are connected to the inputs of the digital-analog converter, the output of the digital-analog converter is connected to the second input {and comparison blocks, the output switch of the on-off signals, the inputs which is connected to the channel number code generation unit, and the outputs to the corresponding second trigger inputs, the control unit, which is connected via bus i to the channel number code generation unit, via dvuhgomm switch of two-point signals, through the clock bus with pulse generator, The bus output of one of the bits of the counter is with counter 2. The disadvantage of the multichannel analog digital converter is low speed, since after each successive operation the comparison block is necessary o perform after-. Conduct polling of the status of the triggers of all channels and write the counter code into the corresponding cells of the processor's memory, which leads to an increase in the total conversion time. The purpose of the invention is to enhance the quick action. The goal is to achieve that in a multichannel analog-to-OBE converter, which contains a pulse generator, the output of which is connected to the pulse input of the control unit, the first output of which is connected to the first input of the counter, the outputs of which are connected to the inputs of the O-analogue converter, output which is connected to the first inputs of the comparison blocks, a priority interrupt block, a random access memory, a multi-input element. OR, a channel number identifier, loop triggers, and OR elements, The cycle trigger outputs are respectively connected to the second inputs of the comparison units, the outputs of which are connected to the potential inputs of the priority interrupt unit and the inputs of the OR multi-input element, whose output is connected to the first input of the control unit, and the second input to the first output of the priority interrupt unit, the second the output of which is connected to the first inputs of the random access memory and the channel number decoder, the second input of which is connected to the second output of the control unit, the outputs of the decoder The channel channel is connected to the first inputs of the OR elements, the second inputs of which are connected to the third output of the control unit, the outputs of the OR elements are connected to the first inputs of cycle triggers, the second inputs of which are connected to the fourth output of the control unit, and the third input of the control unit is connected to the output of the counter and the second input of the random access memory, the third input of which is connected to the fifth output of the control unit and the first input of the priority interrupt unit, the output of the operational storage device of the connection They are connected to the interface buses to which the second, third, fourth, and fifth inputs of the priority interrupt block, the fourth and fifth inputs of the control unit, and the fourth input of the random access memory are connected. FIG. 1 shows the structural electrical circuit of the device in FIG. 2 is a preemption block diagram; in fig. 3 is a diagram of an operative recording device; in fig. 4 is a control block diagram. The device contains an element OR cycle triggers, comparison units, a digital-analog converter (D / A converter) 4, a priority interrupt block 5, a multi-input element OR 6, a channel number decoder 7, a counter 8, a control block 9, a random access memory (RAM) pulse generator 11, connected by bus 12 to block 9, which is connected by bus 13 to counter 8, bus 14 to decoder 6, bus 15 to one of the inputs of the elements OR 1x) -1, and counter 8, bus 16 to the installation input I triggers 2 -, - 2, bus 17 - with a block (LV 5 and RAM 1O, tires 18 and 19 - with tires int The interface 20, the counter 8 is connected by bus 21 to the DAC 4, blocks 9, RAM 1O, DAC 4 is connected to one at the inputs of the blocks, to BTOfftie whose inputs connect the sources of convertible signals, the inputs of the blocks are connected to the block 5 and the multiple input element OR 6, the output which bus 22 is connected to blocks 9, block 5 by bus 23 is connected to blocks 9, bus 24 - to RAM 10 and decoder 7, tires 25-29 - to interface 2O buses, aesh frator 7 exits 1- and connected to the second inputs of the OR elements , the outputs of which are connected to the installation inputs of the flip-flops connected to the third input give blocks, random access memory 1O busbars 30, 31 connected to the interface unit 20. The tires preemption ( "u}. 2) consists of a register 32 for interrupt requests, a current priority register 33, an interrupt blocking trigger 34, a priority comparison unit 35, OR elements 36 and 37, AND elements 38-40, a current priority register 41, an interrupt trigger 42.

OneparviBHoe memory device (Fig. 3) contains a data register 43, a write address decoder 49, a drive 45, an address decoder 46 read; a buffer amplifier 47.

The control unit (Fig. 4) contains a trigger 48, an element AND 49, a decoder 5O zero, a frequency divider 51, a pulse shaper 52, elements AND 53 and 54, a trigger 55, elements And 56 and 57

The device works as follows.

I

The entire conversion process takes place during a one-time change of the compensating signal from its minimum value to the maximum, then the conversion time is repeated. When a signal is fed from the bus interface 2O to bus 18 to the control unit, a trigger 48 is turned on (FIG. 4), allowing clock pulses from generator 11 to pass through bus 12 through AND 49 to divider 51 and another (EN 57. Pulsed frequency is fed to the forms 52, which, via bus 15, through the elements OR g, are set & triggered and counted into O. 8. The bits of the counter 8 outputs through bus 21 go to block 9 to a decoder, 50, forming a start pulse using bus 16 to set triggers in, the output signal from which, entering the third block inputs, p xp {parrying two signals: reference, in the form of stepwise-changing of the highest voltage, and measured. The second pulse through the And 56 element at resolution on the bus 23 from block 5 goes to the counting input of the counter 8 on the bus 13, setting the next step at the output of a digital-to-analog converter 4, delivered to the second inputs of the blocks, to the first inputs of which the sources of the converted signals are connected. The moment of conversion over a particular channel is the moment of the signal change at the outputs of the blocks, the corresponding channel, the signal from which is sent to the corresponding memory register trigger 32 for interrupt requests with an encoder (Fig. 2) blues 5. From the output, 32 interrupt requests are received at block 35, where their values are compared with the current priority, the level of which is stored in register 33. The request level information stored in

the register 32 enters the register 41. The third signal from the driver 52 (FIG. 4) of block 9 in the presence of an enable signal coming from the bus 22 of the multi-input element OR 6 through the element 53 sets the trigger 55 to allow the passage of T61CT pulses through the bus 17 unit 5 for polling register 41, which generates a code for the channel number supplied by bus 24 to decoder 7 where the synchronous pulse simultaneously arrives on bus 14 from unit 9 and to decoder 44 (FIG. 3) RAM 10 for recording information with the counter 8 coming through the bus 21 va re ISTR 43, clock pulse on the bus 17 with a block 9.

In order to prevent a change in the signal at the outputs of the blocks at the next voltage level coming from the digital-to-analog converter 4 for a given channel, the channel number pulse from the decoder 7 goes to the corresponding OR element and sets the trigger to Oh, forbid further conversion to the end of the cycle.

After recording in RAM 1O the information of the counter 8 corresponding to the given counting clock for the channels that changed the signal at the output of one of the blocks (,, the resolution of the analysis on bus 23 from block 5 allows the transition to the next step of compensating voltage and further conversion. If At this voltage step, there was no request for scattering, then the signal from the multi-input element OR 6 does not flow to BL1G 9 via bus 22, which does not emit sync pulses through buses 17 and 14, but allows bus 23 from block 6 to pass s next pulse fsfmirovatel 52 via the bus 13 to

the counting input of counter 8, which increments the output code by one.

Claims (2)

To select information given by the canals during the time of the strobe interruption on the bus 29, a clock is sent from the interface bus 2O over the bus I 29 to hold the request signal in register 32 before sending information about the current priority on cs of 25 with local signals of the priority level sampling away 26 and recording resolution via bus 27. Information of this channel is recorded in the random access memory 10 by a signal fed through bus 17, read to the address on lUHHax 30 and transmitted via buses 31 via interface buses 20 to the input information tional npoueccqpa computer bus. The end of the conversion comes on the signal coming from the buses of the interface 20 via bus 19 to the trigger 48 of block 9. Thus, o6pa3c vt, there is no need to interrogate all channels at a given counting clock, and only those that send a signal at the output of the comparison unit it is possible to monitor and measure only a certain group of channels depending on the priority and the ability of a computer to access random access memory in any way to read information on any group of channels. Claim 1: A multichannel analog-to-digital converter containing a pulse generator, the output of which is connected to the pulse input of the control, the first output of which is connected to the first input of the counter, which connects to the inputs of the digital-analog converter, the output of which is connected to the first inputs of the comparison blocks characterized in that, in order to improve speed, the blocks of the priority interrupt, the input element OR, the memory device, the decoder are entered channel channel, cycle triggers and ment) OR, the cycle trigger outputs are respectively connected to the second inputs of the comparison blocks, the outputs of which are connected to the potential inputs of the priority interrupt unit and the inputs of the multi-input element OR whose output is connected to the first input of the control unit, and the second input to the first output of the priority interrupt unit, the second output of which is connected to the first inputs of the random access memory and the decoder of the channel number, the second input of which is connected to the second output block ynpai laziness, the decoder outputs the channel number are connected to first inputs of OR elements, the second inputs of which are connected to the third output of the control unit, outputs of OR elements are connected to first inputs of flip-flops cycle, second inputs connected to the fourth output of the control unit. the third input of the control unit is connected to the output of the counter and to the second input of the random access memory, the third input of which is connected to the fifth output of the control unit and the first input of the security interrupt unit, the output of the operational memory is connected to the interface buses to which the second, third, the fourth and fifth inputs of the priority interrupt unit, the fourth and fifth inputs of the control unit, and the fourth input of the random access memory. Sources of information taken into account during the examination 1. USSR author's certificate No. 229О57, cl. N OZ K 13/17, 1967. 2. Kagan B.M. A.I. Voitelev, Luky L.M. Communication systems of UVM with control objects in industrial control system. M., Soviet radio. 1978, p. 166, fig. 4.25 (prototype). 4f "I 4G