SU1216652A1 - Recorder - Google Patents

Abstract

The invention relates to a measurement technique and can be used in recording devices for continuous recording, such as memory oscilloscopes, alarm recorders, etc. The purpose of the invention is to increase the recording accuracy, reduce the accuracy requirements of a digital-to-analog converter (DAC) and simplify its design. . The recorder contains a DAC 1, a comparator 2, terminals 3, memory elements 4-7, an address counter 8, a driver of 9 pulses, a shift register 10, a generator of II clock pulses, resistors 12-15, a control terminal I6, sources 17 and 18 of a single and zero signals, respectively, elements of the DRGSN SURNER OR 19-21. The logger contains the logic of the bit balancing method. The error in the weight of each bit is taken into account by choosing the weight of the subsequent lower bits, while the weight of the last minor bit can be arbitrarily small and is determined by the requirements for the resolution of the recorder. I il.

Description

The invention relates to a measurement technique and can be used in recording devices for continuous recording, such as memory oscilloscopes, alarm recorders, etc.

The purpose of the invention is to simultaneously increase the registration accuracy, reduce the requirements for the accuracy of the D / A converter and simplify it.

The drawing shows the proposed registrar.

The recorder contains a digital-to-analog converter (CAC), a comparator 2, one input of which is connected to the input terminal 3, and a second input of the comparator 2 - with the output of the D / A converter 1, elements 4-7 of memory, counter 8 of the address, outputs of which are connected to adrens mn inputs element-. 4-7 memory, shaper 9 itM pulses, shift register 10; pulse generator shaper output 9 is connected to the resolution input of address counter 8 and set input into shift register unit W, generator 1) clock pulses, the output of which is connected to clock inputs of forms 9 pulses, an address counter 8 and a shift register 10, the high-order input of the digital counter 1 is connected to the output of the corresponding memory element 4, resistors 52-15, the control input 16 connected to the input of the zero register 0 for the shift, the current indicator G / single signal and source IR 18 zero signal, the elements of the exponential or j 92f. I

The inputs of the 4-7 memory are connected together and connected to the output of comparator 2, the first output of the shift register 10 is connected to the Record-read input of the A element of the high-order memory, the other outputs of the shift register 10 are connected to the corresponding Record-Read inputs. elements. 5-7 memory of lower bits, outputs of elements 5-7 of memory through elements EXCLUSIVE OR 19 2.1 are connected to the corresponding discharge of the digital indicator, the remaining input of each element EXCLUSIVE OR 19-21 is connected to the input Record-reading of elements 6, 5 and 4 memories of the previous senior bit, respectively, but outputs of elements 4-7 of memory of

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the cut resistors 12-15 are connected to the source 17 of a single signal; the input of the shift register 10 is connected to the source 18 of a zero signal,

5 D / I output is connected to output terminal 19.

The proposed recorder works as follows.

In the recording mode, the recorded signal is fed to the input terminal 3, and the Log signal is sent to the control terminal. ABOUT.

Shaper 9 pulses with a signal I sets the outputs

(5 shift register in 1 and opens the resolution input of the address 8. address. At the same time, the signal of the clock pulse generator I 1 sets at the output of the address 8 counter the address code 20 that goes to the address inputs of memory elements 4-7. Signal 1 s the outputs of the register 10 shift is fed to the input Record-read elements 4-7 memory,

25 puts them into Record mode. At the outputs, the terminals of the memory elements are set to I via resistors 12-15 by the source 17 of a single signal. At the input of the DAC 1 comes

30, code 1000, its output voltage is compared with the analog input signal by comparator 2, the result of the comparison is supplied to tia memory elements 5-7 and stored in them. By

termination of the signal f at the output of the pulse generator 9, the shift register 10 is unlocked and with the arrival of the next signal of the clock pulse generator JI, the first output of the shift register 10 appears

 ABOUT

served on his

input source 18 zero signal.

The signal O from the first output of the shift register 10 transfers the memory element 4 to the Read mode and at its output a result appears comparing the weight of the most significant bit of the DAC 1

the value of the analog signal at terminal 3. Next, the EXCLUSIVE OR 19 is transferred by the signal O to the repeater mode and 1 from the output of the memory element 5 is fed to the input of the DAC 1. The output voltage of the DAC I is again compared with the analog signal by the comparator 2, the result of comparison with its output is supplied on elements 4-7 of memory (element 4

m is transferred to the mode - Reading and does not perceive the input signal). The next signal of the generator I 1 clock pulses writes O to the second output of the shift register Yu, with the memory element 5 being transferred to read mode, and the EXCLUSIVE ALTER OR 20 to the Repeater. The result of comparing the two most significant bits of the D / A converter 1 is stored in memory elements 4 and 5, 1 from the output of memory element 6 through the EXCLUSIVE OR 20 is fed to the input of the third bit of the DAC 1, and the first and second bits serve the contents of elements 4 and 5 memories.

The output signal at the output of the D / I converter is compared with the analog signal by the comparator 3, the result of the comparison is stored in the memory element 6. The subsequent bits of the D / I converter sequentially compare the output with the analog signal, and the results are stored in the memory elements of the lower bits. After all the outputs of shift register 10 are set to O, the conversion is complete. Elements 4–7 of the memory store the code of the number balancing the weights of the bits of the ATP I input analog signal.

A new conversion cycle begins after the next signal 1 is supplied by the shaper 9 pulses to the input of the resolution of the address counter 8, which increases the address code by one. During the recording process, the contents of the address counter 8 are cycled from O to overflow, and the information in the cells of the 4-7 memory is also cyclically replaced. The termination of the registration of the signal and its reproduction occurs after training 1 at the control terminal 16, while the outputs of the shift register 10 are blocked in the state O.

Signals O from the outputs of the register. elements 4–7 of memory are read into the read mode, and elements of the TRIMMER ALSO 19–21 are in the repeater mode. The signals of the generator of 9 pulses and the generator of 11 clock pulses alternately in the same order as in the recording, change the address codes to the output of the counter 8 addresses, resulting in the outputs of the elements 4-7 memory alternately set

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Analog signal codes are stored in memory elements 4-7. The DAC 1, according to the codes from the outputs of the 4-7 memory elements, generates the values

5 analog value, reproduced recorded analog value over time. Since DAC 1 participates in analog-digital, and then it is also in digital-to-analogue conversion) 0, then, in general, the specific weight of each bit is not significant, but its constancy during the time between recording and play

15 izvestnom. However, since the proposed registrar incorporates the logic of the bit balancing method, a necessary condition for normal operation is

20, so that the weight of each bit is no more than the sum of the weight of the subsequent lower bits, taking into account the possible variations in the weight of the older and younger bits.

25

Thus, the error in the weight of each bit is taken into account by choosing the weight of the subsequent lower bits, while the weight of the last one is lower.

The Q th output can be arbitrarily small, and is determined by the requirements for the resolution of the recorder.

35

Claims (1)

Invention Formula A recorder containing a comparator, the first input of which is connected to the input terminal, and the second - with the output of the digital-to-voltage converter, memory elements whose address inputs are connected to the outputs of the address counter, the input of which is connected to the input of the 1 shift register and the output pulse generator, clock generator, - connected to the clock inputs of the counter addressg: and shift register, input. the control terminal is connected to the input home setup in the About shift register. resistors, a source of a single signal, a source of a zero signal, characterized in that, in order to increase the registration accuracy, elements of a NSWLORTER OR are introduced into it, and the inputs of the memory elements are connected together and connected to the output of the comparator, the second 51216652 6 the input of which is connected to the output directly to the first input of the digital-analog terminal, the outputs of the shift-converter register, and the outputs are connected to the inputs of the Record-reading of the tal memory elements through the memory elements and, except for the lower inputs of the elements, EXCLUDE OR bit, to the first # 1 inputs of the elements 5 are connected to the rest of the input DISCOVER ALREADY OR, the output of the element by the pair of digital-to-analogue conversion of the most significant bit is connected by navatel.